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fixes the memory barrier for SCRQ/CRQ entry
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| Archived =
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| 2 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[net,3/3] ibmvnic: Ensure that CRQ entry read/write are correctly ordered
fixes the memory barrier for SCRQ/CRQ entry
-
-
-
2021-01-21
Lijun Pan
New
[net,1/3] ibmvnic: rework to ensure SCRQ entry reads are properly ordered
fixes the memory barrier for SCRQ/CRQ entry
-
-
-
2021-01-21
Lijun Pan
New