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Show patches with
: Submitter =
Yash Shah
| State =
Action Required
| Archived =
No
| 4 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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S/W/F
Date
Submitter
Delegate
State
[v2,2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
[v2,1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
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2020-11-30
Yash Shah
New
[2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
SiFive DDR controller and EDAC support
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2020-08-25
Yash Shah
New
[2/3] riscv: dts: fu540-c000: define hart clocks
Dynamic CPU frequency switching for the HiFive
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2020-06-16
Yash Shah
New
[v2,2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled
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2020-01-03
Yash Shah
New