| Message ID | 1592308864-30205-3-git-send-email-yash.shah@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Dynamic CPU frequency switching for the HiFive | expand |
On Tue, Jun 16, 2020 at 8:01 PM Yash Shah <yash.shah@sifive.com> wrote: > > Declare that each hart defined in the FU540 DT data is clocked by the > COREPLL. This is in preparation for enabling CPUFreq for the > FU540-C000 SoC on the HiFive Unleashed board. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > Any idea of why this patch was not applied? Regards, Bin
On Wed, Jun 16, 2021 at 6:17 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Tue, Jun 16, 2020 at 8:01 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > Declare that each hart defined in the FU540 DT data is clocked by the > > COREPLL. This is in preparation for enabling CPUFreq for the > > FU540-C000 SoC on the HiFive Unleashed board. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > Any idea of why this patch was not applied? There was a decision not to upstream CPUFreq stuff for Unleashed thus the whole series probably was abandoned. Not all Unleashed can operate in a stable way at 1.4GHz. IIRC other issues could exist. See Palmer reply for the whole series. david > > Regards, > Bin > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Jun 16, 2021 at 11:14 PM David Abdurachmanov <david.abdurachmanov@gmail.com> wrote: > > On Wed, Jun 16, 2021 at 6:17 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > On Tue, Jun 16, 2020 at 8:01 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > > > Declare that each hart defined in the FU540 DT data is clocked by the > > > COREPLL. This is in preparation for enabling CPUFreq for the > > > FU540-C000 SoC on the HiFive Unleashed board. > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > --- > > > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > > Any idea of why this patch was not applied? > > There was a decision not to upstream CPUFreq stuff for Unleashed thus > the whole series probably was abandoned. Not all Unleashed can operate > in a stable way at 1.4GHz. IIRC other issues could exist. See Palmer > reply for the whole series. Thanks, but the DT change is still valid, and should be upstreamed. Regards, Bin
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 7db8610..735e102 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -30,6 +30,7 @@ i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&prci PRCI_CLK_COREPLL>; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -55,6 +56,7 @@ riscv,isa = "rv64imafdc"; tlb-split; next-level-cache = <&l2cache>; + clocks = <&prci PRCI_CLK_COREPLL>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -79,6 +81,7 @@ riscv,isa = "rv64imafdc"; tlb-split; next-level-cache = <&l2cache>; + clocks = <&prci PRCI_CLK_COREPLL>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -103,6 +106,7 @@ riscv,isa = "rv64imafdc"; tlb-split; next-level-cache = <&l2cache>; + clocks = <&prci PRCI_CLK_COREPLL>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -127,6 +131,7 @@ riscv,isa = "rv64imafdc"; tlb-split; next-level-cache = <&l2cache>; + clocks = <&prci PRCI_CLK_COREPLL>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc";
Declare that each hart defined in the FU540 DT data is clocked by the COREPLL. This is in preparation for enabling CPUFreq for the FU540-C000 SoC on the HiFive Unleashed board. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++ 1 file changed, 5 insertions(+)