| Message ID | 1607403341-57214-8-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Accepted |
| Commit | 57985788158a5a6b77612e531b9d89bcad06e47c |
| Headers | show |
| Series | [v2,1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC | expand |
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built FU740-C000 Soc > around the SiFIve U7 Core Complex and a TileLink interconnect. > > This file is expected to grow as more device drivers are added to the > kernel. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++ > 1 file changed, 293 insertions(+) > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > new file mode 100644 > index 0000000..eeb4f8c3 > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > @@ -0,0 +1,293 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 SiFive, Inc */ > + > +/dts-v1/; > + > +#include <dt-bindings/clock/sifive-fu740-prci.h> > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "sifive,fu740-c000", "sifive,fu740"; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + ethernet0 = ð0; > + }; > + > + chosen { > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + compatible = "sifive,bullet0", "riscv"; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <16384>; > + next-level-cache = <&ccache>; > + reg = <0x0>; > + riscv,isa = "rv64imac"; > + status = "disabled"; > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu1: cpu@1 { > + compatible = "sifive,bullet0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <40>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <40>; > + mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > + reg = <0x1>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu2: cpu@2 { > + compatible = "sifive,bullet0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <40>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <40>; > + mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > + reg = <0x2>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu3: cpu@3 { > + compatible = "sifive,bullet0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <40>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <40>; > + mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > + reg = <0x3>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu3_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + cpu4: cpu@4 { > + compatible = "sifive,bullet0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <40>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <40>; > + mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > + reg = <0x4>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + cpu4_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + plic0: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + #address-cells = <0>; > + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > + reg = <0x0 0xc000000 0x0 0x4000000>; > + riscv,ndev = <69>; > + interrupt-controller; > + interrupts-extended = < > + &cpu0_intc 0xffffffff > + &cpu1_intc 0xffffffff &cpu1_intc 9 > + &cpu2_intc 0xffffffff &cpu2_intc 9 > + &cpu3_intc 0xffffffff &cpu3_intc 9 > + &cpu4_intc 0xffffffff &cpu4_intc 9>; > + }; > + prci: clock-controller@10000000 { > + compatible = "sifive,fu740-c000-prci"; > + reg = <0x0 0x10000000 0x0 0x1000>; > + clocks = <&hfclk>, <&rtcclk>; > + #clock-cells = <1>; > + }; > + uart0: serial@10010000 { > + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; > + reg = <0x0 0x10010000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <39>; > + clocks = <&prci PRCI_CLK_PCLK>; > + status = "disabled"; > + }; > + uart1: serial@10011000 { > + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; > + reg = <0x0 0x10011000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <40>; > + clocks = <&prci PRCI_CLK_PCLK>; > + status = "disabled"; > + }; > + i2c0: i2c@10030000 { > + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; > + reg = <0x0 0x10030000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <52>; > + clocks = <&prci PRCI_CLK_PCLK>; > + reg-shift = <2>; > + reg-io-width = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + i2c1: i2c@10031000 { > + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; > + reg = <0x0 0x10031000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <53>; > + clocks = <&prci PRCI_CLK_PCLK>; > + reg-shift = <2>; > + reg-io-width = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + qspi0: spi@10040000 { > + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10040000 0x0 0x1000>, > + <0x0 0x20000000 0x0 0x10000000>; > + interrupt-parent = <&plic0>; > + interrupts = <41>; > + clocks = <&prci PRCI_CLK_PCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + qspi1: spi@10041000 { > + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10041000 0x0 0x1000>, > + <0x0 0x30000000 0x0 0x10000000>; > + interrupt-parent = <&plic0>; > + interrupts = <42>; > + clocks = <&prci PRCI_CLK_PCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + spi0: spi@10050000 { > + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10050000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <43>; > + clocks = <&prci PRCI_CLK_PCLK>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + eth0: ethernet@10090000 { > + compatible = "sifive,fu540-c000-gem"; "sifive,fu740-c000-gem"? > + interrupt-parent = <&plic0>; > + interrupts = <55>; > + reg = <0x0 0x10090000 0x0 0x2000>, > + <0x0 0x100a0000 0x0 0x1000>; > + local-mac-address = [00 00 00 00 00 00]; > + clock-names = "pclk", "hclk"; > + clocks = <&prci PRCI_CLK_GEMGXLPLL>, > + <&prci PRCI_CLK_GEMGXLPLL>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + pwm0: pwm@10020000 { > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > + reg = <0x0 0x10020000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <44>, <45>, <46>, <47>; > + clocks = <&prci PRCI_CLK_PCLK>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + pwm1: pwm@10021000 { > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > + reg = <0x0 0x10021000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <48>, <49>, <50>, <51>; > + clocks = <&prci PRCI_CLK_PCLK>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + ccache: cache-controller@2010000 { > + compatible = "sifive,fu740-c000-ccache", "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <2048>; > + cache-size = <2097152>; > + cache-unified; > + interrupt-parent = <&plic0>; > + interrupts = <19 20 21 22>; > + reg = <0x0 0x2010000 0x0 0x1000>; > + }; > + gpio: gpio@10060000 { > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; > + interrupt-parent = <&plic0>; > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, > + <30>, <31>, <32>, <33>, <34>, <35>, <36>, > + <37>, <38>; > + reg = <0x0 0x10060000 0x0 0x1000>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + clocks = <&prci PRCI_CLK_PCLK>; > + status = "disabled"; > + }; > + }; > +}; Regards, Bin
> -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 10 December 2020 19:05 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > FU740-C000 Soc > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > This file is expected to grow as more device drivers are added to the > > kernel. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > +++++++++++++++++++++++++++++ > > 1 file changed, 293 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > new file mode 100644 > > index 0000000..eeb4f8c3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > @@ -0,0 +1,293 @@ ... > > + plic0: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + #address-cells = <0>; > > + compatible = "sifive,fu540-c000-plic", > > + "sifive,plic-1.0.0"; > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? That's because it is not required. There won't be any difference in driver code for FU740 plic. ... > > + eth0: ethernet@10090000 { > > + compatible = "sifive,fu540-c000-gem"; > > "sifive,fu740-c000-gem"? > Same reason as above. Thanks for your review. - Yash > > + interrupt-parent = <&plic0>; > > + interrupts = <55>; > > + reg = <0x0 0x10090000 0x0 0x2000>, > > + <0x0 0x100a0000 0x0 0x1000>; > > + local-mac-address = [00 00 00 00 00 00]; > > + clock-names = "pclk", "hclk"; > > + clocks = <&prci PRCI_CLK_GEMGXLPLL>, > > + <&prci PRCI_CLK_GEMGXLPLL>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + status = "disabled"; > > + }; > > + pwm0: pwm@10020000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10020000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <44>, <45>, <46>, <47>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + pwm1: pwm@10021000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10021000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <48>, <49>, <50>, <51>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + ccache: cache-controller@2010000 { > > + compatible = "sifive,fu740-c000-ccache", "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <2048>; > > + cache-size = <2097152>; > > + cache-unified; > > + interrupt-parent = <&plic0>; > > + interrupts = <19 20 21 22>; > > + reg = <0x0 0x2010000 0x0 0x1000>; > > + }; > > + gpio: gpio@10060000 { > > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; > > + interrupt-parent = <&plic0>; > > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, > > + <30>, <31>, <32>, <33>, <34>, <35>, <36>, > > + <37>, <38>; > > + reg = <0x0 0x10060000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + status = "disabled"; > > + }; > > + }; > > +}; > > Regards, > Bin
Hi Yash, On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> wrote: > > > -----Original Message----- > > From: Bin Meng <bmeng.cn@gmail.com> > > Sent: 10 December 2020 19:05 > > To: Yash Shah <yash.shah@openfive.com> > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > > C000 SoC > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > > > FU740-C000 Soc > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > This file is expected to grow as more device drivers are added to the > > > kernel. > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > --- > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > +++++++++++++++++++++++++++++ > > > 1 file changed, 293 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > new file mode 100644 > > > index 0000000..eeb4f8c3 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > @@ -0,0 +1,293 @@ > > ... > > > > + plic0: interrupt-controller@c000000 { > > > + #interrupt-cells = <1>; > > > + #address-cells = <0>; > > > + compatible = "sifive,fu540-c000-plic", > > > + "sifive,plic-1.0.0"; > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > That's because it is not required. There won't be any difference in driver code for FU740 plic. Are there any driver changes for the drivers that have an updated fu640-c000-* bindings? I don't see them in the linux-riscv list. > > ... > > > > + eth0: ethernet@10090000 { > > > + compatible = "sifive,fu540-c000-gem"; > > > > "sifive,fu740-c000-gem"? > > > > Same reason as above. > > Thanks for your review. Regards, Bin
> -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 16 December 2020 11:36 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Hi Yash, > > On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> > wrote: > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@gmail.com> > > > Sent: 10 December 2020 19:05 > > > To: Yash Shah <yash.shah@openfive.com> > > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > > kernel@vger.kernel.org>; linux-riscv > > > <linux-riscv@lists.infradead.org>; > > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM > > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg > > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou > > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org; > > > u.kleine-koenig@pengutronix.de; Thierry Reding > > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > Rob > > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > > <bgolaszewski@baylibre.com>; Linus Walleij > > > <linus.walleij@linaro.org> > > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the > > > SiFive FU740- > > > C000 SoC > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> > wrote: > > > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is > > > > built > > > > > > FU740-C000 Soc > > > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > > > This file is expected to grow as more device drivers are added to > > > > the kernel. > > > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > > --- > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > > +++++++++++++++++++++++++++++ > > > > 1 file changed, 293 insertions(+) create mode 100644 > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > new file mode 100644 > > > > index 0000000..eeb4f8c3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > @@ -0,0 +1,293 @@ > > > > ... > > > > > > + plic0: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + #address-cells = <0>; > > > > + compatible = "sifive,fu540-c000-plic", > > > > + "sifive,plic-1.0.0"; > > > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > > > That's because it is not required. There won't be any difference in driver > code for FU740 plic. > > Are there any driver changes for the drivers that have an updated > fu640-c000-* bindings? I don't see them in the linux-riscv list. Yes, they will be posted soon. - Yash > > > > > ... > > > > > > + eth0: ethernet@10090000 { > > > > + compatible = "sifive,fu540-c000-gem"; > > > > > > "sifive,fu740-c000-gem"? > > > > > > > Same reason as above. > > > > Thanks for your review. > > Regards, > Bin
Hi Yash, On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote: > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > around the SiFIve U7 Core Complex and a TileLink interconnect. > > This file is expected to grow as more device drivers are added to the > kernel. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> Thanks for your patch, which became commit 57985788158a5a6b ("riscv: dts: add initial support for the SiFive FU740-C000 SoC"). > --- /dev/null > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > @@ -0,0 +1,293 @@ > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + compatible = "sifive,bullet0", "riscv"; I'm wondering why you're using compatible = "sifive,bullet0", "riscv"; According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC"), it should be compatible = "sifive,u74-mc", "riscv"; instead. Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using compatible = "sifive,e51", "sifive,rocket0", "riscv"; and compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; but according to the DT bindings the rocket part should not be present. Is there any specific reason for that? Should the DT bindings and/or the DTS files be fixed? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, Jul 16, 2021 at 3:51 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Yash, > > On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote: > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > This file is expected to grow as more device drivers are added to the > > kernel. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > Thanks for your patch, which became commit 57985788158a5a6b ("riscv: > dts: add initial support for the SiFive FU740-C000 SoC"). > > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > @@ -0,0 +1,293 @@ > > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + cpu0: cpu@0 { > > + compatible = "sifive,bullet0", "riscv"; > > I'm wondering why you're using > > compatible = "sifive,bullet0", "riscv"; > > According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv: > Update DT binding docs to support SiFive FU740 SoC"), it should be > > compatible = "sifive,u74-mc", "riscv"; > > instead. I plan to send out new DT for the Rev3A and Rev3B (the final board customers can buy) boards. This is already fixed in meta-sifive. In general bullet here is micro architecture, but it's less descriptive in /proc/cpuinfo. > > Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using > > compatible = "sifive,e51", "sifive,rocket0", "riscv"; > > and > > compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > but according to the DT bindings the rocket part should not be present. > > Is there any specific reason for that? > Should the DT bindings and/or the DTS files be fixed? > > Thanks! > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi new file mode 100644 index 0000000..eeb4f8c3 --- /dev/null +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 SiFive, Inc */ + +/dts-v1/; + +#include <dt-bindings/clock/sifive-fu740-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu740-c000", "sifive,fu740"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = ð0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,bullet0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + reg = <0x0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <69>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu740-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <39>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <40>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_PCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@10031000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10031000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <53>; + clocks = <&prci PRCI_CLK_PCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <41>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <42>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@10050000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <43>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <55>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <44>, <45>, <46>, <47>; + clocks = <&prci PRCI_CLK_PCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <48>, <49>, <50>, <51>; + clocks = <&prci PRCI_CLK_PCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + ccache: cache-controller@2010000 { + compatible = "sifive,fu740-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <19 20 21 22>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>, <31>, <32>, <33>, <34>, <35>, <36>, + <37>, <38>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + }; +};
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built around the SiFIve U7 Core Complex and a TileLink interconnect. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++ 1 file changed, 293 insertions(+) create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi