Patch Metrics

There are 40156 patches submitted by members of this team, and 10360 of those have been accepted upstream.

Patches per month: Submitted Accepted
Time-to-acceptance distribution (in days)

Current Members

Show patches with: Archived = No       |   40156 patches
« 1 2 ... 375 376 377 … 401 402 »
Patch Series S/W/F Date Submitter Delegate State
Support for HWbreak/watchpoint accross fork/vfork on arm-native --- 2014-02-12 Omair Javaid New
[RFC] translate-all.c: add hack for coverage testing --- 2014-02-11 Peter Maydell New
[v2,2/2] target-arm: A64: Implement remaining 3-same instructions --- 2014-02-11 Peter Maydell Accepted
[v2,1/2] softfloat: Support halving the result of muladd operation --- 2014-02-11 Peter Maydell Accepted
[PULL,07/48] tests: Run qom-test for every architecture --- 2014-02-10 Andreas Färber New
[PULL,23/29] disas/libvixl: Fix upstream libvixl compilation issues --- 2014-02-08 Peter Maydell Accepted
[PULL,22/29] disas: Add subset of libvixl sources for A64 disassembler --- 2014-02-08 Peter Maydell Accepted
[PULL,21/29] rules.mak: Link with C++ if we have a C++ compiler --- 2014-02-08 Peter Maydell Accepted
[PULL,20/29] rules.mak: Support .cc as a C++ source file suffix --- 2014-02-08 Peter Maydell Accepted
[PULL,14/29] target-arm: Add support for AArch32 64bit VCVTB and VCVTT --- 2014-02-08 Peter Maydell Accepted
[PULL,13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group --- 2014-02-08 Peter Maydell Accepted
[PULL,11/29] target-arm: A64: Add narrowing 2-reg-misc instructions --- 2014-02-08 Peter Maydell Accepted
[PULL,10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT --- 2014-02-08 Peter Maydell Accepted
[PULL,09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG --- 2014-02-08 Peter Maydell Accepted
[PULL,08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group --- 2014-02-08 Peter Maydell Accepted
[PULL,07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc --- 2014-02-08 Peter Maydell Accepted
[PULL,06/29] target-arm: A64: Implement remaining integer scalar-3-same insns --- 2014-02-08 Peter Maydell Accepted
[PULL,05/29] target-arm: A64: Implement scalar pairwise ops --- 2014-02-08 Peter Maydell Accepted
[PULL,04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR --- 2014-02-08 Peter Maydell Accepted
[PULL,03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD --- 2014-02-08 Peter Maydell Accepted
[PULL,02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns --- 2014-02-08 Peter Maydell Accepted
[PULL,01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns --- 2014-02-08 Peter Maydell Accepted
[PULL,00/29] target-arm queue --- 2014-02-08 Peter Maydell Accepted
[8/8] target-arm: A64: Implement remaining 3-same instructions --- 2014-02-07 Peter Maydell Superseded
[7/8] softfloat: Support halving the result of muladd operation --- 2014-02-07 Peter Maydell Superseded
[4/8] target-arm: A64: Implement scalar three different instructions --- 2014-02-07 Peter Maydell Superseded
[3/8] target-arm: A64: Implement SIMD scalar indexed instructions --- 2014-02-07 Peter Maydell Superseded
[2/8] target-arm: A64: Implement long vector x indexed insns --- 2014-02-07 Peter Maydell Superseded
[1/8] target-arm: A64: Implement plain vector SIMD indexed element insns --- 2014-02-07 Peter Maydell Accepted
malloc/mtrace.c: Cosmetic cleanup. --- 2014-02-06 Will Newton Accepted
Disable gdb.dwarf2/implptr-64bit.exp for 32-bit targets --- 2014-02-06 Omair Javaid New
Disable gdb.dwarf2/implptr-64bit.exp for 32-bit targets --- 2014-02-06 Omair Javaid New
[v3,4/5] disas/libvixl: Fix upstream libvixl compilation issues --- 2014-02-05 Peter Maydell Superseded
[v3,3/5] disas: Add subset of libvixl sources for A64 disassembler --- 2014-02-05 Peter Maydell Superseded
[v3,2/5] rules.mak: Link with C++ if we have a C++ compiler --- 2014-02-05 Peter Maydell Superseded
[v3,1/5] rules.mak: Support .cc as a C++ source file suffix --- 2014-02-05 Peter Maydell Superseded
[v2] ARM: Add SystemTap probes to longjmp and setjmp. --- 2014-02-05 Will Newton Superseded
[v3] manual/probes.texi: Add documentation of setjmp/longjmp probes --- 2014-02-05 Will Newton Accepted
[1/8] vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type --- 2014-02-04 Juan Quintela New
[1/8] vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type --- 2014-02-04 Juan Quintela New
Add support for MAP_NORESERVE mmap flag. --- 2014-02-03 Christophe Lyon Superseded
[ARM] Vectorizer generates unaligned access when -mno-unaligned-access is enabled --- 2014-02-03 Kugan Vivekanandarajah Accepted
[v2,13/13] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group --- 2014-02-01 Peter Maydell Superseded
[v2,11/13] target-arm: A64: Add narrowing 2-reg-misc instructions --- 2014-02-01 Peter Maydell Superseded
[v2,10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT --- 2014-02-01 Peter Maydell Superseded
[v2,09/13] target-arm: A64: Implement 2-register misc compares, ABS, NEG --- 2014-02-01 Peter Maydell Superseded
[v2,08/13] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group --- 2014-02-01 Peter Maydell Superseded
[v2,07/13] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc --- 2014-02-01 Peter Maydell Superseded
[v2,06/13] target-arm: A64: Implement remaining integer scalar-3-same insns --- 2014-02-01 Peter Maydell Superseded
[v2,05/13] target-arm: A64: Implement scalar pairwise ops --- 2014-02-01 Peter Maydell Superseded
[v2,04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR --- 2014-02-01 Peter Maydell Superseded
[v2,03/13] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD --- 2014-02-01 Peter Maydell Superseded
[v2,02/13] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns --- 2014-02-01 Peter Maydell Superseded
[v2,01/13] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns --- 2014-02-01 Peter Maydell Superseded
[v2,35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI --- 2014-01-31 Peter Maydell Superseded
[v2,34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers --- 2014-01-31 Peter Maydell Superseded
[v2,33/35] target-arm: Implement AArch64 ID and feature registers --- 2014-01-31 Peter Maydell Superseded
[v2,32/35] target-arm: Implement AArch64 generic timers --- 2014-01-31 Peter Maydell Superseded
[v2,31/35] target-arm: Implement AArch64 MPIDR --- 2014-01-31 Peter Maydell Superseded
[v2,30/35] target-arm: Implement AArch64 TTBR* --- 2014-01-31 Peter Maydell Superseded
[v2,29/35] target-arm: Implement AArch64 VBAR_EL1 --- 2014-01-31 Peter Maydell Superseded
[v2,28/35] target-arm: Implement AArch64 TCR_EL1 --- 2014-01-31 Peter Maydell Superseded
[v2,27/35] target-arm: Implement AArch64 SCTLR_EL1 --- 2014-01-31 Peter Maydell Superseded
[v2,26/35] target-arm: Implement AArch64 memory attribute registers --- 2014-01-31 Peter Maydell Superseded
[v2,25/35] target-arm: Implement AArch64 dummy MDSCR_EL1 --- 2014-01-31 Peter Maydell Superseded
[v2,24/35] target-arm: Implement AArch64 TLB invalidate ops --- 2014-01-31 Peter Maydell Superseded
[v2,23/35] target-arm: Implement AArch64 cache invalidate/clean ops --- 2014-01-31 Peter Maydell Superseded
[v2,22/35] target-arm: Implement AArch64 DAIF system register --- 2014-01-31 Peter Maydell Superseded
[v2,21/35] target-arm: Implement AArch64 MIDR_EL1 --- 2014-01-31 Peter Maydell Superseded
[v2,20/35] target-arm: Implement AArch64 CurrentEL sysreg --- 2014-01-31 Peter Maydell Superseded
[v2,19/35] target-arm: A64: Make cache ID registers visible to AArch64 --- 2014-01-31 Peter Maydell Superseded
[v2,18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg --- 2014-01-31 Peter Maydell Superseded
[v2,17/35] target-arm: Remove failure status return from read/write_raw_cp_reg --- 2014-01-31 Peter Maydell Superseded
[v2,16/35] target-arm: Remove unnecessary code now read/write fns can't fail --- 2014-01-31 Peter Maydell Superseded
[v2,15/35] target-arm: Drop success/fail return from cpreg read and write functions --- 2014-01-31 Peter Maydell Superseded
[v2,14/35] target-arm: Convert miscellaneous reginfo structs to accessfn --- 2014-01-31 Peter Maydell Superseded
[v2,13/35] target-arm: Convert generic timer reginfo to accessfn --- 2014-01-31 Peter Maydell Superseded
[v2,12/35] target-arm: Convert performance monitor reginfo to accesfn --- 2014-01-31 Peter Maydell Superseded
[v2,11/35] target-arm: Split cpreg access checks out from read/write functions --- 2014-01-31 Peter Maydell Superseded
[v2,10/35] target-arm: Stop underdecoding ARM946 PRBS registers --- 2014-01-31 Peter Maydell Superseded
[v2,09/35] target-arm: A64: Implement MSR (immediate) instructions --- 2014-01-31 Peter Maydell Superseded
[v2,08/35] target-arm: A64: Implement store-exclusive for system mode --- 2014-01-31 Peter Maydell Superseded
[v2,07/35] target-arm: Add exception level to the AArch64 TB flags --- 2014-01-31 Peter Maydell Superseded
[v2,06/35] target-arm: Log bad system register accesses with LOG_UNIMP --- 2014-01-31 Peter Maydell Superseded
[v2,05/35] target-arm: Remove unused ARMCPUState sr substruct --- 2014-01-31 Peter Maydell Superseded
[v2,04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier --- 2014-01-31 Peter Maydell Superseded
[v2,03/35] target-arm: Define names for SCTLR bits --- 2014-01-31 Peter Maydell Superseded
[v2,02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs --- 2014-01-31 Peter Maydell Superseded
[v2,01/35] target-arm: Fix raw read and write functions on AArch64 registers --- 2014-01-31 Peter Maydell Superseded
[PULL,v2,00/34] target-arm queue --- 2014-01-31 Peter Maydell Superseded
Support for HWbreak/watchpoint accross fork/vfork on arm-native --- 2014-01-30 Omair Javaid New
[v2] manual/probes.texi: Add documentation of setjmp/longjmp probes --- 2014-01-30 Will Newton Superseded
[PULL,31/38] target-arm: A64: Add simple SIMD 3-same floating point ops --- 2014-01-29 Peter Maydell Accepted
[PULL,30/38] target-arm: A64: Add integer ops from SIMD 3-same group --- 2014-01-29 Peter Maydell Accepted
[PULL,29/38] target-arm: A64: Add logic ops from SIMD 3 same group --- 2014-01-29 Peter Maydell Accepted
[PULL,28/38] target-arm: A64: Add top level decode for SIMD 3-same group --- 2014-01-29 Peter Maydell Accepted
[PULL,27/38] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops --- 2014-01-29 Peter Maydell Accepted
[PULL,26/38] target-arm: A64: Add SIMD three-different ABDL instructions --- 2014-01-29 Peter Maydell Accepted
[PULL,25/38] target-arm: A64: Add SIMD three-different multiply accumulate insns --- 2014-01-29 Peter Maydell Accepted
[PULL,24/38] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM --- 2014-01-29 Peter Maydell Accepted
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