From patchwork Tue Mar 13 06:17:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 131408 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp347337ljb; Mon, 12 Mar 2018 23:17:54 -0700 (PDT) X-Google-Smtp-Source: AG47ELsxiSnu6C1tqoEzMWKTrUsc/qILhAQS/UIPvP9q9tZ5eUD20HRgo0KpIcADNWTHKFciSpDG X-Received: by 10.98.225.2 with SMTP id q2mr1083504pfh.23.1520921874777; Mon, 12 Mar 2018 23:17:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520921874; cv=none; d=google.com; s=arc-20160816; b=iixCeoACvyfqF561st/+z+ipVViaSsIX1NRytrfi9V/Y7VPNFh/0e6kWMOfNY/mSaG 2c0np2QlhN/KRTLQUMNw2wQsitZ3Ba0/wCLWOXpqDgNz8NVQxewbaB8HKUUGzNbOq4/w kYPDIfd/g6Kam1jgZy8y3TUHiH7o+qwm2VOL3MdNQlQBMWTrmX0Zw+gMGILzckcaQvHm xO5MUsPsRwGstchjuxBKIi05eizxeWrJ8/SLyg12lmKqGabvOXvXMedST8coz1kjuBrw wD/Wt13Yrw7n2twVTfUbtwNpjbYWoCP8XMMBxdAFG8Aro79LFIwaYd6i8PMiJUjT+1z6 aeYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=ZfHKfW+Y3IERpLdkH0yTfIXi+pDtemeAWULd9L8STr/9kg/fn7zBc4eZaabZzP5diW 4FKG/z0hlYFW6OQ+3NAwbvKy3Zr23VEFQ6Lu3lNcQeqbs1KOGNTXlk7yjjU52MGm+WwY u0djUMCKtBdq4+qtYLA0TgvEq0NdAH3feEswdOebRPKMw69E6kNoS53H7KNk4JscmBrR 4HdU7PVEqkjq2g9jYaLloo9uifjoARFFwW0aDnvwH5EQ3zQBSV+SqP5sjEBA1vYZyNcE mUAigXFR1D3bPj8uhhuAGHXlMNa3JP6QB0iD44Vp8SGCgB0eEf+bT332F8PkbuXutulQ mX1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=GZfEOLJl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si1060330plj.510.2018.03.12.23.17.54; Mon, 12 Mar 2018 23:17:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=GZfEOLJl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751842AbeCMGRw (ORCPT + 28 others); Tue, 13 Mar 2018 02:17:52 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:41064 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751574AbeCMGRt (ORCPT ); Tue, 13 Mar 2018 02:17:49 -0400 Received: by mail-pg0-f65.google.com with SMTP id w17so3498768pgq.8; Mon, 12 Mar 2018 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=GZfEOLJlu1QacD6meKEmg0+/q3OlAVHi7ubVvc1D83MilNqZRRVR9cO0gIHGQ6ROdg KB12pV/PSBtV1QBtbMj+ONqBnpSNsQo06cfbcdMPC5urCz97zUnfMYM9wOtVGRJkBYqZ JWb084htGKr0JFjwJ85aGHd1TDViN01hJnQAJbL2cKM/zYHLQBg0RHYlcnLWt6xA8oa0 entMnCbgP7mgoPsqP+qChPF9FTusYRUB8AZSwVHMrg5m/bG7C8aLKY8sqJffSoapV+GP zvChatr5OHyS0zD3GdiWSAn9+yfkOvj8Qy+yjyuDC1ntXSyo2B0w3JRO3oPZ06xcp2eu HkHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=k3Fzj4bPFwNLp0/ikNr/gRec8JAUKkdwZFtLhjYuZD/VwRNJHY91/iLTKZFm+et7Ko qpfBPlwPrj7nm8V6spohKev8FIIQ5j6tNor1Ilw2/G81cONIVrhQwh3ZOW/OyEvirn+j YZhB+jhfS2LGagJmPxSb57BrkbzNgo3PjTiGSLkG2WJfhJZtKeV+gHnq94ifsnlci45K ZHOpjhChOwU1Lh2TSaNL76EzGJKkamzdRF75jN2/Bdu9G8h2Nl7NheAxbuhwe9Lhw/pN XMNAPGW9IwRRv2+7wZuYmqy93bagUy/H79LZltUCNytMEggPDFtqh0ihEv+Rb8lEe6/B 5nTg== X-Gm-Message-State: AElRT7HW/P0lmaF4AVkUlM4pPPkh/xp4de+WxPo084wIGn1uVlMZb0fe nELqMt0hi0N9oOprJPNm9wXp+MPzT7E= X-Received: by 10.101.69.66 with SMTP id x2mr8707135pgr.438.1520921868613; Mon, 12 Mar 2018 23:17:48 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id h7sm7195972pgp.26.2018.03.12.23.17.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Mar 2018 23:17:47 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 13 Mar 2018 16:47:40 +1030 From: Joel Stanley To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Mark Rutland , Marcus Folkesson Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon , Avi Fishman , Brendan Higgins Subject: [PATCH v4 1/2] dt-bindings: watchdog: Add Nuvoton NPCM description Date: Tue, 13 Mar 2018 16:47:25 +1030 Message-Id: <20180313061726.21601-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180313061726.21601-1-joel@jms.id.au> References: <20180313061726.21601-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These bindings describe the watchdog IP as used by the Nuvoton NPCM750 (Poleg) BMC SoC. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley --- V2: Add optional timeout property v3: - Fix address in example - Add Rob's reviewed-by --- .../bindings/watchdog/nuvoton,npcm-wdt.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt -- 2.15.1 Reviewed-by: Guenter Roeck diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt new file mode 100644 index 000000000000..6d593003c933 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt @@ -0,0 +1,28 @@ +Nuvoton NPCM Watchdog + +Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. +The watchdog supports a pre-timeout interrupt that fires 10ms before the +expiry. + +Required properties: +- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg). +- reg : Offset and length of the register set for the device. +- interrupts : Contain the timer interrupt with flags for + falling edge. + +Required clocking property, have to be one of: +- clocks : phandle of timer reference clock. +- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx + timer (usually 25000000). + +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + +Example: + +timer@f000801c { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xf000801c 0x4>; + clocks = <&clk NPCM7XX_CLK_TIMER>; +}; From patchwork Tue Mar 13 06:17:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 131409 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp347437ljb; Mon, 12 Mar 2018 23:18:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELsx5N/8PGLgEo1OOyUGSvT9ITAlxErymHDiHcL5BaYY4eUZWesf9hhKJ43tPFSU4OhZ9njm X-Received: by 2002:a17:902:7290:: with SMTP id d16-v6mr10651213pll.31.1520921883152; Mon, 12 Mar 2018 23:18:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520921883; cv=none; d=google.com; s=arc-20160816; b=kTPbPr1BnXKN1D++1zQulSyY5vPJWE37neDHvlE2anWOsuoLsK4A2XvlgfW5hKgJW9 E9soD6EqHysTFdhBC+ARXLCtld/DjPnc23o7H+cz+AZEyBk0HoPZWGWzpV1g9Wr92kFq YMdH7VCFPr+jhg5+7K3hR5jCvWTvkMveeDt2zTPV4hUiZeaD0+ErqbGuO9twgmspHhUY T9jcKZF1aeZEaGSWfmsMXDmHl6r/pAToBkc/Yz9PQsGiD2PH9yCmpex+VHav8ErlMguv F0iCwaJEcrDef6SaGdUIWRtl4a0rWcEyQxR/rmUJNXtvwiJOYCxQBRI9vLge7IRY4+AZ C7xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xVCKwVp4XFcOGZySFls00Vxo8P5oBhsZpPDjoAsEOc0=; b=gE2Uf1yVf2LQ1YNJ5l6uOFp5GqarOc5Qcm9aaSIFPRR/Ydv2oR24IvAA1ZuxsKbPnB UNPi1h0LJY8RU/GLOnVHTugRRqM8aLyzs02Gw6hMMVbBh0IYpVI95PA9ZO4Ky8OPgfva eDAvbleaR250kIFyReYVmFMerdEBPrMnGjJN/0IMX3iKaX7VVBWUlqbYEJ2+tk2cUQaN R7FaHvSStzLyxSregQuxaP2Vif+v6lGGdunc50I4qLPF02CcxknZleUyqktHKWuC4GkC hvG2HQ+NADkoXEEVLVgJ6Wj4BG5TyMQceMH+IoFj9aynZ+L5RxbL5McgKyKEEiXI7dWR 8lBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=YTP0A+zd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This driver exposes that watchdog as a standard watchdog device with coarse timeout intervals, limited by the combination of prescaler and counter that is provided by the hardware. The calculation is taken from the Nuvoton vendor tree. The watchdog is left running if a bootloader had it going. The rate is the one specified in the device tree, or the default value (obtained from the datasheet). There is a pre-timeout IRQ that is wired up. This timeout always occurs 1024 clocks before the timeout. Signed-off-by: Joel Stanley --- v2: - Make MODULE_LICENCE gpl v2 to match SPDX - Remove unused struct device pointer - Remove unused setting of drvdata - Add linux/bitops.h - Sort includes - Remove unused fiq include - Update timeout with achieved value v3: - Calculate the time and register value separately - Pass device tree value through set_timeout to ensure it can be represented by hardware v4: - Propagate return code from platform_get_irq --- drivers/watchdog/Kconfig | 11 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 254 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c -- 2.15.1 Reviewed-by: Guenter Roeck diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index aff773bcebdb..0c1cc68894e6 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -513,6 +513,17 @@ config COH901327_WATCHDOG This watchdog is used to reset the system and thus cannot be compiled as a module. +config NPCM7XX_WATCHDOG + bool "Nuvoton NPCM750 watchdog" + depends on ARCH_NPCM || COMPILE_TEST + default y if ARCH_NPCM750 + select WATCHDOG_CORE + help + Say Y here to include Watchdog timer support for the + watchdog embedded into the NPCM7xx. + This watchdog is used to reset the system and thus cannot be + compiled as a module. + config TWL4030_WATCHDOG tristate "TWL4030 Watchdog" depends on TWL4030_CORE diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0474d38aa854..97a5afb5cad2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o +obj-$(CONFIG_NPCM7XX_WATCHDOG) += npcm_wdt.o obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 000000000000..0d4213652ecc --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright (c) 2018 IBM Corp. + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NPCM_WTCR 0x1C + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +/* + * Watchdog timeouts + * + * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400 + * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410 + * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800 + * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420 + * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810 + * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430 + * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820 + * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00 + * 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830 + * 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10 + * 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20 + * 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30 + */ + +struct npcm_wdt { + struct watchdog_device wdd; + void __iomem *reg; +}; + +static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) +{ + return container_of(wdd, struct npcm_wdt, wdd); +} + +static int npcm_wdt_ping(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + u32 val; + + val = readl(wdt->reg); + writel(val | NPCM_WTR, wdt->reg); + + return 0; +} + +static int npcm_wdt_start(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + u32 val; + + if (wdd->timeout < 2) + val = 0x800; + else if (wdd->timeout < 3) + val = 0x420; + else if (wdd->timeout < 6) + val = 0x810; + else if (wdd->timeout < 11) + val = 0x430; + else if (wdd->timeout < 22) + val = 0x820; + else if (wdd->timeout < 44) + val = 0xC00; + else if (wdd->timeout < 87) + val = 0x830; + else if (wdd->timeout < 173) + val = 0xC10; + else if (wdd->timeout < 688) + val = 0xC20; + else + val = 0xC30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + + writel(val, wdt->reg); + + return 0; +} + +static int npcm_wdt_stop(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + writel(0, wdt->reg); + + return 0; +} + + +static int npcm_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + if (timeout < 2) + wdd->timeout = 1; + else if (timeout < 3) + wdd->timeout = 2; + else if (timeout < 6) + wdd->timeout = 5; + else if (timeout < 11) + wdd->timeout = 10; + else if (timeout < 22) + wdd->timeout = 21; + else if (timeout < 44) + wdd->timeout = 43; + else if (timeout < 87) + wdd->timeout = 86; + else if (timeout < 173) + wdd->timeout = 172; + else if (timeout < 688) + wdd->timeout = 687; + else + wdd->timeout = 2750; + + if (watchdog_active(wdd)) + npcm_wdt_start(wdd); + + return 0; +} + +static irqreturn_t npcm_wdt_interrupt(int irq, void *data) +{ + struct npcm_wdt *wdt = data; + + watchdog_notify_pretimeout(&wdt->wdd); + + return IRQ_HANDLED; +} + +static int npcm_wdt_restart(struct watchdog_device *wdd, + unsigned long action, void *data) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); + udelay(1000); + + return 0; +} + +static bool npcm_is_running(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + return readl(wdt->reg) & NPCM_WTE; +} + +static const struct watchdog_info npcm_wdt_info = { + .identity = KBUILD_MODNAME, + .options = WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE, +}; + +static const struct watchdog_ops npcm_wdt_ops = { + .owner = THIS_MODULE, + .start = npcm_wdt_start, + .stop = npcm_wdt_stop, + .ping = npcm_wdt_ping, + .set_timeout = npcm_wdt_set_timeout, + .restart = npcm_wdt_restart, +}; + +static int npcm_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct npcm_wdt *wdt; + struct resource *res; + int irq; + int ret; + + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + wdt->reg = devm_ioremap_resource(dev, res); + if (IS_ERR(wdt->reg)) + return PTR_ERR(wdt->reg); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + wdt->wdd.info = &npcm_wdt_info; + wdt->wdd.ops = &npcm_wdt_ops; + wdt->wdd.min_timeout = 1; + wdt->wdd.max_timeout = 2750; + wdt->wdd.parent = dev; + + wdt->wdd.timeout = 86; + watchdog_init_timeout(&wdt->wdd, 0, dev); + + /* Ensure timeout is able to be represented by the hardware */ + npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); + + if (npcm_is_running(&wdt->wdd)) { + /* Restart with the default or device-tree specified timeout */ + npcm_wdt_start(&wdt->wdd); + set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); + } + + ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, + "watchdog", wdt); + if (ret) + return ret; + + ret = devm_watchdog_register_device(dev, &wdt->wdd); + if (ret) { + dev_err(dev, "failed to register watchdog\n"); + return ret; + } + + dev_info(dev, "NPCM watchdog driver enabled\n"); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id npcm_wdt_match[] = { + {.compatible = "nuvoton,npcm750-wdt"}, + {}, +}; +MODULE_DEVICE_TABLE(of, npcm_wdt_match); +#endif + +static struct platform_driver npcm_wdt_driver = { + .probe = npcm_wdt_probe, + .driver = { + .name = "npcm-wdt", + .of_match_table = of_match_ptr(npcm_wdt_match), + }, +}; +module_platform_driver(npcm_wdt_driver); + +MODULE_AUTHOR("Joel Stanley"); +MODULE_DESCRIPTION("Watchdog driver for NPCM"); +MODULE_LICENSE("GPL v2");