From patchwork Wed Feb 3 12:58:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98AB9C433E0 for ; Wed, 3 Feb 2021 13:01:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53B8464E30 for ; Wed, 3 Feb 2021 13:01:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230131AbhBCNBS (ORCPT ); Wed, 3 Feb 2021 08:01:18 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14157 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbhBCNAt (ORCPT ); Wed, 3 Feb 2021 08:00:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612357805; x=1643893805; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HuL/RXPfYhx4XwPsZJpcViVF/tXPYXsIbvZ4bFefu0E=; b=f2GRXag+jUte37tJ1UP034KKs9bjCLk9pWnoNXLfT9/ms752tNgUSMl+ uK45Fc5mhQpx+meE8SfHi35S3BAR33VPM8TdYCVFsG5UQ/YrmpT4UCckh bhzBgDX6gHmKUJ/u8EkOY7IPJwCEfBHgR9UPs4k1eIduvc62yoniSzLiJ gNDeEnbwbxzKjOiHWKXD7QleHTle5JgvQU32r3ZslTys5FNjmz26NGj2Y 1ZlHt+ja62O5evDfGEJPtvfV1QXXWl9ODLHMAH3hAJ2/JK699RGQchUgH fcF7/06vvFfjRiM+7Xtoz7PHzwiFAclldogk1WD3rVjpGO/36TBuKeYG8 Q==; IronPort-SDR: HpoB2CY2089NSN+wYWore6vlClPG+ImmfbS8rv46BHgJyVFzUcygAVzatO0eMImygxJF9a3eKh 6czHo9cqTlAyQyikVzOwJek1JPAx6NQrgcXSbvhl2D/ck1wnb/LUBKpCIuqUTk878KZu+IlMe3 STNS6vgffi1lIvbm7pEx71F59UPsWzG5deCgMX7t9n1etmgTCDPjDqY2Z7CBJHKq7tBilovMJV mVI0s+gxkniVhx2X7UZyEmKJyoPHTxX1sA4GU/i1d3f1P5K9WQ+3Klzw+/ym5k53xm8asvob21 kAw= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106919" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:27 +0800 IronPort-SDR: Ms8Y3amOmTLpaJoSypu6k8MaIR7R9MJDKUyW8/kVVELNeaD4OCk7BehdKHir2HTqYf0d8JKeIQ i7/j9s/6du/xAEBf0exVonJJiOstTqAL7mWxPWkAS3nUewQa3T5Dn0TXIVeY+mNnpGNIx+vCNA I3d42gg3t3dqykndDdqWv4I40s0+x/B+t1ND0bi40AriGAl8//gACm7voxZ7YMw7WakzCUU+OT nyq65sZGIC1MrO1jFzUZOaemnMmZJ3WKhozEaz0NaCv/gfgxuJ84QZKDMhmOsnl/WeK/4d+uDH YG9F/9qZTM/GF1xUmd91zZcZ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:43 -0800 IronPort-SDR: IGikk8QHZypD1jGsJsdb+5pPWh+/5WToE7Jk6xfhjobvY7bXiFuHpAKHMNcB8kupXC55/qInsW J8cOwaq2t0YUyjL9T1uPtsKNrNbRobcCY6XR6qzWDSZkhRalM3C+46atK9kdQCxxQXG3ROmGCV sLufGIdvq+W3d/r7CSSjcvn3X4+2B5qYv1B55YzbmEsv+ZOcwwHWNDiW6r09IIA9YZvPrJ0MfQ cDvx+NRXvdxN/qkBRyrqzNmW8aweg9CBt62jaiBeZ4GrrQOWoHMSNWkGMw9jRirFH+PkOqySNc IUA= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:41 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 02/16] dt-bindings: add Canaan boards compatible strings Date: Wed, 3 Feb 2021 21:58:59 +0900 Message-Id: <20210203125913.390949-3-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce the file riscv/canaan.yaml to document compatible strings related to the Canaan Kendryte K210 SoC. The compatible string "canaan,kendryte-k210" used to indicate the use of this SoC to the early SoC init code is added. This new file also defines the compatible strings of all supported boards based on this SoC. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Reviewed-by: Rob Herring --- .../devicetree/bindings/riscv/canaan.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/canaan.yaml diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml new file mode 100644 index 000000000000..f8f3f286bd55 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/canaan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan SoC-based boards + +maintainers: + - Damien Le Moal + +description: + Canaan Kendryte K210 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sipeed,maix-bit + - const: sipeed,maix-bitm + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-go + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-dock-m1 + - const: sipeed,maix-dock-m1w + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maixduino + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-kd233 + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-k210 + +additionalProperties: true + +... From patchwork Wed Feb 3 12:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89489C433DB for ; Wed, 3 Feb 2021 13:01:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5329860203 for ; Wed, 3 Feb 2021 13:01:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbhBCNBX (ORCPT ); Wed, 3 Feb 2021 08:01:23 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14165 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231264AbhBCNAx (ORCPT ); Wed, 3 Feb 2021 08:00:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612357810; x=1643893810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UMFQIdrYtQi54YrRachcvZozXVK7+0hIHPjfiw4r9KA=; b=P82ViV2ZTXETQHVD4WimMeoUDbtxjXK36B8OtV8EPPwRcCvQe9I/+Xal 1WzDz5iOB3dQSNv11UVZavPlMrNUq2kH1Qk9Tof1atmw0kBRR/4ISTjlT h2hMjoyhBQz73+i5RpNl45vv5+d/0ljbyYaX8DkxGPkPqVl3HhWjVcHYd fffn/H7icqbxtonM+clC3C1DMX/eu0A4Wfp4L+5Ccojmazq/s87fk5nBu 4twXbEd9ln3UDeEDYlHcGxDUGaZNGzhNUFa0QKVUzmxGyEN+sDbALpNYi UkXNEsNilrJPNpBFnNaWHchlaHgbEIMGcsveiKXvxsd49/hypQDDhT3zY A==; IronPort-SDR: f8xG8gjxbpEBnOxnP+r5GJgrczPMb57qHYTorejsuXnB0yWPMxR3nxKGkVFmj0Tv7NGIPfCO7t VX/Vr/ImMfiPNMz4wvtLMcSxutFZi9+P1O4WrCWEFDwBGruA+BcYYAJKv7lyaS8E4+2WFpYN96 sBiqdrozGkyatYvGcJaDEVUjI1tIrI2RQ9G6pqXIQ8ZOBSMdnMSnR27PsszQo+QNTJigUu9Fl4 gDSeh9oDuCRoNFgyfqgIyg2LmZed4oe7J2lHLb59FQYUeD4B7ZqHTQC0eyUCHa5DRFrp3xgD0C 0/s= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106932" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:32 +0800 IronPort-SDR: xFJFybMduehFulM5pxc8VVZCQyTLrhJg3GsZVkADmy//4nHAAuNcLCbJoprebii6Le2Q9ItqsT WFl2r7fIGsnfpHHU6orqW8w9Jtc/QHOTgEo2hsaZbYO691v3zwV3dJU91mKp5WDskzJUK+CSW9 ojBBRrORBSkmU8F7d/orN4bl10HSSSO4OpBbgR1ouwxiO2PSgoSLhFwvaHP0GnUbWrWoMWzNpg jHB+rWJ+CZhIC6LYVL3Xq1XRIRYmalej9gG8wrSQSkLH9Y+v//TWDGCK/4aO1rTMiH9/Q/GoCo mh08gDyGtUatQXoucGhJ1KZa Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:47 -0800 IronPort-SDR: uS+ApnV/oVN8lTTMdgOlZM7R+TZgaXPNPOscRJQDIQEsvj8bNQnC4ImXoAKM7iv6m1Ejc51+r+ LEbDL2vb5aFi6Q7HzmPw+SA0NbqugG6yKNHBnoAsHFGZaqPANrj22rQTyculkJalvu+5pCOFZ5 fKBngu4lZsbYtNkT33SW7lMCEQs9pntOqk4pE/yq5rstk33a/w2pt2G4glqFYxYDHoyqqL6srf 6+KAoO2iG3Vb1SEHrzCYRLi+iI0/DpCuboLr8Lvw5RV7+Gpue5agd9CMTx9jYXZd0YhaFXQfJu 6h8= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:45 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 04/16] dt-bindings: update sifive plic compatible string Date: Wed, 3 Feb 2021 21:59:01 +0900 Message-Id: <20210203125913.390949-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string "canaan,k210-plic" to the Sifive plic bindings to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan Kendryte K210 SoC. The description is also updated to reflect this change, that is, that SoCs from other vendors may also use this plic implementation. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra --- .../sifive,plic-1.0.0.yaml | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..04ed7a03c97e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive SoCs and other RISC-V SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -41,9 +42,14 @@ maintainers: properties: compatible: - items: - - const: sifive,fu540-c000-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - const: sifive,fu540-c000-plic + - const: sifive,plic-1.0.0 + + - items: + - const: canaan,k210-plic + - const: sifive,plic-1.0.0 reg: maxItems: 1 From patchwork Wed Feb 3 12:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 333F9C433DB for ; Wed, 3 Feb 2021 13:02:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04ED064E30 for ; Wed, 3 Feb 2021 13:02:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229691AbhBCNCD (ORCPT ); Wed, 3 Feb 2021 08:02:03 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14157 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231449AbhBCNB6 (ORCPT ); Wed, 3 Feb 2021 08:01:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612357908; x=1643893908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PM7gAVPPOPJE8psIKumgDdsYrcLYZwGhuiJjB6JnJKs=; b=LpTGzpx+DT8qUBaFE34QjYC0ydQcmpMalCwBtjg/Mnr0BR9HvCrTI9fn v3a6JvK3ItA5J01KSPySIEqE0iHYzSFNv2wjcdsAbliKeLjDRv4zKerwA F8A/73dHNTLzgpZ3ZjFvMoQTZJrWkVoj986rF03v8adtZZzfRoDmiF8zn rXXq0ArIt1AO74iTEhQyDgOzu+hhgTCTJTXZ9xIFrJzel1kE9RX13eIPr o4poHB7yNrR0SVXyCKqJ1pby+S+wC1Cf5EuTb4+dX3uUf+WlYGrcz0H3r Xh+z6coI5kfZ+ZouQYCu2xxOLdBry76ZP1GNPD+ODq90V36OdEP4Z7qCU Q==; IronPort-SDR: 0z5VNDzKiyb9UWWbdsupvlmobIP8IvFfCLU91JlhV0PpSthKy9qK7LEKpZFL6/QOsoiPTms6TY l5vbLgniMQczbuH4ZUoWWXH6WeDlvZ9uKCKJnt4haFk7WVaJVpuiXfdcb4xITK+PjqU07qVD6+ rP1eT4NQAP/nfbPJEZ+ZDekXqBFOUvaLW9KiSvB2TBwe/EyjNzP5adtpv7Ho42UMUtML5TOmdX ptQItBKR6rRLjJHS/N1GXRw5+Yh+MjFgTWcSRFQuIRTSZXcfISqVZKrUZwRZzY6Tyfoom213DN AQA= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106934" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:34 +0800 IronPort-SDR: ZVB4Oc78h9K0OC07ZUnI25YdoPjUdfugX8wHqe8B25h9PQhYR2/BXhMIdYd7g4UKNYJHd2M+9/ s51NiVCiOYxeFWa+VPfuhdCuKK1NxdFW/mPKy258qLNPRTta7zZHXVuv4ijAcDiTI8T2BoXSFM Uu95iJzaFtmgpQvhOwrOx2IHYSboouaWqm1Rc8bbuYp9YAM9sC5BKd1nwZhxTwFChEZaVhlORH gm+gRlL/Hv3C7V2isl20weFIRkxR4oi/EeVZtXlolk+cxaRD3vn70UmB9EwW99bkuoSy4N4lfE YeNpBgx16LJSdAM9Pa4DS9RI Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:48 -0800 IronPort-SDR: biTLdoxmtiV/VDj4H0HxNOSpdbTrE8AocVsKBQRR0nJQNMpjFP3XU0YO7qusZCwk1wGALDTLi9 BhEd6OPJkngaxKMcpZ5XXSZJ44Q3CX2B7vzNW8DuVn7g3tpFl5aGr3ezAtag004yI0IuDnv7tu G8aaOhR+Hlp1+VBJri/Hff2sDrK9pWq1PmthZYwenJTck+6ka0toujuQDmWnNiT7VvRtqQS02T /dwGgO+gwnCir66Vw2+KAHsmr4XbJljiWeVmSreG1wFg1Iuw1uzQuffg99t/oWkVNGR9YV/wbd nAk= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:46 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 05/16] dt-bindings: update sifive clint compatible string Date: Wed, 3 Feb 2021 21:59:02 +0900 Message-Id: <20210203125913.390949-6-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the "canaan,k210-clint" compatible string to the Sifive clint bindings to indicate the use of the "sifive,clint0" IP block in the Canaan Kendryte K210 SoC. The description of the compatible string property is also updated to reflect this addition. Cc: Anup Patel Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra --- .../bindings/timer/sifive,clint.yaml | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 2a0e9cd9fbcf..1a7d582a208f 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,16 +22,23 @@ description: properties: compatible: - items: - - const: sifive,fu540-c000-clint - - const: sifive,clint0 + oneOf: + - items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + - items: + - const: canaan,k210-clint + - const: sifive,clint0 description: - Should be "sifive,-clint" and "sifive,clint". + Should be ",-clint" and "sifive,clint". Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated - onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive - CLINT v0 IP block with no chip integration tweaks. + onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and + "sifive,clint0" for the SiFive CLINT v0 IP block with no chip + integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details reg: From patchwork Wed Feb 3 12:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA4F9C433E0 for ; Wed, 3 Feb 2021 13:02:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9802764F93 for ; Wed, 3 Feb 2021 13:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231335AbhBCNCM (ORCPT ); Wed, 3 Feb 2021 08:02:12 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14165 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231596AbhBCNCD (ORCPT ); Wed, 3 Feb 2021 08:02:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612357917; x=1643893917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HnJ883zL+t4xSM63wnXK5D+H6FssPdmgykJIZOwLcLA=; b=IJaIHgjjU46inZUygjJgMCtI2ZFGwMhcz5a0Lh3l0UoLIRLwcJ/WuWZF okdFm/VxOxidNOge8A8LORrTXjJdSHlVr2vCnK5lkdYBVUxNgxEk+o1d+ rKjvV8AY6NFab0cA8n2wJWISx0rFmGTDbsCZqmjq79Xsj4zz5cCTEr3H7 MbQGeQkmPPzSWkwkU4DrXJhnTKPVaWGV8U3q1Si/Cf027jcgPSlyweu0x 1aAkzSUpI1EFTDg7+pUITGVcsHY9MxlasmuDAiYQQ0Cx9laQZQGpKCUQS j4D/X8O+oOXDFQmZhvWXDpJRmQsJH6ExgV9II6dUQe9X+jAGIsG9Y9UHA Q==; IronPort-SDR: GKrwaeyOaifRLH6I2jk8L/xEEL/Y6H2OGxSSGZXToR8VW4KSdZ9e/mOlGLM+hRRa7QcRh3P3qW lnHXi64OoPBbGcS7M+gFiYrNDIXYkUzibhTfzyss7PyTbhtebrLslgSZZgZYVy9CKghLLJm+Ei cSWKzPN0lLS6/g3Cpi5uW7V7XhKTX2X/YKA/6HUD4YL41twQ5rsuOzVvP1VoWJmK6HwoAuKzbg M7lt+O2bY2npYoalnCbe0zMrwVjQKlBh498vpyZ07xV6Kwn84+WHNxJh149QYLxqYLhQo0E+j2 vO4= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106941" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:40 +0800 IronPort-SDR: Woe7Ln109NKEdP9VDmiFpVwkHwMP/9lsBB/ITkGUFAadt5sWj2+HdH+Jt9DFUbV4uDfnVT9FVo 3r9ejEEy5uJ01BzXWu+tWUUKCG+I/Oo9RxNkyp3tUZYfFnZ/rNZITNcyn7y8IM5zKBLjdzLNyH bt7i0nmqKRbTHlP7Q7piIvBsJ0XelCjp4fTbd/SSKuQQdRBpzCi3So7Xej9j8ASTnKKFzC25Oj TpJNrnWjvLMvugTPGpzEdg0h+J6c/R1uDPn9vKVMyI4qerUR9akUUt5v4eAxzl6G8ZqUHhbz5F bn3XEgFtTA2wif+zXtTce7zp Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:52 -0800 IronPort-SDR: DVW3tS8qC0S/VzUthlpvCggHMkxqZJ/9h6ezOmOBapR2o8TSvvWy5DRP7p+2GI33CWp4kLgjrJ x8KEOCMliKZLP/6tHyJNwYfaJGX5B0Uc0ymWMoc/KCP9JVF+1oSQOXQknlmEr2j/roPhqQKBSg FF8kcEK/eQqAcHJkwtMHeFNSadMYq5wkDvjCLq5dYNKju5uSZJtkiyaeUSEOE/ear2uPRAncxL 2EY7TkfGAJScEf6nN9et0az/qZ4V9cEccyU8cmQy8+KHh9ZQXT2Zik0/EzESf3SSc84EazC3OG P1o= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:50 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 07/16] dt-bindings: fix sifive gpio properties Date: Wed, 3 Feb 2021 21:59:04 +0900 Message-Id: <20210203125913.390949-8-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string to indicate the use of this gpio controller in the Canaan Kendryte K210 SoC. If this compatible string is used, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio IP block. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..2cef18ca737c 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + interrupt mapping one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,10 @@ properties: "#gpio-cells": const: 2 + ngpios: + minimum: 1 + maximum: 32 + gpio-controller: true required: @@ -46,10 +51,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples: From patchwork Wed Feb 3 12:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CB6EC433DB for ; Wed, 3 Feb 2021 13:02:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E40F764F53 for ; Wed, 3 Feb 2021 13:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230526AbhBCNCv (ORCPT ); Wed, 3 Feb 2021 08:02:51 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14163 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231254AbhBCNCn (ORCPT ); Wed, 3 Feb 2021 08:02:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612357976; x=1643893976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3+AZXlQYL+Oi9isOvjtJAUNCWKaUzQuawdKiXp5Ssaw=; b=l8wy4SzLi1Hr15Azmt5cRfi+5U8fcAfYq+cn1fdgFBCopbU7EW86r5vH xjpply3DzZ9knMUqnVm9TJTeWgebSUtEypqbqORBVl1BederEhP9/ETSj wF8kshL0YGmyzXNa1gidukT1UaiQIMEc9XvxUkHPqcQkoGsQkrIU4ZxVz C/YVX2KtLzScRvxGPodtK+/ZXB48zs34OK9STVrPLvrqPuyJ4Afibw+IO w+53xtw4DzUS58gctbdzZgz36iBULSdwihAOjTwQvjKm2mZ6rlijUDhgu ItTWku+6ohYbYlleZeZYzr9ed2xBDy7mT+4IYrzKUfVG8lGt31m7x8++Y g==; IronPort-SDR: npK52oKep8JW2BE+iXiGS41j+GpeBM3mEXmG0gNKO1dE7tFB2cAWuCU+Zu5D3PTZkGxbMD3yCy //opNoQWLAdHH+5E91lwOvY8Eb2R92+EHxVHu3bcN0gPuCFnOSCCXyl6eNXxzX8Emdjt5A/mPM wiyo4Ocpkf8PZP9GzlfPkpDSL3nth98ZV4WLhQkeNZVQypxMRsuWQS6oUyCLoxV+b/xKL4rrnG kD1LmBfTvbO6VCLUjlWB/KEDlYaoAGbEd5QUp6+6QiW/yP4FB/JB4WZVEjQvPkc8GrczC2ICLi oyk= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106947" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:44 +0800 IronPort-SDR: a28cwCH3KEn62hWEUiSJhjUx2A+Jon/hHnNlQnvkD1Xaua0YKW5Q2JDYLL+J04cfvquwRq8IQq +Jinhf7E/4icDm7EBhyTlcH4hRpynIVuQajpnFQjKKRT9cjWTvJJUHnygc13XalgFnEVpOcbGs pw3VyrT+c98+MV5bMROZEQRJJQ3iGHJTnocXXVUWB/MVvUMYeqU9E1kKc5gLe5DY+zCuRnOul7 Myt0sQUfk+KaK065lcDddO+YAH4Xy8waD1oGhvsCrfukqxGQszR5/cnVu3uED1JvG3ca3bnwiU 1lJ1Cs071tkm73h97+s/Fria Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:55 -0800 IronPort-SDR: PmW5rZU2W1wIKOFyvbrI7KFyLTWy/se2sKOgVsgVG2thA2o5kgim69GhEXh5QbtrhpOJH9fRsq S74FSd5hsPe+u4WFOwn/dKDqqlOdXg9EY8GnxmU1JdFSa5KKWpuigUY+Dx5hrDNGqUBCwGY2in mRdRaX3W13O9OAAfh/JXtprnECoKRoLbPhCfYbS5dkMMyMOKK1wIqVE4jkIXlwdgWxP+MB/83p RM5l24TPnwSLIX/UBEye0zbNsnd403Qv+JrFOHbFGKEliJnKCSYC6ZAhhJYXYG0CmDCf8Rd+Vf F/Q= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:53 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 09/16] riscv: Update Canaan Kendryte K210 device tree Date: Wed, 3 Feb 2021 21:59:06 +0900 Message-Id: <20210203125913.390949-10-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the Canaan Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default value selection of the SOC_CANAAN_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes this generic device tree suitable for use with a builtin initramfs with all known K210 based boards. These changes result in the K210_CLK_ACLK clock ID to be unused and removed from the dt-bindings k210-clk.h header file. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the K210. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/canaan/k210.dts | 23 - arch/riscv/boot/dts/canaan/k210.dtsi | 535 +++++++++++++++++++- arch/riscv/boot/dts/canaan/k210_generic.dts | 46 ++ include/dt-bindings/clock/k210-clk.h | 1 - 5 files changed, 554 insertions(+), 53 deletions(-) delete mode 100644 arch/riscv/boot/dts/canaan/k210.dts create mode 100644 arch/riscv/boot/dts/canaan/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6402746c68f3..7efcece8896c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -51,7 +51,7 @@ config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN depends on SOC_CANAAN_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/canaan/k210.dts b/arch/riscv/boot/dts/canaan/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/canaan/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 354b263195a3..63c1f4c98d6c 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include / { /* @@ -12,14 +14,33 @@ / { */ #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210"; + compatible = "canaan,kendryte-k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; }; /* - * The K210 has an sv39 MMU following the priviledge specification v1.9. + * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". @@ -30,14 +51,14 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <0>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -46,14 +67,14 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <1>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -64,10 +85,15 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { @@ -81,40 +107,493 @@ in0: oscillator { soc { #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210-soc", "simple-bus"; + compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + debug0: debug@0 { + compatible = "canaan,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + status = "disabled"; }; clint0: clint@2000000 { - #interrupt-cells = <1>; - compatible = "riscv,clint0"; + compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; }; - plic0: interrupt-controller@c000000 { + plic0: interrupt-controller@C000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + #address-cells = <0>; + compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; - riscv,max-priority = <7>; }; uarths0: serial@38000000 { - compatible = "kendryte,k210-uarths", "sifive,uart0"; + compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "canaan,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "canaan,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "canaan,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio-port@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + ngpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,k210-spi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "canaan,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "canaan,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "canaan,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "canaan,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + canaan,k210-misc-offset = <&sysctl 84>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "canaan,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "canaan,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; }; }; }; diff --git a/arch/riscv/boot/dts/canaan/k210_generic.dts b/arch/riscv/boot/dts/canaan/k210_generic.dts new file mode 100644 index 000000000000..396c8ca4d24d --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pins>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pins: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pins: uarths-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index a48176ad3c23..b2de702cbf75 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -9,7 +9,6 @@ /* * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_ACLK 0 #define K210_CLK_CPU 0 #define K210_CLK_SRAM0 1 #define K210_CLK_SRAM1 2 From patchwork Wed Feb 3 12:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5A56C433DB for ; Wed, 3 Feb 2021 13:03:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E22F64F53 for ; Wed, 3 Feb 2021 13:03:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230034AbhBCND2 (ORCPT ); Wed, 3 Feb 2021 08:03:28 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14157 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbhBCND0 (ORCPT ); Wed, 3 Feb 2021 08:03:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612358042; x=1643894042; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cLJLy/HsfaKJnI40HMcMyu6lTnD7VmKbWkTSB5pV0yE=; b=bplNr+6Wz0ZTcT0lDrwYOwGOTvoW6tnXrXTSfAKchkawiyidWhsEoap4 1rhgCz2cSS6/vNXJceYAxzhaym6kljZOCWYZgYAKm16X5sWBryHHkIyvF wGP1OFVvfjNzedv4YvtFVrH88aVSPVkhI0cB6iiZTHVWV8YPm14adnsQL D9YzQu1gjVPLJXSVK2G8BIquOVdTdyAYtk4nMjL7HIXnCAcaU8x3U3ZkS 1lMGqnonhMohxvbUWdbX1oiyt3z2YWgXKWbprZjnDAFwOJQKBboWGvbv7 +0MjrUc41bgKkjze571UXe+4JyNuz1kECZ9eIY5UNaXXkF+g1GtWLGeRk A==; IronPort-SDR: SHlFIzeQj1l8wlEz4iykymxJWUWiwFbfqMefVrIAp4Oyk//mDWSDid+DKybcZNyJP0hB1l97Jk /KQu+vMTU2n5vwMy0XcODCtKMngcDYzCO7OdN9gcExxWkCTVqoYYkqV/nF7M/rL37F8rvECqXt ygPi/fxRa+lV2mHwpbOIKZIZGAb9eFy+5YYwZ4zBpQywkA9GjRXLOHx365IDzea9l8eSApgJ9k 4ZiY94wmBw1AjzcZnA2NO0vhQOrNkXh3je5jV2Dv+YauRQ6KRjl9xOkhYB2m1ei8RpVvBGJb+w FU8= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106954" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:49 +0800 IronPort-SDR: 73I7uHGPgAIE2lsC7YCmMwtHqBz07YshWO2JVhQG8Kn2fjuufFCgY6u6tz3IzAezkXUC3kgQWE ijyBekYsUlz1Tuj6s5YN9vXM7pieDbwml/m191s8j72FKCgrYGbjjXEQpwbm1L0R6p4ZLZoDGQ dUiHxXFZh9N5wo/9P81t3V1AalOmWB9lJJgPi8wfm36nvs8AgdzpvXW1n/nvmnt3JKT27iI0UN 8GqIhCeSvs2ljM1Po36xsq2+hZaP6xdj/WuKXIhXNeuEoDM4zMto4iIoSK05GUnzP+D5v4UPtI gexZzSmjX3UWUy95JgCKmXD/ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:43:58 -0800 IronPort-SDR: FQMMPJyweYod6LvjosWTuQbwNrGKdhixIM6NbZpvmbPn9rg2NlZBnaL+tTNhTs8sHO0JYOhFJx QEp87BP8SG9HmMums5TjMAUi1S+7cgIr+PcYGK6Suf1rzpWfo1tAdoQ+aoiyS2pvC53x7WQ4aW B79pH0UxWhAIx1uKGrtawhH44x/QOBP6JvdGgRkrWpW0x0Ofl1208tv5Tgh2OH+RrTXp+/pWif OF/wBE3IPmyC45iB1PZ6+TNg30CmqbHk/SpyULW52GygF4/V/yOY9q3Pbr42dniWYIzX1HPyrH RF0= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 04:59:57 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 11/16] riscv: Add SiPeed MAIX DOCK board device tree Date: Wed, 3 Feb 2021 21:59:08 +0900 Message-Id: <20210203125913.390949-12-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_dock.dts for the SiPeed MAIX DOCK m1 and m1w boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maix_dock.dts | 236 ++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts new file mode 100644 index 000000000000..fae0149a8740 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX Dock"; + compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* + * Note: the board wiring drawing documents green on + * gpio #4, red on gpio #5 and blue on gpio #6. However, + * the board is actually wired differently as defined here. + */ + led0 { + color = ; + label = "blue"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "green"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "red"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Wed Feb 3 12:59:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 375556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE921C433E0 for ; Wed, 3 Feb 2021 13:03:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91B2764F6C for ; Wed, 3 Feb 2021 13:03:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbhBCNDi (ORCPT ); Wed, 3 Feb 2021 08:03:38 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:14165 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230151AbhBCNDh (ORCPT ); Wed, 3 Feb 2021 08:03:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612358058; x=1643894058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NxkrMnisgB5Y7CCjo51izxzf/ZM8UZEu9H+xpU97oZI=; b=Vc3Wg9pU8egdT78oytfMxsNkESxiloeax4PlxXO9zwF9QEUXSETIZM/Y LjbGo9avUDN3PT84LZvtjcibrhU+c/znO2aARTvH47NzAcptszW0hWp3O p+07ZPoA8oH6cOEj6HcYUNSTwbFksPEDopb42TKo9BBy0xCe6ekEL5qDZ 8E9JWgBCfMsfpAgwcoj/ui9GV9f83tMln69upvAzAyFIK7bWOhvwaZCrO SZM1aSycOs+qf1NeI+A5x0f6gXPggd1Tgig/MK6KVcxyxy7iSXlQ3jXx1 ws8gelO0wNpy7prNQpt+GC5FZiM5bjP4LamYnc0q5zL51vcJHn1reRSjS A==; IronPort-SDR: Np6Mo7KLfhr1YTpOe0JtXm4TXoxCJRQrqsem2qr3GEIAnuhwaGyyI4dhBLdxU9Wgpo11biJJyC FhmdkenA843U2njimhOjEtMuDJYUEW70Y460dD5nXzggu14QJAgxRcxPUaW8d1qYikxlfVr7tW NfwMdoTASlUUqrhhAyGzVAOtKsHfsRR0hxFKLfkKUBuDuhki4cbrXmtKlU77tQBfEDsC+CFFhH ltxnemnw67wHXXnorvzfFL+zTZ6nCvZcasRxWMglYpeCj1tXiekfVTygoRLarFAjj5ktZuMa82 QXc= X-IronPort-AV: E=Sophos;i="5.79,398,1602518400"; d="scan'208";a="263106959" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 03 Feb 2021 21:08:54 +0800 IronPort-SDR: zfvyXLBotE0OUz5Lu1/eXABfu0E6fYH3kKAO5xikSJ6SYPKUzhJpMmW6edyfkKeawG2mCwxkPJ 0DrryILAKSYy6b+tWs/kbPGCEWNjPmRgCqOtK7Mp5kvg0p0U2yg5oiRh3wthLr76jGBri3taYt bX/gRm6bRsjOrwSPEev9osZNEfLlVf8bfoDxgdqGbSAhmWu9GzXXJQUoFcOn7XyIWiVPyoyX7p UhJt5WKtNj0zcTc7x7rIiFjNr9WpyP/c1cyTxdLpRy2aHwY607YOZ6eYXyQ1BucTBrMxzFnWXH pn5kObSLdO/7sYw4OGiTpLsO Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 04:44:02 -0800 IronPort-SDR: 8cJ3MwjpEzrQuyv/9SpF+77Fpo9n0WpN7GHLvqKNsxq27jugfIL3Wa3WRc3z1DOwjxKcgvpQC2 nQZxO0Z532r25VyyHC1eNAN30KE0ehfkiVe2oUDGDH444zDTeo/PIRBr+Won0MULhUX8jNNEvQ KANt+mqpZxVLXLWVug+4qAga+LXDItH1m/S1MRKTy4+LLctdjmbWNXvhvEUPmRFKTpzXwC4hn+ 7QwcdYJg/hRZCn1sm7z8tauhJTTeNa3bCdwHjru76q+aB6iFHztY3objIIWUj6r6a4f9m4Ebhz NKw= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Feb 2021 05:00:00 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v15 13/16] riscv: Add SiPeed MAIXDUINO board device tree Date: Wed, 3 Feb 2021 21:59:10 +0900 Message-Id: <20210203125913.390949-14-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210203125913.390949-1-damien.lemoal@wdc.com> References: <20210203125913.390949-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maixduino.dts for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maixduino.dts | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts new file mode 100644 index 000000000000..804edc45eeeb --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; + + vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + power-supply = <&vcc_3v3>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};