From patchwork Fri Mar 9 16:35:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131158 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1194978lja; Fri, 9 Mar 2018 08:37:46 -0800 (PST) X-Google-Smtp-Source: AG47ELtCRpiAD4pXo3qKadltDZTDlDXdj5Z6hIxyH8GpsuG3RLlEOb6yxC9XCiysbjNDFMCgzn/e X-Received: by 10.36.116.130 with SMTP id o124mr4512931itc.30.1520613466525; Fri, 09 Mar 2018 08:37:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613466; cv=none; d=google.com; s=arc-20160816; b=t4pS5sGy1QE7iG/iuYh+XFYc90UjtRHrugk7sbDowXRXNAC0zMXQZwdFxsyj2R2orP ixDw5CMVDrn0OmGbylX1YvWn9XJrMRpg7dhR8e0osxhyr4jAduOsXOorJW2vITa+Ngcd 5p6cFl+plyU4VDFf+cQdIKrDeYMF++Ag4HtnaVKQ5CXek4jCX18aK4yjUg44A/Viox2x GNUMo2uConNBZ2R10dzzCvcSXUy5YiDJkNhtGFgIb77Ao0cC4MDjwBnM0C1kk7uzvZMP oWt33IyELLiVy/QT6G9gAoAor2IAlJn0xLi4OQu9nrex+MD5f+Y+REpa8Iuvw1vBUYZ9 x6UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=HgN+aZlfZt3yh2Yvd2ZIHbmXKCyAfL4KxFzPvw3fNvw=; b=zIziuQ3c8Bfkp8fnUWfLwDMtxW7lcn3khKSpEdA2qCTD3RkVcHDQHB2P3dKcicoX0I /tkWv9h5mCIO+Kh/w1juKTGg1dWkaNKKJimPOh0vCm1T0WDPmj5Y6/E4KjOSmfwrak9O x2Sv9PZb4tllxpE+fr+X0SMvVsXebv1e6mm/8UdjuPW6A2eM5OTns1JFpVIGv2cFoXgl GrjMkH+oK5KbVKoH9Ng+SRj77wtZ7pBaYYwjWC37nfaGUoMgpGhnlVLLMQYjWhM88Bj2 pS+JMaL1BG+4kBRNLpWhG6ttNauylvkeHsiT7a1o8BYzhIghd/+14yaByHarU6TJpALX jL/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p6si1155054ioe.268.2018.03.09.08.37.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:37:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzP-0000gN-2Z; Fri, 09 Mar 2018 16:35:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzN-0000gB-Q2 for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:35:25 +0000 X-Inumbo-ID: 32fdc1ac-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 32fdc1ac-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:47 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5316E15B2; Fri, 9 Mar 2018 08:35:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67EB93F487; Fri, 9 Mar 2018 08:35:18 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:06 +0000 Message-Id: <20180309163511.18808-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 1/6] xen/arm: gic: Fix indentation in gic_update_one_lr X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-vgic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 61f093db50..e3cb47e80e 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -197,8 +197,8 @@ static void gic_update_one_lr(struct vcpu *v, int i) { if ( p->desc == NULL ) { - lr_val.state |= GICH_LR_PENDING; - gic_hw_ops->write_lr(i, &lr_val); + lr_val.state |= GICH_LR_PENDING; + gic_hw_ops->write_lr(i, &lr_val); } else gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", From patchwork Fri Mar 9 16:35:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131156 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1194893lja; Fri, 9 Mar 2018 08:37:41 -0800 (PST) X-Google-Smtp-Source: AG47ELudLcKGo5mUqF/BbjBU2G/TGvpr1yBdE0hjH97NzWMtvNTzSZBN08KJXa4HAwneuTnE148f X-Received: by 2002:a24:108c:: with SMTP id 134-v6mr4096935ity.94.1520613461790; Fri, 09 Mar 2018 08:37:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613461; cv=none; d=google.com; s=arc-20160816; b=GQvIHaOjLCfCqDcI0j7QU7U4dJW+O02FOv/UyEpQXpVoK1Z0vVjoJFjZoH1sRz2vuR bjrrrpiq9W/teMwZSaRNvd+A1DsvXFyFTQHveYw81hwFjxIFkDDIuMEtAhRFlw9qDtau WAr03oD+sI6eIi+PHOoddYKT6xitZYK5LAECu61WOsdP6GI7/MWaOVIj2s/jAe1CKzHL fnxryPgQkGxKR2vGQHMKKaMxArPeSYfQkpvR8PrekOu6q8awJxDA5/QZ+HrBY3i7HbUX p/tCzuWgEFOI/Qe4+mU7f3ZQ/mVPOgbkgO92jZ3dxoI0X+qk8LoerCHotvqce1c3aEe5 ONBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=2MU1sY5c/t1IMby3fF6Zrqy8KBzU1drIUVOxuuqMOdk=; b=u/ww6RzHA8v+EjX6QSK9i8mnH0BOlhu/B+RlGbnr3GWVrFYnQO8HAZPEzWxWUgweb/ GwfGk+6Ws2J/e1czwC7qRXFC8wuXsV0x8wVseKAtnKYFGNrt3gyPzKhu4hLUTpXqm0Nl kux9TK0RinhnrPsfBvi+JLWNol3JaXXGrYZOo6xCGOhrMuWVwIIaI7/2DXTOEC19urd5 rABppIZm4JLGY6jcAR7b6DUGefz8bS2WVwJiYx5KVPjdH9W/1LRkbsxWgGaFNlKrIkTk wWHuSPp3H/X9o+XUtY3r+tetEPfKPM8liVJqLwPz03ikXSUdenz2tazke1w98pF+CZYO aypA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l93si1205079iod.321.2018.03.09.08.37.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:37:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzQ-0000hP-Py; Fri, 09 Mar 2018 16:35:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzP-0000gC-ND for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:35:27 +0000 X-Inumbo-ID: 33b5021c-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 33b5021c-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CA171529; Fri, 9 Mar 2018 08:35:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9183B3F487; Fri, 9 Mar 2018 08:35:19 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:07 +0000 Message-Id: <20180309163511.18808-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 2/6] xen/arm: vgic: Override the group in lr everytime X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall At the moment, write_lr is assuming the caller will set correctly the group. However the group should always be 0 when the guest is using vGICv2 and 1 for vGICv3. As the caller should not care about the group, override it directly. With that change, write_lr is now behaving like update_lr for the group. Signed-off-by: Julien Grall --- xen/arch/arm/gic-v2.c | 4 +--- xen/arch/arm/gic-v3.c | 11 ++++++++--- xen/include/asm-arm/gic.h | 1 - 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index f16e17c1a3..fc105c08b8 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -469,7 +469,6 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; - lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -483,8 +482,7 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) | ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) - << GICH_V2_LR_HW_SHIFT) | - ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); + << GICH_V2_LR_HW_SHIFT)); writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 09b49a07d5..0dfa1a1e08 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1012,7 +1012,6 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; - lr_reg->grp = (lrv >> ICH_LR_GRP_SHIFT) & ICH_LR_GRP_MASK; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1023,8 +1022,14 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) | - ((u64)(lr->grp & ICH_LR_GRP_MASK) << ICH_LR_GRP_SHIFT) ); + ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) ); + + /* + * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 + * would result in a FIQ, which will not be expected by the guest OS. + */ + if ( current->domain->arch.vgic.version == GIC_V3 ) + lrv |= ICH_LR_GRP1; gicv3_ich_write_lr(lr_reg, lrv); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 49cb94f792..1eb08b856e 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -211,7 +211,6 @@ struct gic_lr { uint8_t priority; uint8_t state; uint8_t hw_status; - uint8_t grp; }; enum gic_version { From patchwork Fri Mar 9 16:35:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131162 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1198383lja; Fri, 9 Mar 2018 08:41:26 -0800 (PST) X-Google-Smtp-Source: AG47ELvYuQJ7KadEpYrL3hVENb07CyzWhU5n1ttAH360WFhGzXHBEYxhVCgBjjeWNnq7GjSGunOv X-Received: by 10.107.59.130 with SMTP id i124mr36001918ioa.129.1520613686289; Fri, 09 Mar 2018 08:41:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613686; cv=none; d=google.com; s=arc-20160816; b=V21za7uIo71skj3bUvcqXWjyjz5JyfdwwPEz++pAw9fedjtZp4oalYs37Q+EuaXbCN JkiTKr0+2MGEsiAdg3ktlWqU+MzbtP8QzYHfRAGkeLBQH2Ah5GGruBda2Rqm0RXsBo6n wbMqcafOdBVWkSxGRxM2Q9RpgzR+jVdpZ4xS+VeMIz1qwqD6O8UwDdJA+y9Vi8lyLDPM TIxrDsRT1ZBlt3zoQtiGpndiJR0dEXu8850pHpWN7Ut+XqrnFFgvLTMatErxZu1S6GIH I/5h7PzC6Ru0VkKCXuKeq9F43SDDCm4lZ4cheRqRghLlNDsDESf0dHfknHewQqlaKjGn GsrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=A0QjkeA5prjZKP/qAXO+JMD68p8m7ApX/aYkq0Grw5Q=; b=HaluV+W6l4ujDefdbBR1aX3EPWjbfdB76Eh7zO/5LEZlBKU8bSrFQda+kIbZC8pDxy qYQRuiSsJi8WyXAi3SCIePpywsKttUelF4QNFFZifmm/klnbDEzQyvyRhmelSH2xz9km CcqAeWeTepPPXxWPoY3yADsXECNlkVrtzZidtborW9DC/OSowcbtMw2Ugw3JQxgyYYTk q26DNEkgroxdxBaepA/qhwNxj+OULiWiRTIwhr4PD6iXZEnTrdwqyQun138GBlDGQmjl epf/MyIgDm1EOYKYXvjTvkwC4jhw42IB9Jj3Nuc6KdlnGV2VoGbyHwqbM40H2n24ASeR oP3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p8si1363498ioo.305.2018.03.09.08.41.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:41:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3K-0001aA-0b; Fri, 09 Mar 2018 16:39:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3J-0001YA-GZ for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:39:29 +0000 X-Inumbo-ID: 34618d0e-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 34618d0e-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:49 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A636015B2; Fri, 9 Mar 2018 08:35:21 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BAF613F487; Fri, 9 Mar 2018 08:35:20 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:08 +0000 Message-Id: <20180309163511.18808-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 3/6] xen/arm: gic: Use bool instead of uint8_t for the hw_status in gic_lr X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall hw_status can only be 1 or 0. So convert to a bool. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 9 +++++---- xen/arch/arm/gic-v3.c | 8 +++++--- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index fc105c08b8..23223575a2 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -468,7 +468,7 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; + lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -480,9 +480,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) << GICH_V2_LR_PRIORITY_SHIFT) | ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) - << GICH_V2_LR_STATE_SHIFT) | - ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) - << GICH_V2_LR_HW_SHIFT)); + << GICH_V2_LR_STATE_SHIFT) ); + + if ( lr_reg->hw_status ) + lrv |= GICH_V2_LR_HW; writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0dfa1a1e08..0711e509a6 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1011,7 +1011,7 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; + lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1021,8 +1021,10 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) ); + ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) ); + + if ( lr->hw_status ) + lrv |= ICH_LR_HW; /* * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1eb08b856e..daec51499c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -210,7 +210,7 @@ struct gic_lr { uint32_t virq; uint8_t priority; uint8_t state; - uint8_t hw_status; + bool hw_status; }; enum gic_version { From patchwork Fri Mar 9 16:35:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131160 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1196438lja; Fri, 9 Mar 2018 08:39:24 -0800 (PST) X-Google-Smtp-Source: AG47ELseWu4ZJOlYtJypf/AJdNt+df192E0ePGFqsEnLoCIvPdM4vBN7qEHIT1MG03bP1bWPK+t2 X-Received: by 10.107.36.204 with SMTP id k195mr35643496iok.131.1520613564023; Fri, 09 Mar 2018 08:39:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613564; cv=none; d=google.com; s=arc-20160816; b=uRlW4hzX76jT2mQrfovqTZSkecKIzYqx1VdCAIfd5yeTnsoO8k9Y80aXAsOSVNb9Y6 wBua1/GfTTJO4NYlozLoKeKQ6CAmZzWhg2eBB1GJKQF2h1XDoQeaX+pZGFBhBaJtB6hC 4DErQ5F1T9+w1YmA3dxACmuzsHdYzjjeYdTz1BGsiTt4TElV8/t0a35LA5ROT76/mbnT 8TZ5mvGVCQ8n6+ndTvXiDdj4QtVG1ccUk8J9/QatKmTkqHRQSLXguJ2Oa07AzsI7PS1h aVXCeCRnwh9h4UE1D5O3XpAOTPINvR5IXCgl4rBiSbVksVs7NEfXgQtGHiWY3lKLn2tI UF5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=63CS8qQWCJYT+4FVvsE7l5xEld/HwoFbmrEvLiMALkU=; b=W4fu3S99u0uQ4/Qn3RoO0ND+eNeVey+R4wczUF2TAFadWY7rveR0TkGdA9d4yYyznA zM2LZr9rUPgJBePsC45Vd63P4Bacym7YiOuTOKzeHcG7f4WA7kSsB1q6IDkpp2oIk8GJ xoxvgsbH5OxbRqkefhuMo3YArjlO5xRdBguvnM1TspdX2Kf2jmladJ0Dz4+AR0895SZ+ pB/w6j564rmzThkpmdFnJAlRaNt+sfFgV9HxCY8YUuWbDWtkGG5OP0bK+DZNTFzye3b1 KRPkI54N1ZJ7w6K62QmVeTRIt68TAKUe98rFbuEi8EGKAhVpgb0ZnIJvbmnjWUv3IDMx 2ldQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d26si1142274iob.50.2018.03.09.08.39.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:39:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL1N-0001GW-Ad; Fri, 09 Mar 2018 16:37:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL1M-0001Fj-BT for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:37:28 +0000 X-Inumbo-ID: 3514f618-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 3514f618-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:50 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D116E165C; Fri, 9 Mar 2018 08:35:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E4F903F487; Fri, 9 Mar 2018 08:35:21 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:09 +0000 Message-Id: <20180309163511.18808-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 4/6] xen/arm: gic: Split the field state in gic_lr in 2 fields active and pending X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall Mostly making the code nicer to read. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 15 +++++++++++---- xen/arch/arm/gic-v3.c | 12 +++++++++--- xen/arch/arm/gic-vgic.c | 6 +++--- xen/include/asm-arm/gic.h | 3 ++- xen/include/asm-arm/gic_v3_defs.h | 2 ++ 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 23223575a2..90d8f652d3 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -51,6 +51,8 @@ #define GICH_V2_LR_PHYSICAL_SHIFT 10 #define GICH_V2_LR_STATE_MASK 0x3 #define GICH_V2_LR_STATE_SHIFT 28 +#define GICH_V2_LR_PENDING (1U << 28) +#define GICH_V2_LR_ACTIVE (1U << 29) #define GICH_V2_LR_PRIORITY_SHIFT 23 #define GICH_V2_LR_PRIORITY_MASK 0x1f #define GICH_V2_LR_HW_SHIFT 31 @@ -467,7 +469,8 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; - lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; + lr_reg->pending = (lrv & GICH_V2_LR_PENDING) == GICH_V2_LR_PENDING; + lr_reg->active = (lrv & GICH_V2_LR_ACTIVE) == GICH_V2_LR_ACTIVE; lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; } @@ -478,9 +481,13 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) | ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) - << GICH_V2_LR_PRIORITY_SHIFT) | - ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) - << GICH_V2_LR_STATE_SHIFT) ); + << GICH_V2_LR_PRIORITY_SHIFT) ); + + if ( lr_reg->active ) + lrv |= GICH_V2_LR_ACTIVE; + + if ( lr_reg->pending ) + lrv |= GICH_V2_LR_PENDING; if ( lr_reg->hw_status ) lrv |= GICH_V2_LR_HW; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0711e509a6..4dbbf0afd2 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1010,7 +1010,8 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->virq = (lrv >> ICH_LR_VIRTUAL_SHIFT) & ICH_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; - lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; + lr_reg->pending = (lrv & ICH_LR_STATE_PENDING) == ICH_LR_STATE_PENDING; + lr_reg->active = (lrv & ICH_LR_STATE_ACTIVE) == ICH_LR_STATE_ACTIVE; lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; } @@ -1020,8 +1021,13 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | - ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) ); + ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) ); + + if ( lr->active ) + lrv |= ICH_LR_STATE_ACTIVE; + + if ( lr->pending ) + lrv |= ICH_LR_STATE_PENDING; if ( lr->hw_status ) lrv |= ICH_LR_HW; diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index e3cb47e80e..d831b35525 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -189,7 +189,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) return; } - if ( lr_val.state & GICH_LR_ACTIVE ) + if ( lr_val.active ) { set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && @@ -197,7 +197,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) { if ( p->desc == NULL ) { - lr_val.state |= GICH_LR_PENDING; + lr_val.pending = true; gic_hw_ops->write_lr(i, &lr_val); } else @@ -205,7 +205,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) irq, v->domain->domain_id, v->vcpu_id, i); } } - else if ( lr_val.state & GICH_LR_PENDING ) + else if ( lr_val.pending ) { int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); #ifdef GIC_DEBUG diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index daec51499c..c32861d4fa 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -209,7 +209,8 @@ struct gic_lr { /* Virtual IRQ */ uint32_t virq; uint8_t priority; - uint8_t state; + bool active; + bool pending; bool hw_status; }; diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index ccb72cf0f1..817bb0d5c7 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -171,6 +171,8 @@ #define ICH_LR_PHYSICAL_SHIFT 32 #define ICH_LR_STATE_MASK 0x3 #define ICH_LR_STATE_SHIFT 62 +#define ICH_LR_STATE_PENDING (1UL << 62) +#define ICH_LR_STATE_ACTIVE (1UL << 63) #define ICH_LR_PRIORITY_MASK 0xff #define ICH_LR_PRIORITY_SHIFT 48 #define ICH_LR_HW_MASK 0x1 From patchwork Fri Mar 9 16:35:10 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id s3si1159172ioe.131.2018.03.09.08.41.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:41:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3E-0001YD-Ll; Fri, 09 Mar 2018 16:39:24 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3D-0001XT-Ah for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:39:23 +0000 X-Inumbo-ID: 35cd7af6-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 35cd7af6-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:51 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06DC21529; Fri, 9 Mar 2018 08:35:24 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B84B3F487; Fri, 9 Mar 2018 08:35:22 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:10 +0000 Message-Id: <20180309163511.18808-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 5/6] xen/arm: GIC: Only set pirq in the LR when hw_status is set X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall The field pirq should only be valid when the virtual interrupt is associated to a physical interrupt. This change will help to extend gic_lr for supporting specific virtual interrupt field (e.g eoi, source) that clashes with the PIRQ field. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 13 ++++++++++--- xen/arch/arm/gic-v3.c | 10 +++++++--- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 90d8f652d3..daf8c61258 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -466,20 +466,24 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) uint32_t lrv; lrv = readl_gich(GICH_LR + lr * 4); - lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->pending = (lrv & GICH_V2_LR_PENDING) == GICH_V2_LR_PENDING; lr_reg->active = (lrv & GICH_V2_LR_ACTIVE) == GICH_V2_LR_ACTIVE; lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; + + if ( lr_reg->hw_status ) + { + lr_reg->pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; + lr_reg->pirq &= GICH_V2_LR_PHYSICAL_MASK; + } } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) { uint32_t lrv = 0; - lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) | - ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | + lrv = (((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) << GICH_V2_LR_PRIORITY_SHIFT) ); @@ -490,7 +494,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) lrv |= GICH_V2_LR_PENDING; if ( lr_reg->hw_status ) + { lrv |= GICH_V2_LR_HW; + lrv |= lr_reg->pirq << GICH_V2_LR_PHYSICAL_SHIFT; + } writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 4dbbf0afd2..f73d386df1 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1006,21 +1006,22 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lrv = gicv3_ich_read_lr(lr); - lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> ICH_LR_VIRTUAL_SHIFT) & ICH_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->pending = (lrv & ICH_LR_STATE_PENDING) == ICH_LR_STATE_PENDING; lr_reg->active = (lrv & ICH_LR_STATE_ACTIVE) == ICH_LR_STATE_ACTIVE; lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; + + if ( lr_reg->hw_status ) + lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) { uint64_t lrv = 0; - lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| - ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | + lrv = ( ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) ); if ( lr->active ) @@ -1030,7 +1031,10 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv |= ICH_LR_STATE_PENDING; if ( lr->hw_status ) + { lrv |= ICH_LR_HW; + lrv |= (uint64_t)lr->pirq << ICH_LR_PHYSICAL_SHIFT; + } /* * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index c32861d4fa..545901b120 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -204,7 +204,7 @@ union gic_state_data { * The LR register format is different for GIC HW version */ struct gic_lr { - /* Physical IRQ */ + /* Physical IRQ -> Only set when hw_status is set. */ uint32_t pirq; /* Virtual IRQ */ uint32_t virq; From patchwork Fri Mar 9 16:35:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131159 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1195070lja; Fri, 9 Mar 2018 08:37:52 -0800 (PST) X-Google-Smtp-Source: AG47ELti5iteNWQJPivrzuJs8uh+ONmy8wRwZuukq1jN+ia0Ly6BGXjB7DB+RJvtwrBSpRHc6zLA X-Received: by 10.107.143.23 with SMTP id r23mr36172470iod.191.1520613472303; Fri, 09 Mar 2018 08:37:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613472; cv=none; d=google.com; s=arc-20160816; b=HDE8nrnW9ye5gkDhxCO0jMF5NsijdrMULPaZ9N6pVa5wHeh7XVF8fSCsvtoix1F8Z+ 6MlCgHYLlgQc8ZJc62hjpSga8yGjwU8ZccTLJADLePdpZoI+mxuVAzgzmIpZhIv3eUKd qlb2OnKcU2+ExzA0mvH/S1omXgom/f4xK21sKranJFrTQiAwXh/hvk74f41tO4C4jrlC BB/SPNLXEhL7fMMk/QxFq57K3cz75CdSFYl52MVpk81EhNnjsOjNsrVBI7Ug8FFYhNS9 LU9c6GRFvmpXmmbV17kUNUIIwJjv7B0umfYegmLH6NAsuVQcvAuWzqBn5xiSHnC9B/Dl 5Xrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=VN+NybTp+RfRcGS4iqg3AWvAvaU9yZ6vBHcVGkxWO+Q=; b=dUb+75tpBm4OVi4iplNEaOmLCx5w1hRLJoPqLVg3FQWvN5FTehaTZMP6HYYjmnOOfy 67MZViN0TYrNwyyfGKHbOS0kUggW2csV5hODTmx+Qa/E73QdVc+xa35LLodr7w+n3+bS bHwEmY/a9/3/2ULjPCmAWX1jmO1dZc3jrYfnJySkeYkQQ82VBaA23Z6aYSVdzq+aGWeD PN+2avclyggPSxLEB/PvxDr5xQvQx2tBSsD3TpumaMci7PJB+OiWev6tsQgUFoK4U81z 1o4IzJoOJvzDP8LlO3PHq18FY7Bn+Wl8KEpFxCnzstBDaHd6uK7vgPtJuRt9J3JMW0Pr dxGg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p69si1198318iod.279.2018.03.09.08.37.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:37:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzQ-0000hE-JE; Fri, 09 Mar 2018 16:35:28 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzP-0000gU-E5 for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:35:27 +0000 X-Inumbo-ID: b3ae79ca-23b7-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id b3ae79ca-23b7-11e8-ba59-bc764e045a96; Fri, 09 Mar 2018 17:34:13 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54C241529; Fri, 9 Mar 2018 08:35:25 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45B5F3F487; Fri, 9 Mar 2018 08:35:24 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:11 +0000 Message-Id: <20180309163511.18808-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, Andre Przywara Subject: [Xen-devel] [PATCH 6/6] ARM: GIC: extend LR read/write functions to cover EOI and source X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Andre Przywara So far our LR read/write functions do not handle the EOI bit and the source CPUID bits in an LR, because the current VGIC implementation does not use them. Extend the gic_lr data structure to hold these bits of information by using a union to differentiate field used depending on whether the vIRQ has a corresponding pIRQ. Note that source is not covered by GICv3 LR. This allows the new VGIC to use this information. Signed-off-by: Andre Przywara Signed-off-by: Julien Grall --- xen/arch/arm/gic-v2.c | 22 +++++++++++++++++++--- xen/arch/arm/gic-v3.c | 11 +++++++++-- xen/include/asm-arm/gic.h | 16 ++++++++++++++-- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index daf8c61258..69f8d6044a 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -474,8 +474,17 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) if ( lr_reg->hw_status ) { - lr_reg->pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; - lr_reg->pirq &= GICH_V2_LR_PHYSICAL_MASK; + lr_reg->h.pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; + lr_reg->h.pirq &= GICH_V2_LR_PHYSICAL_MASK; + } + else + { + lr_reg->v.eoi = (lrv & GICH_V2_LR_MAINTENANCE_IRQ) == GICH_V2_LR_MAINTENANCE_IRQ; + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ + lr_reg->v.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) & GICH_V2_LR_CPUID_MASK; } } @@ -496,7 +505,14 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) if ( lr_reg->hw_status ) { lrv |= GICH_V2_LR_HW; - lrv |= lr_reg->pirq << GICH_V2_LR_PHYSICAL_SHIFT; + lrv |= lr_reg->h.pirq << GICH_V2_LR_PHYSICAL_SHIFT; + } + else + { + if ( lr_reg->v.eoi ) + lrv |= GICH_V2_LR_MAINTENANCE_IRQ; + if ( lr_reg->virq < NR_GIC_SGI ) + lrv |= (uint32_t)lr_reg->v.source << GICH_V2_LR_CPUID_SHIFT; } writel_gich(lrv, GICH_LR + lr * 4); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index f73d386df1..a855069111 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1014,7 +1014,9 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; if ( lr_reg->hw_status ) - lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; + lr_reg->h.pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; + else + lr_reg->v.eoi = (lrv & ICH_LR_MAINTENANCE_IRQ) == ICH_LR_MAINTENANCE_IRQ; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1033,7 +1035,12 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) if ( lr->hw_status ) { lrv |= ICH_LR_HW; - lrv |= (uint64_t)lr->pirq << ICH_LR_PHYSICAL_SHIFT; + lrv |= (uint64_t)lr->h.pirq << ICH_LR_PHYSICAL_SHIFT; + } + else + { + if ( lr->v.eoi ) + lrv |= ICH_LR_MAINTENANCE_IRQ; } /* diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 545901b120..4cf5bb385d 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -204,14 +204,26 @@ union gic_state_data { * The LR register format is different for GIC HW version */ struct gic_lr { - /* Physical IRQ -> Only set when hw_status is set. */ - uint32_t pirq; /* Virtual IRQ */ uint32_t virq; uint8_t priority; bool active; bool pending; bool hw_status; + union + { + /* Only filled when there are a corresponding pIRQ (hw_state = true) */ + struct + { + uint32_t pirq; + } h; + /* Only filled when there are no corresponding pIRQ (hw_state = false) */ + struct + { + bool eoi; + uint8_t source; /* GICv2 only */ + } v; + }; }; enum gic_version {