From patchwork Mon Feb 1 19:16:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 374444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D9CC433E0 for ; Mon, 1 Feb 2021 19:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C158264E8D for ; Mon, 1 Feb 2021 19:17:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbhBATRJ (ORCPT ); Mon, 1 Feb 2021 14:17:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbhBATRI (ORCPT ); Mon, 1 Feb 2021 14:17:08 -0500 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1054BC061573; Mon, 1 Feb 2021 11:16:28 -0800 (PST) Received: by mail-ed1-x534.google.com with SMTP id y8so5053965ede.6; Mon, 01 Feb 2021 11:16:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Vudz7Jq3CovoiOUmAZDu7pX1ATasm53I9HD8Bq8Ch+U=; b=NOlicBRSikm/UtWBLnB71WogDHzgE/ktshfE/+H9dMxldgy4S53TuPHzO6DFWyp7om Tkisu2JF0glF1rVvZId9xYSyvLmsVoHCNRBN4A2sWamEKXSTGHRpOpkTnTqDOg82Spy9 pa232VTfbmnzbh4ZjA/ivPBI2ayKjpEsXY9s8uPYIxWEwX7Om8Amt50CgB1BVWm+Qyva G8O1tsMPBvl/eiaiy8vZU/ADdjoC18CYxDLE0oL8bXFuYlBJKp6/MYkGbhx85TmhqDIX LtgCN4wW4Kj/LeFFca28hSmeRriTBQnbAAiUVRoeoysAIthTT9KGWtO18IjyUOazj5k1 FE9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Vudz7Jq3CovoiOUmAZDu7pX1ATasm53I9HD8Bq8Ch+U=; b=o9YNdaMhCzBWNhOl/+65mKXiiJUhkJhJwa1y0vVCwMshmp46qIBL2YrcRLfhKDsf6X SASiLgOLzqo4YY+3f5LZUyisSPAE3eHL3J0R3+HKvDhymzOvWasZgvFVqvaGMhC/1Q32 mX12DywpnC8gnEPfgcpfHj6BdOE1VsM6lhvdQA+5cw0Kt/6zKRS3aBZDjhsrWNVT9iZS hClIY7sG6IHhyYn575pKWNEeQdHFCfXM/WVr2/fG+uVQOG8J8xYfikTbimBI574Qk/St RXHiqNnQZDcd+TLdCl/hNmLq4qizVqQbJNaBO8H0SYxgUuw3ge8HVywAKsClySUgFi/3 Nkhw== X-Gm-Message-State: AOAM530CFUzmP/8dl32DWn/k9PwZV1bYcUpBEqJnMJZgQTxPiC4UMN99 mSQEB1nq93RQLCRN2dJW70U= X-Google-Smtp-Source: ABdhPJwj/wg6nbbgC4bHudj+wMwJo0zVmkxIcLcYyFNyKLt7bB/XHOd8IiYRotcGBgJyuBgFB5azcw== X-Received: by 2002:a50:fd0b:: with SMTP id i11mr11985392eds.387.1612206986770; Mon, 01 Feb 2021 11:16:26 -0800 (PST) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id a11sm8243630ejc.64.2021.02.01.11.16.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Feb 2021 11:16:26 -0800 (PST) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Date: Mon, 1 Feb 2021 20:16:15 +0100 Message-Id: <20210201191619.32353-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org In the past Rockchip dwc3 usb nodes were manually checked. With the conversion of snps,dwc3.yaml as common document we now can convert rockchip,dwc3.txt to yaml as well. Added properties for rk3399 are: resets reset-names Generic properties that are now also filtered: "#address-cells" "#size-cells" ranges Signed-off-by: Johan Jonker --- .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ----------- .../devicetree/bindings/usb/rockchip,dwc3.yaml | 107 +++++++++++++++++++++ 2 files changed, 107 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted file mode 100644 index 945204932..000000000 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt +++ /dev/null @@ -1,56 +0,0 @@ -Rockchip SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "ref_clk" Controller reference clk, have to be 24 MHz - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS - operation and >= 30MHz for HS operation - "grf_clk" Controller grf clk - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY - -Example device nodes: - - usbdrd3_0: usb@fe800000 { - compatible = "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - usbdrd_dwc3_0: dwc3@fe800000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; - dr_mode = "otg"; - }; - }; - - usbdrd3_1: usb@fe900000 { - compatible = "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - usbdrd_dwc3_1: dwc3@fe900000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; - dr_mode = "otg"; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file mode 100644 index 000000000..681086fa6 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SuperSpeed DWC3 USB SoC controller + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3399-dwc3 + + clocks: + items: + - description: + Controller reference clock, must to be 24 MHz + - description: + Controller suspend clock, must to be 24 MHz or 32 KHz + - description: + Master/Core clock, must to be >= 62.5 MHz for SS + operation and >= 30MHz for HS operation + - description: + Controller aclk_usb3_rksoc_axi_perf clock + - description: + Controller aclk_usb3 clock + - description: + Controller grf clock + + clock-names: + items: + - const: ref_clk + - const: suspend_clk + - const: bus_clk + - const: aclk_usb3_rksoc_axi_perf + - const: aclk_usb3 + - const: grf_clk + + resets: + maxItems: 1 + + reset-names: + const: usb3-otg + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^usb@[a-f0-9]+$": + type: object + + $ref: "snps,dwc3.yaml" + + description: + A child node must exist to represent the core DWC3 IP block. + The content of the node is defined in snps,dwc3.yaml. + + Phy documentation is provided in the following places. + + USB2.0 PHY + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml + + Type-C PHY + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt + + unevaluatedProperties: false + +additionalProperties: false + +required: + - compatible + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + #include + #include + usbdrd3_0: usb@fe800000 { + compatible = "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + usbdrd_dwc3_0: usb@fe800000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + }; + }; From patchwork Mon Feb 1 19:16:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 374445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C81D5C43381 for ; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id a11sm8243630ejc.64.2021.02.01.11.16.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Feb 2021 11:16:28 -0800 (PST) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] usb: dwc3: of-simple: add compatible for rk3328 Date: Mon, 1 Feb 2021 20:16:17 +0100 Message-Id: <20210201191619.32353-3-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210201191619.32353-1-jbx6244@gmail.com> References: <20210201191619.32353-1-jbx6244@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Cameron Nemo Add a compatible to be hooked into by the Rockchip rk3328 device tree. The rk3399 compatible cannot be reused because the rk3328 SoCs may require a specialized driver in the future and old device trees must remain compatible with newer kernels. Signed-off-by: Cameron Nemo Signed-off-by: Johan Jonker --- drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index e62ecd22b..93bc34328 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -171,6 +171,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { }; static const struct of_device_id of_dwc3_simple_match[] = { + { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "xlnx,zynqmp-dwc3" }, { .compatible = "cavium,octeon-7130-usb-uctl" }, From patchwork Mon Feb 1 19:16:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 374446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D23FC433DB for ; Mon, 1 Feb 2021 19:17:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 545A864E8D for ; Mon, 1 Feb 2021 19:17:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231643AbhBATRM (ORCPT ); Mon, 1 Feb 2021 14:17:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231360AbhBATRK (ORCPT ); Mon, 1 Feb 2021 14:17:10 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 828FFC0613D6; Mon, 1 Feb 2021 11:16:30 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id s3so6481987edi.7; Mon, 01 Feb 2021 11:16:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X2oJ/oS9W6B6NjUjWeyWWEJnoptgHKF+k6enHUja9os=; b=e2ZSe5L4DqRkHowO7yuhyPs3CMkfnLue4kyX/ln/Ia7m3ahZG//k55NGvjuHnUkxel iwTd8xIyzHn9aMLxJvRbjy9zk+Nyha3uq6Uw99qr0+nr5r+hTj4iDhmS825oSh5ix0Ys iLqa4kUp5I+PNPLCmtXO8XTu33h2XuIdJvr7FEiC51d5kQE6jx88JUGu3hF+cWiY5kHV sLqTnerAh2sU/LJXuAp4ysnFOD7k2si575b/RZ6ezCHjVj2PNk03qMOJ9ZoBYNMv2d2j Fw5P9Aj4iL2SC99cjaRxbs3UfGoSZa/RVXNsOUyUW6Wey50aIfFR5u+az3FS5ydrN1WO Yicw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X2oJ/oS9W6B6NjUjWeyWWEJnoptgHKF+k6enHUja9os=; b=WA1HRS3icn0EaWCasr/ARGIxsh0WvF0k6ZnWa6tmKiOhdYkLDk5KtGaTNcuyxqocW3 IZc/vm0HmC4zqszeFYWafS+rbU/OeusUy+x0FSWk3YLgdIiBfOxsq902CtWc/RR01M52 7pgXa2soavwKvtECQy3G6CnPh5Gwu3yul3MBvyfI+bt3KHltJ6PH72CPqLgIzjuAOHE6 tGQINWN1Ysk/H7itG6151xuNw68Gl0AGpUIrU+SGOe+emYgfLoftNK9hmhLZirdOxDzh X3VO92zsxsV2Mk71ZV5hoZeuE/Ykfo2HHiTNwrX8bJ0pKkT2sAJZXcZ/E70gYM4DxQG3 ahpg== X-Gm-Message-State: AOAM53062jULvCWeiRuMR3BYrk/hE2z4XCUzMbXe5G9CzSEXOZch6RhG aOGaxorsrOo6wg0Fz+9rOQZWkaOxuVY= X-Google-Smtp-Source: ABdhPJxhYrtE/Fe8Ro1UgIM2UBNTJv8wyaDn1S4w3Rujmub+U6t7MbTvxNQS9bY+5gv4bSHBFtXm9w== X-Received: by 2002:aa7:dace:: with SMTP id x14mr20615282eds.300.1612206989336; Mon, 01 Feb 2021 11:16:29 -0800 (PST) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id a11sm8243630ejc.64.2021.02.01.11.16.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Feb 2021 11:16:29 -0800 (PST) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] arm64: dts: rockchip: add rk3328 dwc3 usb controller node Date: Mon, 1 Feb 2021 20:16:18 +0100 Message-Id: <20210201191619.32353-4-jbx6244@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210201191619.32353-1-jbx6244@gmail.com> References: <20210201191619.32353-1-jbx6244@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Cameron Nemo RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner Signed-off-by: Cameron Nemo Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 17709faf6..2bb666d35 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -987,6 +987,33 @@ status = "disabled"; }; + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3"; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: usb@ff600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;