From patchwork Fri Mar 9 04:51:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 131074 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp556604lja; Thu, 8 Mar 2018 20:51:33 -0800 (PST) X-Google-Smtp-Source: AG47ELvUQwxJWtOcN75X2dvFoDap4VQGZ8jH2p1hjhPdx3YfCWJM0mRSyt2LKlp/xDftyZcIqsU/ X-Received: by 10.98.61.133 with SMTP id x5mr28833904pfj.181.1520571093675; Thu, 08 Mar 2018 20:51:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520571093; cv=none; d=google.com; s=arc-20160816; b=IJaYlRiGssl6Nnj66mshLAvFPcoCXChOtNR1vwbNFK/n0TDT5Svrbu2OeBdUwkQC2u 96lN5lMfSrIh2x57vQPOCP9ppi7b0gn2QzaC8zSnNrI933jdD3n5cFkUH9Nsi9TNm4KG 4wpio0fuDu5EvIA4GlFbTq+mKesxHQSDLsX+c5qdSKJtyIWHGe0X3Vw1hTYwCASumVUp FY+puTTI/bhtJXu27zcU2AppilymrvibBiTCKPON7SVQPhbZsT++qnRFZ55hxqquhn5x zftvB6/LPD4Y8O5Qk8DmGFq490LyXv14f8XuFgHwqvrskNEEPwlK0PKx3LNaGr9sCeSl ZOAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=IazoAMxzLcXIWds74Quk+MKncJeq3ExQvSvznil/MIK2Tag8236oyV9sAkdwTAUedX OE7kBq5rEiTNZut3vvOM3v3eXHjWg3mFdai4PxSFiJ/0OUglcM0a2JNz6RY6yXaS/7Yi 93gmdLYTCIgFd9R6Y/rEejMx0kgl3D/QLmaawvUaAfqghZiAxJl666MhZqD8vXWNfXz2 7cM3VuZlH1p9DM09CcRxx86duXtB9dFgSy3CIUu0ej2jpkTL1TVzyKG6by+zwVZ3aomk Ne4nVVTVWx703G8ChsGexf+3gJRCTcYmNZMA5KQuZNQlsQ5iJIYJgVxdWqqmqXqpMLyB yiDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=aFtGxSJ/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d13si183627pgn.366.2018.03.08.20.51.33; Thu, 08 Mar 2018 20:51:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=aFtGxSJ/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751284AbeCIEvb (ORCPT + 28 others); Thu, 8 Mar 2018 23:51:31 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:35996 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751218AbeCIEv1 (ORCPT ); Thu, 8 Mar 2018 23:51:27 -0500 Received: by mail-pl0-f68.google.com with SMTP id 61-v6so4664370plf.3; Thu, 08 Mar 2018 20:51:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=aFtGxSJ/OO8WiSK1nzzCNCQnjVd9yPIpFd+O2ik907L/8pKUfj55UfSq3n/KCEofDZ HIB11vStC2n4u8kf5HmZIVWOMea6kI5H3qdaPPDLn8HnfelGgqwhxew7WKkSaHxhFri1 lBLuY3dqdmoYt1A2cefpD/SmaPb+0ZCBigu+vMmUJN1fgGvmJZtFiX1UAdw1h22LvNSv ld+6AWjBh/O/gVCONXT26Q5pJ7LKtMtz6yOq9bmcF832FkkZcCHrkbATbsw6Fos8NfEj OTiI1KtG3lK/PKYqv+PDnRA64nAkrmbSQkqkv789vJlnkBWooANvLwvjTVkxJztbxi+5 RLoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=25viXcWoMvuckTuq//GGGxa0thjedEcpujxU6ZJVpI0=; b=WbJ7MzbfALDCkbxKGI4lyOw+o88G89p77/jJRnNrOZOskVY1n27AaM5RwImwKFfcxi q7cPShvCM+lC/7sTWlc6diTDojnVmrYxwa0tVUkwvN/OTjroPkWIU7B8iywrMZgRHEv2 WGiP3rVvqwDymeYOPHsuDvoak2SCO2ro8quz/VQOhpkKdIMfFachz38tXCBnABa769pK 2hKlQhA5Xs9AjtBrf7xSRaKcDu35oit39KiVhp8K9bFhOYrXxxKUwQ0g03atoXsC61n5 RfTLH5f2G+xDNP3FnG5mwaCzbBtVfEzdBeiO8h2aQmz73H9XZFZ0S1DTz8TIA68EsPHS gEmQ== X-Gm-Message-State: APf1xPCOQoKEmVbnCPNXW7e02dJtxwnnRtGeeV1tit4oUO7mVOa5EgW/ kJLHOTW69nBG4pUfpnh9P/8= X-Received: by 2002:a17:902:550f:: with SMTP id f15-v6mr25976030pli.50.1520571086975; Thu, 08 Mar 2018 20:51:26 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id h69sm491780pfe.97.2018.03.08.20.51.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 20:51:26 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 09 Mar 2018 15:21:18 +1030 From: Joel Stanley To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Mark Rutland , Marcus Folkesson Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon , Avi Fishman , Brendan Higgins Subject: [PATCH v3 1/2] dt-bindings: watchdog: Add Nuvoton NPCM description Date: Fri, 9 Mar 2018 15:21:06 +1030 Message-Id: <20180309045107.8515-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180309045107.8515-1-joel@jms.id.au> References: <20180309045107.8515-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These bindings describe the watchdog IP as used by the Nuvoton NPCM750 (Poleg) BMC SoC. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley --- V2: Add optional timeout property v3: - Fix address in example - Add Rob's reviewed-by --- .../bindings/watchdog/nuvoton,npcm-wdt.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt -- 2.15.1 diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt new file mode 100644 index 000000000000..6d593003c933 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt @@ -0,0 +1,28 @@ +Nuvoton NPCM Watchdog + +Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. +The watchdog supports a pre-timeout interrupt that fires 10ms before the +expiry. + +Required properties: +- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg). +- reg : Offset and length of the register set for the device. +- interrupts : Contain the timer interrupt with flags for + falling edge. + +Required clocking property, have to be one of: +- clocks : phandle of timer reference clock. +- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx + timer (usually 25000000). + +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + +Example: + +timer@f000801c { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xf000801c 0x4>; + clocks = <&clk NPCM7XX_CLK_TIMER>; +}; From patchwork Fri Mar 9 04:51:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 131075 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp556680lja; Thu, 8 Mar 2018 20:51:42 -0800 (PST) X-Google-Smtp-Source: AG47ELtwKFQEII6txJ/uaijkSSfkC83KKpEf2N2sArVY6h2Jqw8WQ9XYuCT+P/BlFEGE9ztBQf11 X-Received: by 2002:a17:902:aa8e:: with SMTP id d14-v6mr19373049plr.318.1520571102723; Thu, 08 Mar 2018 20:51:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520571102; cv=none; d=google.com; s=arc-20160816; b=Q9inOVD2iCHSQE8N+oP+8UhXmdAm+Zk0HogjyCbd2M68eQFV28vN97C9vHv2kMHvy1 skKRDZPXcYz2STeMCQUYq67ZJGRuFKAV/1kEDMuEmIVuOpwGVoebKTz3RL7ViakCAwNg k5v2vHEyIFzqd+VTXRqwgsNyr4d/Qu/En1OfudXRyxMb8SR0K+76IVJSyYCERjYCzBB8 nBcL4B+caZ9H/Akq8JAezzTt6dYnGYS+5Nf0Bc9YSBDxeZ2E1KZgvkdLo3LpBikPaHDs C26WqSx6NjfMQCvkmXzuQjUHvufxs9qsnkwPn7SSCzsZeKEACWy6O0lksvUVdHcyGR92 YAzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6dyU8vq7usECMhS5AWDDo5EqfeyF9oyWzH3ado+SoxQ=; b=HhVAvO2KQdQm+5x55dgncWPajtZCLnYvihBNXr3mw+dxJ1ao9ciyC4jxW55cXDlW83 g/HxDVwSwD+uAJoStQ7HTkS1ShJp3Dc2Z+6sDMl5qwYkfuL8QcXJRoYxXhQJXsGtcV5u o8VlrSecoP0ROqpuNkIjckpzS1FymUJ4nNS8qgoiTFLjfryua4uVyl49ZCgLvhlSOC/k oedy6U3UA2IEtZXI5qjdxtvCv8jmxNZosgsl/7IEGhAnmbl/Hsv0y4sMguhDH2SrcKzF 1NEgFmYiRzfCPlBnOqJL4YNp3oyTjYN94SaIJbWG0GycSw4N0K704LRYgkWCZdKYoF8I Sl8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=LKnLldO4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r62si210488pfe.400.2018.03.08.20.51.42; Thu, 08 Mar 2018 20:51:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=LKnLldO4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751333AbeCIEvj (ORCPT + 28 others); Thu, 8 Mar 2018 23:51:39 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:46869 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751193AbeCIEvg (ORCPT ); Thu, 8 Mar 2018 23:51:36 -0500 Received: by mail-pg0-f66.google.com with SMTP id r26so3146230pgv.13; Thu, 08 Mar 2018 20:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=6dyU8vq7usECMhS5AWDDo5EqfeyF9oyWzH3ado+SoxQ=; b=LKnLldO4vOXWnRLTjeerUO6ltqsGgfW6fgxLqbiL6w6hDHqnkczvOzpGPbokxFAoub lU9Z7o1ZrMG/ozMumFgDVofHcQNNKytDrtA2+dC+64XVehb8eB6fgiSku3Zqg1UBqhxS 8llX25HwUeis0b3nWwplCunHODmKtV2OE4u9Fq7lD7KYvQyNNKeAdKUKhHUdD19oNC5/ gTJvtXDSMsUmOM1pbQxt2FcnufAW55jv4Oz2Nq14Byp3RhD+VYItY2mfesnIlT5bkUDD RV8Ooiwyv8Lb/zD6JD/twnR+IflES8KS1lCgxMWq6Urfr96Kt7DTle1kESdL66HmMMri IRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=6dyU8vq7usECMhS5AWDDo5EqfeyF9oyWzH3ado+SoxQ=; b=i+lvX31Es85r00BU0f5cv7vkRcFUWt6MuQ49dYJi2Yf80dz+gaA8HLuhJTEz7Hgb6c hoeL2H81CW+SyYjP5FJUWOLj6PUCYo2kEdLQOJv2nvypWGHWo8W18cMdWSReqnWbj3Fa pGD4sJ4t093cdMETHSWzohunUWc8FOF+Uo4/d3mvPA6lvPLwpEvNvybaQlc4XMKg6+uW Gnv/euhA4MeWQg82OTDmQDrqMZ12RF/vHlA3crqeeOr0YbiilVBj7XFF1zhWkg3jdx4P UuZut5O+/32Ivh/nI3luS91rUZhDzlpjLV98Ceq0IuMzuJfe1fSnMfGCkhBjmcRjWpj+ aBrQ== X-Gm-Message-State: APf1xPB/1emwjA5xe3yMrXP1fNSBuHgYu8zWgqIahA+7e6Domh1L8cCv YbymeH3RhZ6s7ZMjsOPJ688= X-Received: by 10.99.103.196 with SMTP id b187mr23368508pgc.1.1520571095284; Thu, 08 Mar 2018 20:51:35 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id b123sm483227pfb.179.2018.03.08.20.51.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 20:51:34 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 09 Mar 2018 15:21:27 +1030 From: Joel Stanley To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Mark Rutland , Marcus Folkesson Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon , Avi Fishman , Brendan Higgins Subject: [PATCH v3 2/2] watchdog: Add Nuvoton NPCM watchdog driver Date: Fri, 9 Mar 2018 15:21:07 +1030 Message-Id: <20180309045107.8515-3-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180309045107.8515-1-joel@jms.id.au> References: <20180309045107.8515-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Nuvoton NPCM750 has a watchdog implemented as a single register inside the timer peripheral. This driver exposes that watchdog as a standard watchdog device with coarse timeout intervals, limited by the combination of prescaler and counter that is provided by the hardware. The calculation is taken from the Nuvoton vendor tree. The watchdog is left running if a bootloader had it going. The rate is the one specified in the device tree, or the default value (obtained from the datasheet). There is a pre-timeout IRQ that is wired up. This timeout always occurs 1024 clocks before the timeout. Signed-off-by: Joel Stanley --- v2: - Make MODULE_LICENCE gpl v2 to match SPDX - Remove unused struct device pointer - Remove unused setting of drvdata - Add linux/bitops.h - Sort includes - Remove unused fiq include - Update timeout with achieved value v3: - Calculate the time and register value seperately - Pass device tree value through set_timeout to ensure it can be represented by hardware --- drivers/watchdog/Kconfig | 11 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 254 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c -- 2.15.1 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index aff773bcebdb..0c1cc68894e6 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -513,6 +513,17 @@ config COH901327_WATCHDOG This watchdog is used to reset the system and thus cannot be compiled as a module. +config NPCM750_WATCHDOG + bool "NPCM750 watchdog" + depends on ARCH_NPCM || COMPILE_TEST + default y if ARCH_NPCM750 + select WATCHDOG_CORE + help + Say Y here to include Watchdog timer support for the + watchdog embedded into the NPCM750. + This watchdog is used to reset the system and thus cannot be + compiled as a module. + config TWL4030_WATCHDOG tristate "TWL4030 Watchdog" depends on TWL4030_CORE diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0474d38aa854..97a5afb5cad2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o +obj-$(CONFIG_NPCM7XX_WATCHDOG) += npcm_wdt.o obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 000000000000..723f80ebf100 --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright (c) 2018 IBM Corp. + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NPCM_WTCR 0x1C + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +/* + * Watchdog timeouts + * + * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400 + * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410 + * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800 + * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420 + * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810 + * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430 + * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820 + * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00 + * 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830 + * 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10 + * 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20 + * 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30 + */ + +struct npcm_wdt { + struct watchdog_device wdd; + void __iomem *reg; +}; + +static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) +{ + return container_of(wdd, struct npcm_wdt, wdd); +} + +static int npcm_wdt_ping(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + u32 val; + + val = readl(wdt->reg); + writel(val | NPCM_WTR, wdt->reg); + + return 0; +} + +static int npcm_wdt_start(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + u32 val; + + if (wdd->timeout < 2) + val = 0x800; + else if (wdd->timeout < 3) + val = 0x420; + else if (wdd->timeout < 6) + val = 0x810; + else if (wdd->timeout < 11) + val = 0x430; + else if (wdd->timeout < 22) + val = 0x820; + else if (wdd->timeout < 44) + val = 0xC00; + else if (wdd->timeout < 87) + val = 0x830; + else if (wdd->timeout < 173) + val = 0xC10; + else if (wdd->timeout < 688) + val = 0xC20; + else + val = 0xC30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + + writel(val, wdt->reg); + + return 0; +} + +static int npcm_wdt_stop(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + writel(0, wdt->reg); + + return 0; +} + + +static int npcm_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + if (timeout < 2) + wdd->timeout = 1; + else if (timeout < 3) + wdd->timeout = 2; + else if (timeout < 6) + wdd->timeout = 5; + else if (timeout < 11) + wdd->timeout = 10; + else if (timeout < 22) + wdd->timeout = 21; + else if (timeout < 44) + wdd->timeout = 43; + else if (timeout < 87) + wdd->timeout = 86; + else if (timeout < 173) + wdd->timeout = 172; + else if (timeout < 688) + wdd->timeout = 687; + else + wdd->timeout = 2750; + + if (watchdog_active(wdd)) + npcm_wdt_start(wdd); + + return 0; +} + +static irqreturn_t npcm_wdt_interrupt(int irq, void *data) +{ + struct npcm_wdt *wdt = data; + + watchdog_notify_pretimeout(&wdt->wdd); + + return IRQ_HANDLED; +} + +static int npcm_wdt_restart(struct watchdog_device *wdd, + unsigned long action, void *data) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); + udelay(1000); + + return 0; +} + +static bool npcm_is_running(struct watchdog_device *wdd) +{ + struct npcm_wdt *wdt = to_npcm_wdt(wdd); + + return readl(wdt->reg) & NPCM_WTE; +} + +static const struct watchdog_info npcm_wdt_info = { + .identity = KBUILD_MODNAME, + .options = WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE, +}; + +static const struct watchdog_ops npcm_wdt_ops = { + .owner = THIS_MODULE, + .start = npcm_wdt_start, + .stop = npcm_wdt_stop, + .ping = npcm_wdt_ping, + .set_timeout = npcm_wdt_set_timeout, + .restart = npcm_wdt_restart, +}; + +static int npcm_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct npcm_wdt *wdt; + struct resource *res; + int irq; + int ret; + + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + wdt->reg = devm_ioremap_resource(dev, res); + if (IS_ERR(wdt->reg)) + return PTR_ERR(wdt->reg); + + irq = platform_get_irq(pdev, 0); + if (!irq) + return -EINVAL; + + wdt->wdd.info = &npcm_wdt_info; + wdt->wdd.ops = &npcm_wdt_ops; + wdt->wdd.min_timeout = 1; + wdt->wdd.max_timeout = 2750; + wdt->wdd.parent = dev; + + wdt->wdd.timeout = 86; + watchdog_init_timeout(&wdt->wdd, 0, dev); + + /* Ensure timeout is able to be represented by the hardware */ + npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); + + if (npcm_is_running(&wdt->wdd)) { + /* Restart with the default or device-tree specified timeout */ + npcm_wdt_start(&wdt->wdd); + set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); + } + + ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, + "watchdog", wdt); + if (ret) + return ret; + + ret = devm_watchdog_register_device(dev, &wdt->wdd); + if (ret) { + dev_err(dev, "failed to register watchdog\n"); + return ret; + } + + dev_info(dev, "NPCM watchdog driver enabled\n"); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id npcm_wdt_match[] = { + {.compatible = "nuvoton,npcm750-wdt"}, + {}, +}; +MODULE_DEVICE_TABLE(of, npcm_wdt_match); +#endif + +static struct platform_driver npcm_wdt_driver = { + .probe = npcm_wdt_probe, + .driver = { + .name = "npcm-wdt", + .of_match_table = of_match_ptr(npcm_wdt_match), + }, +}; +module_platform_driver(npcm_wdt_driver); + +MODULE_AUTHOR("Joel Stanley"); +MODULE_DESCRIPTION("Watchdog driver for NPCM"); +MODULE_LICENSE("GPL v2");