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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id a29si16011854pfe.34.2018.03.08.07.21.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Mar 2018 07:21:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Vbcgmqa/; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D23B721ED1C48; Thu, 8 Mar 2018 07:15:33 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B8AD52256861E for ; Thu, 8 Mar 2018 07:15:31 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id 139so61582wmn.2 for ; Thu, 08 Mar 2018 07:21:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=FpoLnLJXPffLwam+oVPMd6+Jf9qWzBS9t8cn7G5yMVs=; b=Vbcgmqa/DFaI0bsRUUZ0XHZtHajPSJ1EX7AVTDG9ubpyceP0nVKhYq2unUA86DeL9Z b0q6bOEHzIxltquw87HSgN0o3dpgPrwnxfFxajvPE06dvHmxtRSU+6lU7r6bz1A7o1J4 nicf0a4MjBjoOe9833HXAH/J980mgLXBzZF9M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FpoLnLJXPffLwam+oVPMd6+Jf9qWzBS9t8cn7G5yMVs=; b=NAesQWCsNIN3plovrWq7iD+UGtvfUbNafSP3TUSM+SlS6qBZUbgphg6mqZPXaBuD9G zLh0DU6YF9qhMH1FjFPqZwqWcCYp9SMLJVGvwlMHJSD+U7x7tLhWySFc89+YmSthKyOC IMXNxYNnQhKqwxuN5hz6PTbHqBFDiI7Ht1E+Q8nE/u0YIvJ03vZH0jrXpSno/2IZqAjH mCnzwn3wp7wqe0p+90DXjUCyajs+Fm7A/E/KqmmTVSvI5GarAAJDMIhvzm8CiYMuVm7G ZA6qTHt9VSaGPFMYEDt9hmR5sdRL7ueOk7yXY2ODjcWNJQapa+YLcUYtqMUCBN3uL/dU 1ugQ== X-Gm-Message-State: AElRT7Gv3W+WyJYJZEdGkoZaAe6/IdnFcmnm75tpYRePeuUFHJZHKa0v RgNEuAK8sGKzvVfU3UmHLgBfDpGutAs= X-Received: by 10.28.220.130 with SMTP id t124mr15355515wmg.60.1520522505955; Thu, 08 Mar 2018 07:21:45 -0800 (PST) Received: from localhost.localdomain ([160.89.73.46]) by smtp.gmail.com with ESMTPSA id g127sm13529600wmf.46.2018.03.08.07.21.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Mar 2018 07:21:45 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 8 Mar 2018 15:21:41 +0000 Message-Id: <20180308152141.1028-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 Subject: [edk2] [PATCH edk2-platforms] Silicon/SynQuacer; add cache topology information to device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a DT description of the size and geometry of the various levels of caches that are present in the SynQuacer SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi | 80 ++++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) -- 2.15.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 2db7de3d5b96..2bea91f7f2c0 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2017, Linaro Limited. All rights reserved. + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials are licensed and made * available under the terms and conditions of the BSD License which @@ -575,3 +575,5 @@ #size-cells = <0>; }; }; + +#include "SynQuacerCaches.dtsi" diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi new file mode 100644 index 000000000000..1fbcd4aabfb6 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi @@ -0,0 +1,80 @@ +/** @file + * Copyright (c) 2018, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#define __L1(cpuref, l2ref) \ +cpuref { \ + i-cache-size = <0x8000>; \ + i-cache-line-size = <64>; \ + i-cache-sets = <256>; \ + d-cache-size = <0x8000>; \ + d-cache-line-size = <64>; \ + d-cache-sets = <128>; \ + l2-cache = ; \ +}; + +#define __L2(idx) \ +L2_##idx: l2-cache##idx { \ + cache-size = <0x40000>; \ + cache-line-size = <64>; \ + cache-sets = <256>; \ + cache-unified; \ + next-level-cache = <&L3>; \ +}; + +/ { + __L2(0) + __L2(1) + __L2(2) + __L2(3) + __L2(4) + __L2(5) + __L2(6) + __L2(7) + __L2(8) + __L2(9) + __L2(10) + __L2(11) + + L3: l3-cache { + cache-level = <3>; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-unified; + }; +}; + +__L1(&CPU0, &L2_0) +__L1(&CPU1, &L2_0) +__L1(&CPU2, &L2_1) +__L1(&CPU3, &L2_1) +__L1(&CPU4, &L2_2) +__L1(&CPU5, &L2_2) +__L1(&CPU6, &L2_3) +__L1(&CPU7, &L2_3) +__L1(&CPU8, &L2_4) +__L1(&CPU9, &L2_4) +__L1(&CPU10, &L2_5) +__L1(&CPU11, &L2_5) +__L1(&CPU12, &L2_6) +__L1(&CPU13, &L2_6) +__L1(&CPU14, &L2_7) +__L1(&CPU15, &L2_7) +__L1(&CPU16, &L2_8) +__L1(&CPU17, &L2_8) +__L1(&CPU18, &L2_9) +__L1(&CPU19, &L2_9) +__L1(&CPU20, &L2_10) +__L1(&CPU21, &L2_10) +__L1(&CPU22, &L2_11) +__L1(&CPU23, &L2_11)