From patchwork Fri Jan 29 18:27:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 373450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B26FDC43381 for ; Fri, 29 Jan 2021 18:29:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7BA0B64E0A for ; Fri, 29 Jan 2021 18:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbhA2S3U (ORCPT ); Fri, 29 Jan 2021 13:29:20 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:14383 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232555AbhA2S2h (ORCPT ); Fri, 29 Jan 2021 13:28:37 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 29 Jan 2021 10:27:57 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 29 Jan 2021 18:27:57 +0000 Received: from audio.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 29 Jan 2021 18:27:53 +0000 From: Sameer Pujar To: , , , CC: , , , , , , Sameer Pujar , Oder Chiou , Bard Liao Subject: [PATCH v2 1/9] ASoC: dt-bindings: rt5659: Update binding doc Date: Fri, 29 Jan 2021 23:57:38 +0530 Message-ID: <1611944866-29373-2-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611944866-29373-1-git-send-email-spujar@nvidia.com> References: <1611944866-29373-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611944877; bh=zegRvFdxvHED4R5W9t6yg7pqQzJOMHOZG7j3dYTBods=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=i4yH0KXWNRsm312/LZZRpSOdcsW8RktQXqjcZ38Jgc1FIHzH3dOx8EwF5V8LveRWz jT+vYmI6pI1kH/YBHw26NljetP+uxbuwK3iHgDSgsMAyZI4tfoz4BxWoArg2ELpHe+ 8LQph4dBG6gQnC1OBJL0gO3KZKJtj2ZwOZt0HHdJ0SZALP/uqrDK7qRv274omWhNRr YoN9henEr7HxxDw3rcq0e92tC9KnLHdv5oHXXvj/6JFUzlgmfn4FbqbLCXe88w/DhP nJcndz6rfPDpdqkM47I9kbYoOCCw4QwpnhT/zImvysAhMZCc5iyOwYvcDRvvGc3GcR caDPHF4wjOeNw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update following in rt5659.txt binding doc - Add JD source for Intel HDA header: Commit 041e74b71491 ("ASoC: rt5659: Add the support of Intel HDA Header") added driver support. Add missing info here. - sound-name-prefix: Used to prefix component widgets/kcontrols with given prefix. - ports: Helps to use the Codec with audio graph card Signed-off-by: Sameer Pujar Reported-by: Jon Hunter Cc: Oder Chiou Cc: Bard Liao --- Documentation/devicetree/bindings/sound/rt5659.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documentation/devicetree/bindings/sound/rt5659.txt index 56788f5..c473df5 100644 --- a/Documentation/devicetree/bindings/sound/rt5659.txt +++ b/Documentation/devicetree/bindings/sound/rt5659.txt @@ -37,10 +37,21 @@ Optional properties: - realtek,jd-src 0: No JD is used 1: using JD3 as JD source + 2: JD source for Intel HDA header - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin. +- sound-name-prefix: Please refer to name-prefix.txt + +- ports: A Codec may have a single or multiple I2S interfaces. These + interfaces on Codec side can be described under 'ports' or 'port'. + When the SoC or host device is connected to multiple interfaces of + the Codec, the connectivity can be described using 'ports' property. + If a single interface is used, then 'port' can be used. The usage + depends on the platform or board design. + Please refer to Documentation/devicetree/bindings/graph.txt + Pins on the device (for linking into audio routes) for RT5659/RT5658: * DMIC L1 From patchwork Fri Jan 29 18:27:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 373449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 753BBC433E0 for ; Fri, 29 Jan 2021 18:29:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 387A864E0A for ; Fri, 29 Jan 2021 18:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232627AbhA2S3W (ORCPT ); Fri, 29 Jan 2021 13:29:22 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:14403 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232702AbhA2S2u (ORCPT ); Fri, 29 Jan 2021 13:28:50 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 29 Jan 2021 10:28:09 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 29 Jan 2021 18:28:09 +0000 Received: from audio.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 29 Jan 2021 18:28:05 +0000 From: Sameer Pujar To: , , , CC: , , , , , , Sameer Pujar , Oder Chiou , Bard Liao Subject: [PATCH v2 4/9] ASoC: rt5659: Add Kconfig prompt Date: Fri, 29 Jan 2021 23:57:41 +0530 Message-ID: <1611944866-29373-5-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611944866-29373-1-git-send-email-spujar@nvidia.com> References: <1611944866-29373-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611944889; bh=F/BW7PY5izzMMJY0fLuFBv2E9jr38z5576WRI7J2fI4=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=nHr8zObCaCY6pG1yyuNQjsFsK4HACEtNZlOEi+9wFF+5YeulwGrvqumXM3dKSTu0y j8dKgOt7hm7jV0t2JGxZLGbW2fk4n2srPAlwHhuT081rRHLsafHByHjj7/C/wIYNYs yA2wbM5gUG1OgNMmNu+cVxW/cwgpef2vTQCYrRc7z3SOQpfQZ6uqevHEgDopyRmrch SwDmps+lFqyyJZvXoqm/wn4AsuYA+mf9E8Z6uui/pmRtSxlYzo3MI3IjYiNQi+Pr3F G8BYUSrzzt9omitztdGp+x9Npznp6J2S5rdRImZHJnVWIfIZKNtqqOGTp8lVHuEAi3 US7ukp7XQzn4A== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add tristate prompt to allow codec selection. Cc: Oder Chiou Cc: Bard Liao Signed-off-by: Sameer Pujar --- sound/soc/codecs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 9bf6bfd..df34b3b 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1162,7 +1162,7 @@ config SND_SOC_RT5651 depends on I2C config SND_SOC_RT5659 - tristate + tristate "Realtek RT5658/RT5659 Codec" depends on I2C config SND_SOC_RT5660 From patchwork Fri Jan 29 18:27:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 373448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8782C43381 for ; Fri, 29 Jan 2021 18:30:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 92D4564E08 for ; Fri, 29 Jan 2021 18:30:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230249AbhA2S3v (ORCPT ); Fri, 29 Jan 2021 13:29:51 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:17122 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232745AbhA2S2y (ORCPT ); Fri, 29 Jan 2021 13:28:54 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 29 Jan 2021 10:28:13 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 29 Jan 2021 18:28:13 +0000 Received: from audio.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 29 Jan 2021 18:28:09 +0000 From: Sameer Pujar To: , , , CC: , , , , , , Sameer Pujar , Oder Chiou , Bard Liao Subject: [PATCH v2 5/9] arm64: defconfig: Enable RT5659 Date: Fri, 29 Jan 2021 23:57:42 +0530 Message-ID: <1611944866-29373-6-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611944866-29373-1-git-send-email-spujar@nvidia.com> References: <1611944866-29373-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611944893; bh=rIqGC+2LJccA5Gf4qPtR3LQ7pbE2iJ1JvFV+aTtOY5I=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=X8C9y7QKmoQudGZPl+LtkpoI4df6JLK/pK03S4mxoAAd0gyDUw3QdksjbKiCL2jGQ k9/WORbQG1yaYDeAIgi/tgRhQFtc2wtu+9z49YVL8S3HkL5pUimGKJ+R2OVewgaa29 zgw58QKjW89xk2RjQcjkUgrGAC1RY1+CqHSqT3GiCgHyOGlvUGitKJgAZHf9b5jcac d28CUecUxhLkn5Ovf24q+TNMs5sZB4gywXF3QKCJJh9V9DESk9LjmglfGL/0NlhD2g wKEa39YltTmwxAUzCYTId7C/LzvBW+c3OFlZLsdVxtG0iM67MFKm5LO0Jy3exKvvhF lFDIIKvnnjMUA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable the RT5659 audio codec driver. Signed-off-by: Sameer Pujar Cc: Oder Chiou Cc: Bard Liao Acked-by: Jon Hunter --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ec377f7..ea279e8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -754,6 +754,7 @@ CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_WCD934X=m From patchwork Fri Jan 29 18:27:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 373446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AA4CC433DB for ; Fri, 29 Jan 2021 18:30:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA62F64E08 for ; Fri, 29 Jan 2021 18:30:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232795AbhA2Sas (ORCPT ); Fri, 29 Jan 2021 13:30:48 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:8344 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232735AbhA2SaA (ORCPT ); Fri, 29 Jan 2021 13:30:00 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 29 Jan 2021 10:28:21 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 29 Jan 2021 18:28:21 +0000 Received: from audio.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 29 Jan 2021 18:28:17 +0000 From: Sameer Pujar To: , , , CC: , , , , , , Sameer Pujar Subject: [PATCH v2 7/9] Revert "arm64: tegra: Disable the ACONNECT for Jetson TX2" Date: Fri, 29 Jan 2021 23:57:44 +0530 Message-ID: <1611944866-29373-8-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611944866-29373-1-git-send-email-spujar@nvidia.com> References: <1611944866-29373-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611944901; bh=I95udSMV/XUfuFEVmUIVdulMrVLxZ9bvj1yUdPIvxCs=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=OmoUYQrg/YSr24+iyc4mBwtIC21nefrGcNzKRO0gpVqfnOAJ6XhBMf3ktqB6jNYzj f/BWhzZtg34HHNo1lfpTYa1L1IhmVwveXsNmlm1zukZYy7AlZe9ORbjDX2On4WomHG /XUFfxOrlPanTylpJpYvhjA81e1dyJH48Sss4XlLwKV7AMKr45zhH8j35tI02mZpcr pNwgQdc+RGNED/mwKgG3DA7a+0wb8VxoCnOFNtAIbKUdt+6ManrAlSKSLPGLnHz+mG luQyuyf8mQMc2i70WiBDrHLQ+tXuOmoyNERz7CfEY5ErTVtHdskz74A2lD8SAcWck0 tEHf7wthl3/mg== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This reverts commit fb319496935b ("arm64: tegra: Disable the ACONNECT for Jetson TX2"). Signed-off-by: Sameer Pujar --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 6fd2e05..7e1723e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -10,6 +10,18 @@ model = "NVIDIA Jetson TX2 Developer Kit"; compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + aconnect { + status = "okay"; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + i2c@3160000 { power-monitor@42 { compatible = "ti,ina3221"; From patchwork Fri Jan 29 18:27:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 373447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7BE7C433E9 for ; Fri, 29 Jan 2021 18:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 891C864E0F for ; Fri, 29 Jan 2021 18:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232343AbhA2SaM (ORCPT ); Fri, 29 Jan 2021 13:30:12 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:17141 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232208AbhA2S3J (ORCPT ); Fri, 29 Jan 2021 13:29:09 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 29 Jan 2021 10:28:25 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 29 Jan 2021 18:28:25 +0000 Received: from audio.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 29 Jan 2021 18:28:22 +0000 From: Sameer Pujar To: , , , CC: , , , , , , Sameer Pujar Subject: [PATCH v2 8/9] arm64: tegra: Audio graph sound card for Jetson TX2 Date: Fri, 29 Jan 2021 23:57:45 +0530 Message-ID: <1611944866-29373-9-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611944866-29373-1-git-send-email-spujar@nvidia.com> References: <1611944866-29373-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611944905; bh=IQ4kJdcWP8n18OsPAUglK+0qFMf2cRaake0iyMmYPRg=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=OXj4oTObHccQYfO+erXHUUznxFiJO0c5b2Oci/uANBlUXUi+acS5YPx7jimfQ84VD D1x9wYAXG4QLCyjgbQi5qvUSilamFjmMoXX7sFAWB3e88Uc49+q49qsSvJX6pmvwSq i7aiKI3zYqg3tr9eS00UtdntwaAxg1vSzyFnQUmTJb6phaKWAYPe/QOdJ/JerZtK7c 3YP4+QxLXFLIfcW5ynCgd+ApdSXGEDqsfs5j2+2o7FZkVIBoZLuiw+2UtH159jyGQZ nIV/9EC318oPtBkWxbvMe93QcPBoqSbF2fF9h8wMpcz11S6sgJjOv56vCooZvbbQlZ m85ToCGm9uDGw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable support for audio-graph based sound card on Jetson TX2. Based on the board design following I/O modules are enabled. * All I2S instances (I2S1 ... I2S6) * All DSPK instances (DSPK1, DSPK2) * DMIC1, DMIC2 and DMIC3 Signed-off-by: Sameer Pujar --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 597 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 22 + 2 files changed, 619 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 7e1723e..5e59584 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -20,6 +20,580 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + port@1 { + reg = <0x1>; + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + port@2 { + reg = <0x2>; + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + port@3 { + reg = <0x3>; + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + port@4 { + reg = <0x4>; + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + port@5 { + reg = <0x5>; + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + port@6 { + reg = <0x6>; + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + port@7 { + reg = <0x7>; + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + port@8 { + reg = <0x8>; + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + port@9 { + reg = <0x9>; + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + port@a { + reg = <0xa>; + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + port@b { + reg = <0xb>; + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + port@c { + reg = <0xc>; + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + port@d { + reg = <0xd>; + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + port@e { + reg = <0xe>; + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + port@f { + reg = <0xf>; + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + port@10 { + reg = <0x10>; + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + port@11 { + reg = <0x11>; + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + port@12 { + reg = <0x12>; + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + port@13 { + reg = <0x13>; + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + xbar_i2s1_port: port@14 { + reg = <0x14>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + xbar_i2s2_port: port@15 { + reg = <0x15>; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + xbar_i2s3_port: port@16 { + reg = <0x16>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@17 { + reg = <0x17>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_i2s5_port: port@18 { + reg = <0x18>; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + xbar_i2s6_port: port@19 { + reg = <0x19>; + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; + }; + }; + xbar_dmic1_port: port@1a { + reg = <0x1a>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@1b { + reg = <0x1b>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + xbar_dmic3_port: port@1c { + reg = <0x1c>; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + xbar_dspk1_port: port@1e { + reg = <0x1e>; + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + xbar_dspk2_port: port@1f { + reg = <0x1f>; + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + admaif1_port: port@1 { + reg = <0x1>; + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + admaif2_port: port@2 { + reg = <0x2>; + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + admaif3_port: port@3 { + reg = <0x3>; + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + admaif4_port: port@4 { + reg = <0x4>; + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + admaif5_port: port@5 { + reg = <0x5>; + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + admaif6_port: port@6 { + reg = <0x6>; + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + admaif7_port: port@7 { + reg = <0x7>; + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + admaif8_port: port@8 { + reg = <0x8>; + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + admaif9_port: port@9 { + reg = <0x9>; + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + admaif10_port: port@a { + reg = <0xa>; + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + admaif11_port: port@b { + reg = <0xb>; + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + admaif12_port: port@c { + reg = <0xc>; + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + admaif13_port: port@d { + reg = <0xd>; + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + admaif14_port: port@e { + reg = <0xe>; + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + admaif15_port: port@f { + reg = <0xf>; + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + admaif16_port: port@10 { + reg = <0x10>; + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + admaif17_port: port@11 { + reg = <0x11>; + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + admaif18_port: port@12 { + reg = <0x12>; + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + admaif19_port: port@13 { + reg = <0x13>; + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + i2s1_port: port@1 { + reg = <1>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + i2s2_port: port@1 { + reg = <1>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + i2s3_port: port@1 { + reg = <1>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + i2s4_port: port@1 { + reg = <1>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + i2s5_port: port@1 { + reg = <1>; + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; + }; + i2s6_port: port@1 { + reg = <1>; + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + dmic1_port: port@1 { + reg = <1>; + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + dmic2_port: port@1 { + reg = <1>; + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + dmic3_port: port@1 { + reg = <1>; + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + dspk1_port: port@1 { + reg = <1>; + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + dspk2_port: port@1 { + reg = <1>; + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + }; }; i2c@3160000 { @@ -114,6 +688,29 @@ status = "okay"; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* FE */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, + <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>, + <&xbar_dspk1_port>, <&xbar_dspk2_port>, + /* I/O */ + <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, + <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, + <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; + + label = "jetson-tx2-ape"; + }; + padctl@3520000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58c5196..0ba791f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -680,6 +680,28 @@ status = "disabled"; }; + sound { + status = "disabled"; + + clocks = <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>, + <&bpmp TEGRA186_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA186_CLK_PLLA>, + <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + /* + * PLLA supports dynamic ramp. Below initial rate is chosen + * for this to work and oscillate between base rates required + * for 8x and 11.025x sample rate streams. + */ + assigned-clock-rates = <258000000>; + + iommus = <&smmu TEGRA186_SID_APE>; + }; + padctl: padctl@3520000 { compatible = "nvidia,tegra186-xusb-padctl"; reg = <0x0 0x03520000 0x0 0x1000>,