From patchwork Wed Mar 7 14:22:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 130911 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp5241988lja; Wed, 7 Mar 2018 06:22:47 -0800 (PST) X-Google-Smtp-Source: AG47ELvvHbkw1daEgPleiF17GrIP/DLoX8bKsmcDtxuP9f9X3XVlQ6u/t01vAE6HTZItDKiE+iQt X-Received: by 10.223.209.205 with SMTP id m13mr17882920wri.99.1520432567495; Wed, 07 Mar 2018 06:22:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520432567; cv=none; d=google.com; s=arc-20160816; b=cLGC5HS7LBaLed2nUmXLysNKcWe4iD9bpSyFRLwLcEOQ2UIFP0M7Os/I6qWqlzYffS OF+W5/+q5rVyUd+QoVnAh35iua406Kb9EfR7RSSyUb9uAFLx925y+9SNOX7pgjAbxi3d 0bPqxfxzyVeDXufq8g9dHmvV/u9d61M50Qn48FSoOUR+F8k2pKY/PFCPSLhJzlETGxuz BMpKyyLPdoTrwv0iIH8N1Dt/acB88eIfb+ETnf92dgUdBRM0PV3ScUc1c42xnppAgQYJ MHEkZeo+njc/zce3Gz0T29Son9Wij255I3KC55N71e6BZ1JCMFqqjMu0RjlZCH0Z4o8D nczA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:date:message-id:in-reply-to:to:from :dkim-signature:delivered-to:arc-authentication-results; bh=WsvcqwMgGCdDWi6u2SxoIyRtMn+XfvxwTpVhIu7qokY=; b=GYXtNyaBk0NE5LaXgltySTQJ2BF6cO5woMwtGuT46RoxQJhVy+897+wnTudnrWWiIU I24ypWin/D5dbkGklUsY/BfWiZONNhfgCjku7/sOH6uPvZQULQtLB1wdiOY4TDvunLTM J5sSaoerRedqCunQJsTC336y0TIJl6yf8Bs2fyTlDnLqWnVG+5xgA3vTU0Ka/jFA5pBl GE2KPtmnPw9S2dJriXZugZ7L2RYYfRJv2TyrGqXQbrNaBjYTCMU+a73WuA1b63HqRfna 83nWFzZ5ePQdx20NDJ+cAzBbS3IUEEYRo515lA9VvzrbZrJBua33ajNhhMcubmv4Unjm YqWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=earQrB+B; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id 28si4434169wrt.122.2018.03.07.06.22.47; Wed, 07 Mar 2018 06:22:47 -0800 (PST) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=earQrB+B; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id A97D02673F3; Wed, 7 Mar 2018 15:22:29 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id A7C3226742D; Wed, 7 Mar 2018 15:22:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id CD5D52673A4 for ; Wed, 7 Mar 2018 15:22:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=3LStWGG2EY84cVKYKl1GRlOmyUEirj4M+WoEW0+ZWiw=; b=earQrB+BRPQ7 knRsGiONIHC151RC+kyruT6k3gFax/NwbzolHboTeuT3fTP/Qe2MN0umgEWTGiy9JpGu7t93oiol3 d97Uqded+skcOyPJ2GZAsytBsbM0d9eSAs6/DvCtzAU6mXmFwI/vRI4p2MO1Ub6QGocJdfdFI/J1M lTwLE=; Received: from debutante.sirena.org.uk ([2001:470:1f1d:6b5::3] helo=debutante) by heliosphere.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1etZxS-0000Dr-RK; Wed, 07 Mar 2018 14:22:18 +0000 Received: from broonie by debutante with local (Exim 4.90_1) (envelope-from ) id 1etZxS-0002mx-Ci; Wed, 07 Mar 2018 14:22:18 +0000 From: Mark Brown To: Hans de Goede In-Reply-To: <20180225104713.4745-26-hdegoede@redhat.com> Message-Id: Date: Wed, 07 Mar 2018 14:22:18 +0000 Cc: Oder Chiou , alsa-devel@alsa-project.org, Pierre-Louis Bossart , Takashi Iwai , Mark Brown , Carlo Caione , Bard Liao Subject: [alsa-devel] Applied "ASoC: Intel: bytcr_rt5651: Configure PLL1 before using it" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: Intel: bytcr_rt5651: Configure PLL1 before using it has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From aeec6cc0821573920d559f7d6297ea5dd3fbbd17 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 4 Mar 2018 15:36:03 +0100 Subject: [PATCH] ASoC: Intel: bytcr_rt5651: Configure PLL1 before using it When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL registers have not been setup yet and we effectively have an invalid clock configuration until byt_rt5651_aif1_hw_params() gets called. Add a new byt_rt5651_prepare_and_enable_pll1() helper and use that from both platform_clock_control() and byt_rt5651_aif1_hw_params() to fix this. Tested-by: Carlo Caione Signed-off-by: Hans de Goede Signed-off-by: Mark Brown --- sound/soc/intel/boards/bytcr_rt5651.c | 73 +++++++++++++++++------------------ 1 file changed, 35 insertions(+), 38 deletions(-) -- 2.16.2 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/intel/boards/bytcr_rt5651.c b/sound/soc/intel/boards/bytcr_rt5651.c index 91b5841af622..af30c730f432 100644 --- a/sound/soc/intel/boards/bytcr_rt5651.c +++ b/sound/soc/intel/boards/bytcr_rt5651.c @@ -111,6 +111,38 @@ static void log_quirks(struct device *dev) #define BYT_CODEC_DAI1 "rt5651-aif1" +static int byt_rt5651_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, + int rate, int bclk_ratio) +{ + int clk_id, clk_freq, ret; + + /* Configure the PLL before selecting it */ + if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) { + clk_id = RT5651_PLL1_S_BCLK1, + clk_freq = rate * bclk_ratio; + } else { + clk_id = RT5651_PLL1_S_MCLK; + if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ) + clk_freq = 25000000; + else + clk_freq = 19200000; + } + ret = snd_soc_dai_set_pll(codec_dai, 0, clk_id, clk_freq, rate * 512); + if (ret < 0) { + dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, + rate * 512, SND_SOC_CLOCK_IN); + if (ret < 0) { + dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret); + return ret; + } + + return 0; +} + static int platform_clock_control(struct snd_soc_dapm_widget *w, struct snd_kcontrol *k, int event) { @@ -136,9 +168,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, return ret; } } - ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, - 48000 * 512, - SND_SOC_CLOCK_IN); + ret = byt_rt5651_prepare_and_enable_pll1(codec_dai, 48000, 50); } else { /* * Set codec clock source to internal clock before @@ -252,44 +282,11 @@ static int byt_rt5651_aif1_hw_params(struct snd_pcm_substream *substream, { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; - int ret; + int rate = params_rate(params); snd_soc_dai_set_bclk_ratio(codec_dai, 50); - ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, - params_rate(params) * 512, - SND_SOC_CLOCK_IN); - if (ret < 0) { - dev_err(rtd->dev, "can't set codec clock %d\n", ret); - return ret; - } - - if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) { - /* 2x25 bit slots on SSP2 */ - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_BCLK1, - params_rate(params) * 50, - params_rate(params) * 512); - } else { - if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ) { - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_MCLK, - 25000000, - params_rate(params) * 512); - } else { - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_MCLK, - 19200000, - params_rate(params) * 512); - } - } - - if (ret < 0) { - dev_err(rtd->dev, "can't set codec pll: %d\n", ret); - return ret; - } - - return 0; + return byt_rt5651_prepare_and_enable_pll1(codec_dai, rate, 50); } static int byt_rt5651_quirk_cb(const struct dmi_system_id *id)