From patchwork Tue Mar 6 14:33:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 130810 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp4009521lja; Tue, 6 Mar 2018 06:33:32 -0800 (PST) X-Google-Smtp-Source: AG47ELv4oXQWjXS8y/9QFjVgwJxLJ3FTQB6VXzYBQhHcscGTtLAIeFzWyF0CVPZ0wdNTbw/GRf9O X-Received: by 2002:a17:902:6b48:: with SMTP id g8-v6mr16942672plt.151.1520346812690; Tue, 06 Mar 2018 06:33:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520346812; cv=none; d=google.com; s=arc-20160816; b=P1pITudUYxfEZf7eziAx4ZXUNdo7MNso+FFDENy6afcNmEaCfuwQVuIld+xW9NH0mu vfo6+YNJF7ZD/n5KdiIISdUF++Wciy8G7LQReBvbmOAeAXMyZdLjA713M5vFpmYPKa+K eH7bIoTDu+41NvtFH0xTBLSlO76b/ES7GmSzMOpMOlHBdQ2iL7d+OGJSa9rfN/c1XqZ4 Kr8Xhi3PZNajszPdEFyMA58UqSoOLXFkWWU5+FzIUAQUT5qXRMtBsn0LLJCOlv8u+oMt cRpaFzeEZrg5D5UFVPCTKPfagDoHENxcGk0jNkRtA8w44UIuYsd/9N78GBy+I426aMNj PwwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=d1Qu7NWAdN1mnTy5dp0rKIxD2DDY+M97FyjlWTG7S8E=; b=UqJ0STysWjJbTmXUBVSq6TGzbSyY3W/apx8iGfjMa5xXrOBV0nLCh+2O6457wWaBeH F15PfSlZemT6KdSozeiMTUzsWuMeIhVgl712LA4fEUa8jRyZnciBC1L1M0OioeXZCMNV d8Qb7pRHmBD+Cgjqn5L6rlnMyZPwQAZQ3KdpYDiE6NbmjO/eDJGCvv/qJzk7zeOSENZm SaGthZvSUKK4twIQDCLwiudLFpgkTqvq4fmzOWYdT3GyT/RkaeCHi8vhsI6E79/A/eoW WDHgXmgh3wO61fs5vK+4/a0UXighsx99XdHly9F+tOYcmFd0TlFTFjf6Dwgn0Wam7Nc4 PKGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=RVWtQIH+; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 6 Mar 2018 14:33:24 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20180306143323eucas1p1d420abb34b827a3128503859e0c21727~ZW1zG2V7K2359223592eucas1p18; Tue, 6 Mar 2018 14:33:23 +0000 (GMT) X-AuditID: cbfec7f2-1dbff70000011644-30-5a9ea6b38b4d Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 91.0F.04178.3B6AE9A5; Tue, 6 Mar 2018 14:33:23 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P5600MGHB3ETD00@eusync1.samsung.com>; Tue, 06 Mar 2018 14:33:23 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 1/6] soc: samsung: pm_domains: Add blacklisting clock handling Date: Tue, 06 Mar 2018 15:33:07 +0100 Message-id: <20180306143312.21035-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180306143312.21035-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsWy7djPc7pbls2LMphRbrFxxnpWi+tfnrNa TLo/gcXi/PkN7BYfe+6xWsw4v4/JYu2Ru+wWh9+0szpweGxa1cnm0bdlFaPH501yAcxRXDYp qTmZZalF+nYJXBkzmx4wFjRwV/y49Jy5gXESZxcjJ4eEgInEpr69TF2MXBxCAisYJdpPdUE5 nxkllq7azQZTNXHufKjEMkaJnTeOM4IkhAQamCRmPI0HsdkEDCW63naBNYgIOEh8/vSaEaSB WaCNSeLsgf1MIAlhgWCJnz/nsoDYLAKqEjc3z2EFsXkFbCXu7jnPCrFNXmLx951ggzgF7CTu XJrJAjJIQuAvq8S8xeuYIYpcJHZt/scIYQtLvDq+hR3ClpHo7DjIBGHXS/R9P8IE0dzDKLG3 ZSpUwlri8PGLYNuYBfgkJm2bDjSUAyjOK9HRJgRR4iEx+fNzqLCjRMv7TIiHJzJK/J4SOoFR agEjwypG8dTS4tz01GLDvNRyveLE3OLSvHS95PzcTYzAWDz97/inHYxfLyUdYhTgYFTi4eXw nhslxJpYVlyZe4hRgoNZSYQ3Qn9elBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeOI26KCGB9MSS 1OzU1ILUIpgsEwenVANj45a17yvMfWQMn6T7vLDfWnbhooVS/Qq7+6uflnyr3l2RsyNT4We8 xvIzp/4yehU3vFihq7p1p5HnLJGcreeTnVlmzvEuPZ+7ftHt548W9l+0uHBynXnU/cZ5KU1W qYV3N5hP35MqUPXLPtxZ8FNJaEab515mFZUVRzoerz2k3HpvhxeDwFZHJZbijERDLeai4kQA jZ1Wx8ECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmluLIzCtJLcpLzFFi42I5/e/4Zd3Ny+ZFGXSf5rbYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MmU0PGAsauCt+XHrO3MA4ibOLkZNDQsBEYuLc+UxdjFwcQgJLGCXWbtkC 5TQxSUzquMUIUsUmYCjR9baLDcQWEXCQ+PzpNSNIEbNAB5PEnr0PwRLCAsESP3/OZQGxWQRU JW5unsMKYvMK2Erc3XOeFWKdvMTi7zvB6jkF7CTuXJoJVi8EVHN5wnfGCYw8CxgZVjGKpJYW 56bnFhvqFSfmFpfmpesl5+duYgQGzbZjPzfvYLy0MfgQowAHoxIP7waPuVFCrIllxZW5hxgl OJiVRHgj9OdFCfGmJFZWpRblxxeV5qQWH2KU5mBREuc9b1AZJSSQnliSmp2aWpBaBJNl4uCU amAsDJ1y4tvzVwa5xjZTJvOf4Pr8oqfpoMh6t9U2FzffXlzE5inw8qH8ov+FDD23Lte0Lcz6 7a14WO64RfSDUO3ItD9rzfcEf1v8UrkiuVXR0uzpzC1HfDIWyaUyTF4T2jrndv/7Hv2CBn8r htuRaTqKv1/yFz7UsWBVPPpXRTnboPc5n2xnkqYSS3FGoqEWc1FxIgAwQV4zFgIAAA== X-CMS-MailID: 20180306143323eucas1p1d420abb34b827a3128503859e0c21727 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180306143323eucas1p1d420abb34b827a3128503859e0c21727 X-RootMTR: 20180306143323eucas1p1d420abb34b827a3128503859e0c21727 References: <20180306143312.21035-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Handling of clock reparenting will be move to clock controller driver, so add possibility to blacklist clock handling on systems, where the clock controller already does all needed operations. This is needed to avoid potential deadlock on clock reparenting during power domain on/off procedure. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- drivers/soc/samsung/pm_domains.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index b6a436594a19..cef30bdf19b1 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -147,6 +147,9 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } +static const char *soc_force_no_clk[] = { +}; + static __init int exynos4_pm_init_power_domain(void) { struct device_node *np; @@ -183,6 +186,11 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_on = exynos_pd_power_on; pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; + for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++) + if (of_find_compatible_node(NULL, NULL, + soc_force_no_clk[i])) + goto no_clk; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { char clk_name[8]; From patchwork Tue Mar 6 14:33:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 130811 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp4009536lja; Tue, 6 Mar 2018 06:33:33 -0800 (PST) X-Google-Smtp-Source: AG47ELuU0MVQm2UGgkikS5zmjhVGA0UxYNZNbntf9TE3/lXWk8+6MfpxMAUVqAJNl1Qy9KmTzeI5 X-Received: by 10.99.186.73 with SMTP id l9mr14975508pgu.83.1520346813264; Tue, 06 Mar 2018 06:33:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520346813; cv=none; d=google.com; s=arc-20160816; b=h7zzg5dVjK2XLyfAxqs0HR/9M2U/WXLbCJSYUzJ2TQtusVSVZVHE8DVICebeNdMg3R qUxuYQgdwslvZKuU7XU6D1TDaoz37TuyM0+NM9x+SiUAg6pMZLa+SOe5oLkxdOo84Kko OJqlDWocxkhj1R4NzGRnflMWiOAgcYvLjnRuqzUvTo4wWbIbORFCQ30NQb5EE9J7cfSQ SXQ57P/PPyg2ePyar8gZr87T3FXpdTdeJMcSvOKkiH+lsn1HRQnBsVjVSeXqaQ06C8IQ FrY2NsiK5+ksfxF664Gaj5nxM1GotJerUigRPJJwP4gGRfR4TvynieQpF+JQnnDRlhEv e+dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=WkFSfgDP1SPXLtPknA/deeATRdeZAzUEtR7VLaGBbWY=; b=Mdnp0ACDrnC3Mq+JbeAds6N4T7BhlUah3GEJ7OHRhG+ZY5XXIZGyBvUF2l7P9uEXSM 8Cp/PpKM6u7j+ro85hrPuq7cEjwqi7Pd4axs/H2X3ASgAV8eJ7ue/LNEgimdj3QLAYHU PYP/gbyItMJx2o+grGF7rtLGwzOjRmC0XrcdhwirlToaZhFg1GsMmyUBRn7sgIu4lOFl Fg2kmAYREQyVCHCAhFNZDQolOtJDDadhib+F7036e97UpGDNzTujrJYaNKaPvAzeqGyj 2sRQG/fs8GFW67KxBKYG+T+Zj18JbEbbEl3rxR7qaqshcAYzG4SDLhmrk3tvxOwvNeFx 67ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=mBJLeSg9; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Handling integration of clock controller and power domain can be done using runtime PM feature of CCF framework. This however needs a separate struct device for each power domain. This patch adds such separate driver for a group of such clocks, which can be instantiated more than once, each time for a different power domain. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5-subcmu.c | 186 +++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5-subcmu.h | 26 +++++ 2 files changed, 212 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5-subcmu.c create mode 100644 drivers/clk/samsung/clk-exynos5-subcmu.h -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c new file mode 100644 index 000000000000..ac3983c8adf2 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 Samsung Electronics Co., Ltd. +// Author: Marek Szyprowski +// Common Clock Framework support for Exynos5 power-domain dependent clocks + +#include +#include +#include +#include + +#include "clk.h" +#include "clk-exynos5-subcmu.h" + +static struct samsung_clk_provider *ctx; +static const struct exynos5_subcmu_info *cmu; +static int nr_cmus; + +static void exynos5_subcmu_clk_save(void __iomem *base, + struct exynos5_subcmu_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) { + rd->save = readl(base + rd->offset); + writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); + rd->save &= rd->mask; + } +}; + +static void exynos5_subcmu_clk_restore(void __iomem *base, + struct exynos5_subcmu_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + writel((readl(base + rd->offset) & ~rd->mask) | rd->save, + base + rd->offset); +} + +static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx, + const struct samsung_gate_clock *list, int nr_clk) +{ + while (nr_clk--) + samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id); +} + +/* + * Pass the needed clock provider context and register sub-CMU clocks + * + * NOTE: This function has to be called from the main, OF_CLK_DECLARE- + * initialized clock provider driver. This happens very early during boot + * process. Then this driver, during core_initcall registers two platform + * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE + * driver and second, for handling its per-domain child-devices. Those + * platform drivers are bound to their devices a bit later in arch_initcall, + * when OF-core populates all device-tree nodes. + */ +void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus, + const struct exynos5_subcmu_info *_cmu) +{ + ctx = _ctx; + cmu = _cmu; + nr_cmus = _nr_cmus; + + for (; _nr_cmus--; _cmu++) { + exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks, + _cmu->nr_gate_clks); + exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs, + _cmu->nr_suspend_regs); + } +} + +static int __maybe_unused exynos5_subcmu_suspend(struct device *dev) +{ + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static int __maybe_unused exynos5_subcmu_resume(struct device *dev) +{ + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static int __init exynos5_subcmu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos5_subcmu_info *info = dev_get_drvdata(dev); + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + pm_runtime_get(dev); + + ctx->dev = dev; + samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks); + samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks); + ctx->dev = NULL; + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops exynos5_subcmu_pm_ops = { + SET_RUNTIME_PM_OPS(exynos5_subcmu_suspend, + exynos5_subcmu_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver exynos5_subcmu_driver __refdata = { + .driver = { + .name = "exynos5-subcmu", + .suppress_bind_attrs = true, + .pm = &exynos5_subcmu_pm_ops, + }, + .probe = exynos5_subcmu_probe, +}; + +static int __init exynos5_clk_register_subcmu(struct device *parent, + const struct exynos5_subcmu_info *info, + struct device_node *pd_node) +{ + struct of_phandle_args genpdspec = { .np = pd_node }; + struct platform_device *pdev; + + pdev = platform_device_alloc(info->pd_name, -1); + pdev->dev.parent = parent; + pdev->driver_override = "exynos5-subcmu"; + platform_set_drvdata(pdev, (void *)info); + of_genpd_add_device(&genpdspec, &pdev->dev); + platform_device_add(pdev); + + return 0; +} + +static int __init exynos5_clk_probe(struct platform_device *pdev) +{ + struct device_node *np; + const char *name; + int i; + + for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { + if (of_property_read_string(np, "label", &name) < 0) + continue; + for (i = 0; i < nr_cmus; i++) + if (strcmp(cmu[i].pd_name, name) == 0) + exynos5_clk_register_subcmu(&pdev->dev, + &cmu[i], np); + } + return 0; +} + +static const struct of_device_id exynos5_clk_of_match[] = { + { }, +}; + +static struct platform_driver exynos5_clk_driver __refdata = { + .driver = { + .name = "exynos5-clock", + .of_match_table = exynos5_clk_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos5_clk_probe, +}; + +static int __init exynos5_clk_drv_init(void) +{ + platform_driver_register(&exynos5_clk_driver); + platform_driver_register(&exynos5_subcmu_driver); + return 0; +} +core_initcall(exynos5_clk_drv_init); diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.h b/drivers/clk/samsung/clk-exynos5-subcmu.h new file mode 100644 index 000000000000..755ee8aaa3de --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5-subcmu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __CLK_EXYNOS5_SUBCMU_H +#define __CLK_EXYNOS5_SUBCMU_H + +struct exynos5_subcmu_reg_dump { + u32 offset; + u32 value; + u32 mask; + u32 save; +}; + +struct exynos5_subcmu_info { + const struct samsung_div_clock *div_clks; + unsigned int nr_div_clks; + const struct samsung_gate_clock *gate_clks; + unsigned int nr_gate_clks; + struct exynos5_subcmu_reg_dump *suspend_regs; + unsigned int nr_suspend_regs; + const char *pd_name; +}; + +void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus, + const struct exynos5_subcmu_info *cmu); + +#endif From patchwork Tue Mar 6 14:33:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 130812 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp4009571lja; Tue, 6 Mar 2018 06:33:35 -0800 (PST) X-Google-Smtp-Source: AG47ELvcBNDsH+wMpZyX66BGdMdX0aIja+o1Hhmbub1YKdZDx27o6rvIaPtIL0wl8lt2MoJ4tHO2 X-Received: by 10.99.185.84 with SMTP id v20mr15597340pgo.112.1520346814874; Tue, 06 Mar 2018 06:33:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520346814; cv=none; d=google.com; s=arc-20160816; b=rP+GCaR4ihWtdH/btHQdqnM2ft+es+PzmqSCfiWtkGdhRmn5QpE6asDrKDdJOp3DCi snupJApyD701VPErTqTBR9GUXbe4x/KR7KxXNv9evQHaLY09pZzTAFszZexlWEP3Ikre cguyVEUVnDpwNKoM6SQDADHRxc7HCAH+4d+R/PqTqUVOIoZ9mTegNZdBmDdgfNnKdFT2 W0tSIff3vo9L8id6+/69o2+7YKfcvauKiAA7rr043wdggCJLNTSZ5GV/kSybZdoZ+ynK WUF3hmGPObnUJtJenw6/gWM1ayiZ/xanzkdRt/vCQrjw4iGwH+e1/jA+A9KVHJEi2fc5 kuMw== ARC-Message-Signature: i=1; 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Tue, 6 Mar 2018 14:33:24 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20180306143324eucas1p192653a37b36bf3bac2db20247fc0b1f3~ZW1z4T5I33083930839eucas1p12; Tue, 6 Mar 2018 14:33:24 +0000 (GMT) X-AuditID: cbfec7f2-1c1ff70000011644-33-5a9ea6b4f0a7 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id D2.0F.04178.4B6AE9A5; Tue, 6 Mar 2018 14:33:24 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P5600MGHB3ETD00@eusync1.samsung.com>; Tue, 06 Mar 2018 14:33:23 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 3/6] clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU driver Date: Tue, 06 Mar 2018 15:33:09 +0100 Message-id: <20180306143312.21035-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180306143312.21035-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsWy7djPc7pbls2LMuj5oWKxccZ6VovrX56z Wky6P4HF4vz5DewWH3vusVrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZr5+kF3REVhz5PIG5gbHRp4uRk0NCwERiQtcCli5GLg4hgRWMEg0PDjBC OJ8ZJd58WsYEU9V64wxUYhmjxIq329lAEkICDUwSM57Gg9hsAoYSXW+7wOIiAg4Snz+9Bmtg Fmhjkjh7YD/YJGGBNIlT8yaCFbEIqEqcnj4HLM4rYCvxYPsuRoht8hKLv+8Eq+EUsJO4c2km 2H0SAn9ZJVY0L2eGKHKR2DlpKSuELSzx6vgWdghbRqKz4yDU2fUSfd+PMEE09zBK7G2ZCpWw ljh8/CJYM7MAn8SkbdOBhnIAxXklOtqEIEo8JO6tu8AEEXaUWPRWAeL7iYwSnQc6WCcwSi1g ZFjFKJ5aWpybnlpsmJdarlecmFtcmpeul5yfu4kRGI2n/x3/tIPx66WkQ4wCHIxKPLwc3nOj hFgTy4orcw8xSnAwK4nwRujPixLiTUmsrEotyo8vKs1JLT7EKM3BoiTOG6dRFyUkkJ5Ykpqd mlqQWgSTZeLglGpgNDouto45dfKEF2ZJ7RNr1r3jO3LnmbCt7PKSY2vUn1dozd922jUk4f88 HybxUu2KBxe1fkrFfJ+6tuv975/8zsVxL86c3HxDw8KZr2uD2e4n89Ja9LxNXuw7aMR2xj32 /+G9Hzx3cvoetFI4nvBu2o8rp3SUCg9ut9n8ceF+y/nv5Sv8H/e9rlNiKc5INNRiLipOBAA+ DQ50wgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkluLIzCtJLcpLzFFi42I5/e/4Zd0ty+ZFGXzuYLLYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6M10/SCzoiK458nsDcwNjo08XIySEhYCLReuMMYxcjF4eQwBJGif+7HrNA OE1MEpM6bjGCVLEJGEp0ve1iA7FFBBwkPn96DdbBLNDBJLFn70OgBAeHsECaxN5+JpAaFgFV idPT54DZvAK2Eg+272KE2CYvsfj7TrA5nAJ2EncuzWQBsYWAai5P+M44gZFnASPDKkaR1NLi 3PTcYkO94sTc4tK8dL3k/NxNjMCA2Xbs5+YdjJc2Bh9iFOBgVOLh3eAxN0qINbGsuDL3EKME B7OSCG+E/rwoId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rznDSqjhATSE0tSs1NTC1KLYLJMHJxS DYzZ2tc2Nt8+d+D21eWl9pvNGW0F98ZODf3z/OsFyXvSFkK5U6v3ml0IW9oRr/22UC1uTdWm OYJM7vde1TuvT3K/EqO0xVx+8ZZXtzrDdnbHbX7u3GaxvbGKUbHh51SJsG1rmDOmn1Izi7q4 zCUk41RHm3PqWuPH97heOcTbvc73rJios17UQUuJpTgj0VCLuag4EQBRS4n5FAIAAA== X-CMS-MailID: 20180306143324eucas1p192653a37b36bf3bac2db20247fc0b1f3 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180306143324eucas1p192653a37b36bf3bac2db20247fc0b1f3 X-RootMTR: 20180306143324eucas1p192653a37b36bf3bac2db20247fc0b1f3 References: <20180306143312.21035-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Clocks related to DISP, GSC and MFC blocks require special handling for power domain turn on/off sequences. Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5 sub-CMU driver instantiated from Exynos5420 driver. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5-subcmu.c | 2 + drivers/clk/samsung/clk-exynos5420.c | 121 ++++++++++++++++++++++++------- drivers/soc/samsung/pm_domains.c | 2 + 4 files changed, 100 insertions(+), 26 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ef8900bc077f..b23d6cfac723 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index ac3983c8adf2..bea10f4b3ee2 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -165,6 +165,8 @@ static int __init exynos5_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5_clk_of_match[] = { + { .compatible = "samsung,exynos5420-clock", }, + { .compatible = "samsung,exynos5800-clock", }, { }, }; diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 6b10b70f7d72..c7b0f55dfbb6 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -19,6 +19,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -863,7 +864,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), - DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), @@ -912,8 +912,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), - /* Mfc Block */ - DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), /* PCM */ DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), @@ -932,8 +930,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), /* GSCL Block */ - DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", - DIV2_RATIO0, 4, 2), DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), /* MSCL Block */ @@ -1190,8 +1186,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", GATE_TOP_SCLK_GSCL, 7, 0, 0), - GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), - GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", GATE_IP_GSCL0, 4, 0, 0), GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", @@ -1205,10 +1199,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_IP_GSCL1, 3, 0, 0), GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", GATE_IP_GSCL1, 4, 0, 0), - GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", - GATE_IP_GSCL1, 6, 0, 0), - GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", - GATE_IP_GSCL1, 7, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", @@ -1227,18 +1217,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", GATE_IP_MSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), - GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), - GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), - GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), - GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", - GATE_IP_DISP1, 7, 0, 0), - GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", - GATE_IP_DISP1, 8, 0, 0), - GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", - GATE_IP_DISP1, 9, 0, 0), - /* ISP */ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), @@ -1255,11 +1233,98 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +}; + +static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { + DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), +}; + +static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), + GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), + GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), + GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), + GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", + GATE_IP_DISP1, 7, 0, 0), + GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", + GATE_IP_DISP1, 8, 0, 0), + GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", + GATE_IP_DISP1, 9, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ + { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ + { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ + { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ +}; + +static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { + DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", + DIV2_RATIO0, 4, 2), +}; + +static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { + GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), + GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), + GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", + GATE_IP_GSCL1, 6, 0, 0), + GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", + GATE_IP_GSCL1, 7, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { + { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ + { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ + { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ + { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ +}; + +static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), +}; + +static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), +}; - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { + { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ + { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ + { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ +}; + +static const struct exynos5_subcmu_info exynos5x_subcmus[] = { + { + .div_clks = exynos5x_disp_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), + .gate_clks = exynos5x_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), + .suspend_regs = exynos5x_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), + .pd_name = "DISP", + }, { + .div_clks = exynos5x_gsc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), + .gate_clks = exynos5x_gsc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), + .suspend_regs = exynos5x_gsc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), + .pd_name = "GSC", + }, { + .div_clks = exynos5x_mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), + .gate_clks = exynos5x_mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), + .suspend_regs = exynos5x_mfc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), + .pd_name = "MFC", + }, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { @@ -1472,6 +1537,8 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); exynos5420_clk_sleep_init(); + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), + exynos5x_subcmus); samsung_clk_of_add_provider(np, ctx); } @@ -1480,10 +1547,12 @@ static void __init exynos5420_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5420); } -CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", + exynos5420_clk_init); static void __init exynos5800_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5800); } -CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", + exynos5800_clk_init); diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index cef30bdf19b1..f2d6d7a09c16 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -148,6 +148,8 @@ static __init const char *exynos_get_domain_name(struct device_node *node) } static const char *soc_force_no_clk[] = { + "samsung,exynos5420-clock", + "samsung,exynos5800-clock", }; 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Tue, 6 Mar 2018 14:33:25 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180306143324eucas1p2ab3484f3e05f3bea06e0be51e0d4791c~ZW10UkEIa0471704717eucas1p2L; Tue, 6 Mar 2018 14:33:24 +0000 (GMT) X-AuditID: cbfec7f5-b45ff700000028a9-b7-5a9ea6b517b3 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 16.91.04183.4B6AE9A5; Tue, 6 Mar 2018 14:33:24 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P5600MGHB3ETD00@eusync1.samsung.com>; Tue, 06 Mar 2018 14:33:24 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 4/6] clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU driver Date: Tue, 06 Mar 2018 15:33:10 +0100 Message-id: <20180306143312.21035-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180306143312.21035-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsWy7djPc7pbl82LMni6ntVi4wwgcf3Lc1aL SfcnsFicP7+B3eJjzz1Wixnn9zFZrD1yl93i8Jt2VgcOj02rOtk8+rasYvT4vEkugDmKyyYl NSezLLVI3y6BK+Pn8UssBS3GFe0rlBoYX2l3MXJwSAiYSGxZ7tDFyMUhJLCCUeLe9xnsEM5n RokJfZ2sXYycYEUtm9czQySWMUo8m7kWLCEk0MAk8fGXLIjNJmAo0fW2iw3EFhFwkPj86TUj SAOzQBuTxNkD+5lA1gkLpEncuR8JUsMioCpxY0I3C4jNK2ArMWf3L3aIZfISi7/vBJvDKWAn cefSTBaQORICP1kl9qx5xQZR5CLRuuQhE4QtLPHq+BaoZhmJy5MhhkoI1Ev0fT/CBNHcwyix t2UqVIO1xOHjF8E+YBbgk5i0bTozJCx4JTrahCBKPCQubNgJ9b2jxPeJFxghvp/IKPG6q419 AqPUAkaGVYziqaXFuempxcZ5qeV6xYm5xaV56XrJ+bmbGIGxePrf8a87GPf9STrEKMDBqMTD u8FjbpQQa2JZcWXuIUYJDmYlEd4I/XlRQrwpiZVVqUX58UWlOanFhxilOViUxHnjNOqihATS E0tSs1NTC1KLYLJMHJxSDYwCe19rnVvylO+BZcYFmcOvXr7+26bZ5n481q9Y7u06sfW7DUuW zlh2vvXI0jjWQP3FLSu3H5Z3fGaynzVFvzr7ZoZRSfI85r/HeGar5s+4eCp9z8UfhaWcR49d 67D88OvFsQv+J/e/2C/T5N6lbX7WXO+U0PmkLCPHY2rOdqkfdm/I3q3SwHBKiaU4I9FQi7mo OBEAB2xrvMECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpiluLIzCtJLcpLzFFi42I5/e/4Zd0ty+ZFGXx9KmWxccZ6VovrX56z Wky6P4HF4vz5DewWH3vusVrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZP49fYiloMa5oX6HUwPhKu4uRk0NCwESiZfN65i5GLg4hgSWMEiceT2WH cJqYJCbeW8oEUsUmYCjR9baLDcQWEXCQ+PzpNSNIEbNAB5PEnr0PwRLCAmkSz68uAGtgEVCV uDGhmwXE5hWwlZiz+xc7xDp5icXfd4LVcwrYSdy5NBOsRgio5vKE74wTGHkWMDKsYhRJLS3O Tc8tNtIrTswtLs1L10vOz93ECAyZbcd+btnB2PUu+BCjAAejEg/vBo+5UUKsiWXFlbmHGCU4 mJVEeCP050UJ8aYkVlalFuXHF5XmpBYfYpTmYFES5z1vUBklJJCeWJKanZpakFoEk2Xi4JRq YNy+8dyhf8V/o5pWCH/hEOkU31bS0cfwWEI3Ov95x67qnLdOLexzk5bO+25nOGHDghImzslN R3Xnye3LeHXCZu2CnPoqmWcr4+9vuFpSLKp2oTNORHXluhKWRw/ntctKSzMqaOWc778qYiE7 tS7yXrO06c4NF61SYw11S9kT9bhUHD7XznF5psRSnJFoqMVcVJwIAGRgwsoVAgAA X-CMS-MailID: 20180306143324eucas1p2ab3484f3e05f3bea06e0be51e0d4791c X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180306143324eucas1p2ab3484f3e05f3bea06e0be51e0d4791c X-RootMTR: 20180306143324eucas1p2ab3484f3e05f3bea06e0be51e0d4791c References: <20180306143312.21035-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Clocks related to DISP1 block require special handling for power domain turn on/off sequences. Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5-subcmu.c | 1 + drivers/clk/samsung/clk-exynos5250.c | 51 ++++++++++++++++++++++---------- drivers/soc/samsung/pm_domains.c | 1 + 4 files changed, 38 insertions(+), 16 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b23d6cfac723..513826393158 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5-subcmu.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index bea10f4b3ee2..93306283d764 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -165,6 +165,7 @@ static int __init exynos5_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5_clk_of_match[] = { + { .compatible = "samsung,exynos5250-clock", }, { .compatible = "samsung,exynos5420-clock", }, { .compatible = "samsung,exynos5800-clock", }, { }, diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 1b3a8f9cd519..06e5ddcb30db 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -18,6 +18,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -571,17 +572,6 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, - 0), - GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, - 0), - GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, - 0), - GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, - 0), - GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, - 0), GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, @@ -671,10 +661,6 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), - GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 9, 0, 0), - GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 8, 0, 0), GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", GATE_IP_ISP0, 8, 0, 0), @@ -698,6 +684,38 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE_IP_ISP1, 7, 0, 0), }; +static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, + 0), + GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, + 0), + GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, + 0), + GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, + 0), + GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, + 0), + GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 9, 0, 0), + GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 8, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */ + { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */ +}; + +static const struct exynos5_subcmu_info exynos5250_disp_subcmu = { + .gate_clks = exynos5250_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks), + .suspend_regs = exynos5250_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs), + .pd_name = "DISP1", +}; + static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -859,10 +877,11 @@ static void __init exynos5250_clk_init(struct device_node *np) __raw_writel(tmp, reg_base + PWR_CTRL2); exynos5250_clk_sleep_init(); + exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", _get_rate("div_arm2")); } -CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index f2d6d7a09c16..caf45cf7aa8e 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -148,6 +148,7 @@ static __init const char *exynos_get_domain_name(struct device_node *node) } static const char *soc_force_no_clk[] = { + "samsung,exynos5250-clock", "samsung,exynos5420-clock", "samsung,exynos5800-clock", }; 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Mark clock related properties in Exynos power domain bindings as deprecated. This change has no inpact on backwards-compatibility, as the new drivers properly work with old DTBs (deprecated properties are ignored). Signed-off-by: Marek Szyprowski --- .../devicetree/bindings/power/pd-samsung.txt | 20 +---- drivers/soc/samsung/pm_domains.c | 90 +--------------------- 2 files changed, 5 insertions(+), 105 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt index 549f7dee9b9d..92ef355e8f64 100644 --- a/Documentation/devicetree/bindings/power/pd-samsung.txt +++ b/Documentation/devicetree/bindings/power/pd-samsung.txt @@ -15,23 +15,13 @@ Required Properties: Optional Properties: - label: Human readable string with domain name. Will be visible in userspace to let user to distinguish between multiple domains in SoC. -- clocks: List of clock handles. The parent clocks of the input clocks to the - devices in this power domain are set to oscclk before power gating - and restored back after powering on a domain. This is required for - all domains which are powered on and off and not required for unused - domains. -- clock-names: The following clocks can be specified: - - oscclk: Oscillator clock. - - clkN: Input clocks to the devices in this power domain. These clocks - will be reparented to oscclk before switching power domain off. - Their original parent will be brought back after turning on - the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - - asbN: Clocks required by asynchronous bridges (ASB) present in - the power domain. These clock should be enabled during power - domain on/off operations. - power-domains: phandle pointing to the parent power domain, for more details see Documentation/devicetree/bindings/power/power_domain.txt +Deprecated Properties: +- clocks +- clock-names + Node of a device using power domains must have a power-domains property defined with a phandle to respective power domain. @@ -47,8 +37,6 @@ Example: mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; #power-domain-cells = <0>; label = "MFC"; }; diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index caf45cf7aa8e..ab8582971bfc 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -13,14 +13,11 @@ #include #include #include -#include #include #include #include #include -#define MAX_CLK_PER_DOMAIN 4 - struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; @@ -33,10 +30,6 @@ struct exynos_pm_domain { void __iomem *base; bool is_off; struct generic_pm_domain pd; - struct clk *oscclk; - struct clk *clk[MAX_CLK_PER_DOMAIN]; - struct clk *pclk[MAX_CLK_PER_DOMAIN]; - struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; u32 local_pwr_cfg; }; @@ -46,29 +39,10 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) void __iomem *base; u32 timeout, pwr; char *op; - int i; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_prepare_enable(pd->asb_clk[i]); - } - - /* Set oscclk before powering off a domain*/ - if (!power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - pd->pclk[i] = clk_get_parent(pd->clk[i]); - if (clk_set_parent(pd->clk[i], pd->oscclk)) - pr_err("%s: error setting oscclk as parent to clock %d\n", - domain->name, i); - } - } - pwr = power_on ? pd->local_pwr_cfg : 0; writel_relaxed(pwr, base); @@ -86,26 +60,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) usleep_range(80, 100); } - /* Restore clocks after powering on a domain*/ - if (power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - - if (IS_ERR(pd->pclk[i])) - continue; /* Skip on first power up */ - if (clk_set_parent(pd->clk[i], pd->pclk[i])) - pr_err("%s: error setting parent to clock%d\n", - domain->name, i); - } - } - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_disable_unprepare(pd->asb_clk[i]); - } - return 0; } @@ -147,12 +101,6 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } -static const char *soc_force_no_clk[] = { - "samsung,exynos5250-clock", - "samsung,exynos5420-clock", - "samsung,exynos5800-clock", -}; - static __init int exynos4_pm_init_power_domain(void) { struct device_node *np; @@ -161,7 +109,7 @@ static __init int exynos4_pm_init_power_domain(void) for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) { const struct exynos_pm_domain_config *pm_domain_cfg; struct exynos_pm_domain *pd; - int on, i; + int on; pm_domain_cfg = match->data; @@ -189,42 +137,6 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_on = exynos_pd_power_on; pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; - for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++) - if (of_find_compatible_node(NULL, NULL, - soc_force_no_clk[i])) - goto no_clk; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "asb%d", i); - pd->asb_clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->asb_clk[i])) - break; - } - - pd->oscclk = of_clk_get_by_name(np, "oscclk"); - if (IS_ERR(pd->oscclk)) - goto no_clk; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "clk%d", i); - pd->clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->clk[i])) - break; - /* - * Skip setting parent on first power up. - * The parent at this time may not be useful at all. - */ - pd->pclk[i] = ERR_PTR(-EINVAL); - } - - if (IS_ERR(pd->clk[0])) - clk_put(pd->oscclk); - -no_clk: on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; pm_genpd_init(&pd->pd, NULL, !on); From patchwork Tue Mar 6 14:33:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 130814 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp4009627lja; Tue, 6 Mar 2018 06:33:37 -0800 (PST) X-Google-Smtp-Source: AG47ELsElkBCe5h7e+nKSZ5ZlSJ0+uZCgxNOtBjFSHK0JjE/ptROj5E2DRkfMuHDN7HnBNrliL60 X-Received: by 2002:a17:902:595d:: with SMTP id e29-v6mr17067095plj.189.1520346817444; Tue, 06 Mar 2018 06:33:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520346817; cv=none; d=google.com; s=arc-20160816; b=bj6Tv+FPakQOfGHEiNRbShV5549BK0J+BXnHaDfBPMbIL0MeZaZXnL1esK9ZO7ucI/ QzXrPWFHM9EAaLgGu78MZXRUgy1S6VdcqpPdrAbIWnICeEtMUPPjky9VMZdEjSl0M/Xd K3snO2Jr6klAB5c1kBgISbR0BYk5sr5k1LVxmZmCFfnKL+2VOTYwzxJJzX1LDJwZyoSt mPecvBkdoRVJ3/WbLQ435Pf7okalvVsctHBWOuc1iIVIQEg/t7yoOdEz1n2fgJDj15X7 XifS+yaWSv8RenDNgqyvDKeYFKa4mQpnYNpPufjnlNUziPirT1eG/f0XzGvUqD+mLsFB GH4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=iTxEGbfzy1u+Qye4LeBAgUY+ayjj0CARpCLVAG6TbiI=; b=cMtd32t9vQ533T3DLSSiL216IMrY/jCgmTFUphoUAwQOdsGTh7IP6qszuwaf6w92DJ voS0YY53wc98FuFBz/IhW10m44i5k//nvw2cImzEQKDtn3zq+SfL4F7zVuyvIavxwfNC 3vXFqokhFbZvwuCusZ8SU0rlEupVSI0g8L/8Gu4Lk9dP1Bw3jh+R9i5Mo7tnlbpvg6F5 ipfZUzB8Z567Z/gbOmVYg6w2BsWuhKj+uOHYZBpNJY6hKvHa5rPJZ+oZR6rfNgnV/4Af 6vIS9GYGZUKsGG7v+nsJMaNY4xQbZ/Vyt2EnVU0EBXis8t2+HtJbOt/2EYMxEdUGiYXH ggbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=RRH8ZbCJ; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 6 Mar 2018 14:33:25 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180306143325eucas1p2f0fe850a9d23dd467fb1814581159539~ZW11EYyL31273712737eucas1p2v; Tue, 6 Mar 2018 14:33:25 +0000 (GMT) X-AuditID: cbfec7f4-713ff700000043e4-0b-5a9ea6b549b7 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id A7.91.04183.5B6AE9A5; Tue, 6 Mar 2018 14:33:25 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P5600MGHB3ETD00@eusync1.samsung.com>; Tue, 06 Mar 2018 14:33:25 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 6/6] ARM: dts: exynos: Remove obsolete clock properties from power domains Date: Tue, 06 Mar 2018 15:33:12 +0100 Message-id: <20180306143312.21035-7-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180306143312.21035-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsWy7djPc7pbl82LMmh6p2+xccZ6VovrX56z Wky6P4HF4vz5DewWH3vusVrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZi3dEF6wWqphz4wZrA+MTvi5GTg4JAROJ1kVz2bsYuTiEBFYwShzZ1Q7l fGaU2LmhjRmm6vDkjYwQiWWMEq/v7GWFcBqYJDb1H2IHqWITMJToetvFBmKLCDhIfP70GqyD WaCNSeLsgf1MIAlhgXiJq3eWsoLYLAKqEhsmNzOC2LwCthKtDU9YINbJSyz+vhNsEKeAncSd SzNZQAZJCPxklTj++BYrRJGLxOzmBewQtrDEq+NboGwZicuTu6EG1Uv0fT/CBNHcwyixt2Uq E0TCWuLw8Ytgg5gF+CQmbZsO9CgHUJxXoqNNCKLEQ2LruedQ/ztKrDu/FqxcSGAi0JwLrhMY pRYwMqxiFE8tLc5NTy02ykst1ytOzC0uzUvXS87P3cQIjMfT/45/2cG460/SIUYBDkYlHl4O 77lRQqyJZcWVuYcYJTiYlUR4I/TnRQnxpiRWVqUW5ccXleakFh9ilOZgURLnjdOoixISSE8s Sc1OTS1ILYLJMnFwSjUwxtmcnK75dKbFp9/3VXaIXr7Ak/FGZN73NUz6rEEJPc2ObBL3ri9R rTLxqkvLvlRuLMD9rTSg9dKRxlZz3XadoOn1kd4y19S2fv+yPWfHF8lzbAm/SxtYTR59e6rM 1h1aNStoxilWjb8c4R6l9ucWvP49+Xj8Mzc+4UehTmUcnq9W50UfyVVXYinOSDTUYi4qTgQA RID6ncMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkluLIzCtJLcpLzFFi42I5/e/4Zd2ty+ZFGZxuFrHYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MxTuiC1YLVcy5cYO1gfEJXxcjJ4eEgInE4ckbGbsYuTiEBJYwSrzvmM0O khASaGKSmPHLEMRmEzCU6HrbxQZiiwg4SHz+9BqsgVmgg0liz96HYAlhgXiJ9fOfM4LYLAKq EhsmN4PZvAK2Eq0NT1ggtslLLP6+E6yeU8BO4s6lmSwQy2wlLk/4zjiBkWcBI8MqRpHU0uLc 9NxiI73ixNzi0rx0veT83E2MwIDZduznlh2MXe+CDzEKcDAq8fBu8JgbJcSaWFZcmXuIUYKD WUmEN0J/XpQQb0piZVVqUX58UWlOavEhRmkOFiVx3vMGlVFCAumJJanZqakFqUUwWSYOTqkG xnPPT4VFln7zfjf93cuo066++7dlnPFs+aVsuyvEYuPbf/ZdfEFR+5oOPNlp0WXtanjryGbz towJ1gc69Hfft2D7KZwxw71znZsZZ0Kj6HTOWHmWm8vPhIkv6Ag8HPoiyrRp9QNPvqVTGf0f hG4SiNzFup1rck2JplaL1OSsOXsCWPc/ZORbosRSnJFoqMVcVJwIAAtWnjIUAgAA X-CMS-MailID: 20180306143325eucas1p2f0fe850a9d23dd467fb1814581159539 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180306143325eucas1p2f0fe850a9d23dd467fb1814581159539 X-RootMTR: 20180306143325eucas1p2f0fe850a9d23dd467fb1814581159539 References: <20180306143312.21035-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Handling of special clock operations on power domain on/off sequences has been moved to respective Exynos clock controller drivers and clock properties have been marked as deprecated. Remove all clock properties from existing Exynos power domain nodes, as they are no longer used. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5250.dtsi | 4 ---- arch/arm/boot/dts/exynos5420.dtsi | 14 -------------- 2 files changed, 18 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 179ef73e576a..e74f370face6 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -132,10 +132,6 @@ reg = <0x100440A0 0x20>; #power-domain-cells = <0>; label = "DISP1"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_ACLK200_DISP1_SUB>, - <&clock CLK_MOUT_ACLK300_DISP1_SUB>; - clock-names = "oscclk", "clk0", "clk1"; }; pd_mau: power-domain@100440c0 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2f3cb2a97f71..9672d0e51f69 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -276,10 +276,6 @@ reg = <0x10044000 0x20>; #power-domain-cells = <0>; label = "GSC"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 { @@ -292,10 +288,6 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; - clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; label = "MFC"; }; @@ -312,12 +304,6 @@ reg = <0x100440C0 0x20>; #power-domain-cells = <0>; label = "DISP"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; mau_pd: power-domain@100440e0 {