From patchwork Mon Jan 25 03:15:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hailong Fan X-Patchwork-Id: 370359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 509E1C433DB for ; Mon, 25 Jan 2021 03:17:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 178D722472 for ; Mon, 25 Jan 2021 03:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbhAYDQw (ORCPT ); Sun, 24 Jan 2021 22:16:52 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:41538 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727003AbhAYDQM (ORCPT ); Sun, 24 Jan 2021 22:16:12 -0500 X-UUID: 398615451dfb4218851be9acf96b5b01-20210125 X-UUID: 398615451dfb4218851be9acf96b5b01-20210125 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 387554124; Mon, 25 Jan 2021 11:15:21 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 25 Jan 2021 11:15:18 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 25 Jan 2021 11:15:17 +0800 From: Hailong Fan To: Sean Wang , Linus Walleij , Matthias Brugger CC: , , , , , Nicolas Boichat , , , , , , Hailong Fan Subject: [PATCH] pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt Date: Mon, 25 Jan 2021 11:15:13 +0800 Message-ID: <20210125031513.1741-1-hailong.fan@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org When flipping the polarity will be generated interrupt under certain circumstances, but GPIO external signal has not changed. Then, mask the interrupt before polarity setting, and clear the unexpected interrupt after trigger type setting completed. Signed-off-by: Hailong Fan --- [V2] --- drivers/pinctrl/mediatek/mtk-eint.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 22736f60c16c..0042f32c7e7e 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -157,6 +157,7 @@ static void mtk_eint_ack(struct irq_data *d) static int mtk_eint_set_type(struct irq_data *d, unsigned int type) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); + bool unmasked; u32 mask = BIT(d->hwirq & 0x1f); void __iomem *reg; @@ -173,6 +174,13 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) else eint->dual_edge[d->hwirq] = 0; + if (!mtk_eint_get_mask(eint, d->hwirq)) { + mtk_eint_mask(d); + unmasked = true; + } else { + unmasked = false; + } + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); writel(mask, reg); @@ -189,8 +197,9 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) writel(mask, reg); } - if (eint->dual_edge[d->hwirq]) - mtk_eint_flip_edge(eint, d->hwirq); + mtk_eint_ack(d); + if (unmasked) + mtk_eint_unmask(d); return 0; }