From patchwork Fri Mar 2 05:48:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130467 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp906331lja; Thu, 1 Mar 2018 21:50:55 -0800 (PST) X-Google-Smtp-Source: AG47ELt5rYbPxOr20lBDZNcC52cwoG7a8XoZKrtiPhGExRhHdZ7Jdu7fgxqxB94KbGXw+q2Szdz0 X-Received: by 10.99.123.12 with SMTP id w12mr3532570pgc.405.1519969855773; Thu, 01 Mar 2018 21:50:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519969855; cv=none; d=google.com; s=arc-20160816; b=w1WDqkIKcKfYwJ3uhYESd8ikdhhtLDk6s78sJV+OJJuqT7tamJ1wrrWE0ejljBsTIK m/intRL3HnVBArNycEKuAg7qKUtcNTNq+CxqrHzQVGfoJh8XyBUKszfh57SjL96z5se5 aoJq3d2cc+t+Vtq4gIG+1ygtA6IFnTm3/kUm/ciJDJwvZGYYBiq+YooPW2yXR69ITq/e D7wEbaXUTTMsFpAoEFi2qqm2Sqk7zkOtsFiPDe4PYmB9aiP4CnOsvEzN912q1c0dvgrR mfHZVdMPTOs9mC83AKwgf3YfOi7OzBZw9tE6AE55o+/HvEleDHGLa0O9YuuD23oAECiq jsXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xZ+7TzIMt9kn1OslAPx3GHaM9jZgp05naPrMk3wo2oA=; b=P+l6LJJgVa25maJ4kV8/gT3Zlpl2h4y8oqy8Y+O02dl15Phcn3WEnzj5KGX6uzv3HB RQLOYd9H9lsMF7VVHBa/j7rg9xHsIXC9WiInnflNGoJ55DW4KtI2yObOgf4esUZLB26Z pWqZyd8uKVFDV+wU6Pd7u5tk4/7ORmdJwlp/7e3HfvjihGNJzcqxepn4SqMNQIV5pes7 /j0swRIO2o7LY6yJSbGSsV/pNVoQTUOyLj7xu3BwB2Ks2lioYiu9svnBLiOd6+YG7IKQ OIp6ThEd+irfUXNCcrL+PKIOrvBSmt2K0QXuznJubNRYTj8fEt+eb+UF01xXclq7QErc wD0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QjM/5JnG; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t15si3548590pgu.62.2018.03.01.21.50.55; Thu, 01 Mar 2018 21:50:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QjM/5JnG; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935936AbeCBFuw (ORCPT + 6 others); Fri, 2 Mar 2018 00:50:52 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:37880 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935916AbeCBFut (ORCPT ); Fri, 2 Mar 2018 00:50:49 -0500 Received: by mail-pf0-f196.google.com with SMTP id h11so3144275pfn.4 for ; Thu, 01 Mar 2018 21:50:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HL5yk831w8iniSjN2dOA4JWU9QejjmpQ37WP/KgAJVE=; b=QjM/5JnG+1ANHXji4mJd2mA3gNg3QByjGcFzC1LpwjGI/FeW/rfWjoOJ7nCK1dyZQA yBvTkmqvEuOsyyD2dq8yL+w1pfdYe7dFOcOCIkXnqs+90e1KH3PFwN4pRYIMMPzub9YO JwrpecKkCGgxGnAiNtLpZaL7hBbPVYa+I7L2Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HL5yk831w8iniSjN2dOA4JWU9QejjmpQ37WP/KgAJVE=; b=WukKqPNLLXQb+pJiqKLOWZJG+PFeFr5VbWtu61ce/8UeoIBGN+G2Eg2Y6uLSetGwfH p9CJxnp9O2YTtdh58Bf7AcdapIznxNF3/Vso3WS+nwiwLCT50g9gjq8zzpKD08Lk08qY A8BTseY550l1uV9RqRZtpbNNaBbcuu0sBenPvFju5+bUKB9NwanILUtoWnVaSTkZLC8O fwrzIHUdRLyuPjP9yofj0Tstg1xL9TFuxcLyVCR9dyD3+nYHBAGAtEPCg7VQ0AsXq9xf K1UBpCen+MZ8E2x25PJXufWsQzhYL44HMGhMGF/HwRtWKzvww0fpYJcao6inBG6VCcfj d0tA== X-Gm-Message-State: APf1xPC8vfFhWZE7MSUCWBzbslyUdoiAozjDI0KWfYhQeQMl+akv53Q8 FgbqxtR02wgu3DBsCwYTZ4dd X-Received: by 10.98.254.6 with SMTP id z6mr4494363pfh.155.1519969848593; Thu, 01 Mar 2018 21:50:48 -0800 (PST) Received: from localhost.localdomain ([2405:204:71c0:7f9a:bd87:b648:dccb:cbc9]) by smtp.gmail.com with ESMTPSA id t63sm12569748pfj.44.2018.03.01.21.50.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Mar 2018 21:50:47 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v4 02/11] arm64: dts: actions: Add S900 clock management unit nodes Date: Fri, 2 Mar 2018 11:18:51 +0530 Message-Id: <20180302054900.11275-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> References: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Actions Semi S900 Clock Management Unit (CMU) nodes Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 11406f6d3a6d..fee0c9557656 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include #include / { @@ -88,6 +89,18 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + diff24M: diff24M { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -154,6 +167,13 @@ status = "disabled"; }; + cmu: clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@e0228000 { compatible = "actions,s900-timer"; reg = <0x0 0xe0228000 0x0 0x8000>; From patchwork Fri Mar 2 05:48:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 130471 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp906792lja; Thu, 1 Mar 2018 21:51:40 -0800 (PST) X-Google-Smtp-Source: AG47ELto7mMF0YyVIr5/hVqecNyNOoGBWw1upWEbJnM01q+CXbxH/BuUhQ/KEDsTFmCdjRBckbs0 X-Received: by 10.167.130.88 with SMTP id e24mr4487508pfn.169.1519969900133; Thu, 01 Mar 2018 21:51:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519969900; cv=none; d=google.com; s=arc-20160816; b=HxT1YxSVW/fiz/T6ssoH01R+IES1AUSXmOfdJAa4JBRDflIfFw3JXU7ytQ0IqQb6Kw QNo69yLPREKdGH5UF7W1h9wB/R28AVnt0pP1t8fQ+WRKOSnT1nXojb6tVs2B1HkcdRuI KibjodSMMawo3OBt0fPTRhYMAXZwuomTt0O08i7d8Mizgp84YzRFyb6se6WiSkORqcXS BMJoOy6yvwXIobVOb7r134WYRIBpsopGeK3SMf9mVDvI4DxVJmKJdPM/dGE2T/kxsdME r3a267UTYGOPvnTHeLUzGM/lQPimaZltyXqQ7Dm4MW5kz94jFEc1tzlKgFyq8GTRV37Z pvPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xc+6prY5HTXwoyEglwFdzVA0bA2ZA4GNguQ/giQmFm4=; b=pJK0nxPE4FZoE1ESrijsOmDPict/A6+vzyNlXNxSLySXmPtgOt0XTD4V6Y6rCxznf0 /Wy42yfZMuA/yTq9sMD8Hgb5Z4SGR4Xkboh3WBOLt9/bOVEhdJxWJBb0FGGpO9UlNOht 6QTbJ5MhAPfzSN3CIEmkZuG9UH5wuwU/iewstHx2zmQqwwdOq7hjEfyaCwL3fM92nQk4 LN6hWaa9Tf+kZ+9jT4ej5xOsASBI226q6OSH5jb7rGiAKZwSU7orkDlfoh/EhE62cNXj QLCy6R/UL0gVEcYca7JyoYwLKIY3uwiN6is2Cfstxhegs4AsMg7i1sxcj04V4lsEHaUD hszg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T4H13KDR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay8-v6si4228322plb.614.2018.03.01.21.51.39; Thu, 01 Mar 2018 21:51:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T4H13KDR; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936019AbeCBFvc (ORCPT + 6 others); Fri, 2 Mar 2018 00:51:32 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:43833 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936002AbeCBFv3 (ORCPT ); Fri, 2 Mar 2018 00:51:29 -0500 Received: by mail-pf0-f193.google.com with SMTP id j2so1391007pff.10 for ; Thu, 01 Mar 2018 21:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=T4H13KDRb2YC7P3GYoRYYkZvFJq06zfw4RKpkdx65F89I/yX4FE5uVf5pSE3ppu4Wl BL0k4M/b/o7cR99IcjPetEk+7voajji2lkaRxQKfC8TOvLr023gZVzBZxFstfQ+kLLg9 Vy96/+jyI++ZsxwpitfQj7TKMxBUD2BvuG0N4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=JXs4j68ptkspQGH/j0rA69aznyomQDeSlgpURClaLXj34xJiljW5nQx540f8TC0XbT 7l/gppIA/sIV9TJNR3gDZUljiFeedn6Qofbjv7I87CgGvE1HmZCR/m+E/sfOgsFMSGfM P8wwNrXBO3nX9KvWmHkyXZlOpiKr69p8yW8CewrATpC9k23X0172+NNbmb3CTcimgRfF hKBSotZ5UPGDNQ8E0nr+7aOKVdIq3sQLt6xYNAKqIaDIb4LWL7L7DIh26Fmc6iKe5ZFL VUci613PR4OOAgoowqG0F6FmDLg/uind9Jx1vVn5xRIW1KTaKy9Dauii+ufit30/ezpb qbVw== X-Gm-Message-State: APf1xPAMKrb8DDDkWSvnGC55e+sc4da821rP2uk5uB9Y/3EKAbr6pfRG 7OLF2N8WoiBeYEVIBuDQA+gR X-Received: by 10.98.36.217 with SMTP id k86mr4540958pfk.137.1519969888652; Thu, 01 Mar 2018 21:51:28 -0800 (PST) Received: from localhost.localdomain ([2405:204:71c0:7f9a:bd87:b648:dccb:cbc9]) by smtp.gmail.com with ESMTPSA id t63sm12569748pfj.44.2018.03.01.21.51.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Mar 2018 21:51:28 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v4 06/11] clk: actions: Add mux clock support Date: Fri, 2 Mar 2018 11:18:55 +0530 Message-Id: <20180302054900.11275-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> References: <20180302054900.11275-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Actions Semi mux clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-mux.c | 60 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-mux.h | 61 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/clk/actions/owl-mux.c create mode 100644 drivers/clk/actions/owl-mux.h -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 1f0917872c9d..2d4aa8f35d90 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o clk-owl-y += owl-gate.o +clk-owl-y += owl-mux.o diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c new file mode 100644 index 000000000000..f9c6cf2540e4 --- /dev/null +++ b/drivers/clk/actions/owl-mux.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-mux.h" + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw) +{ + u32 reg; + u8 parent; + + regmap_read(common->regmap, mux_hw->reg, ®); + parent = reg >> mux_hw->shift; + parent &= BIT(mux_hw->width) - 1; + + return parent; +} + +static u8 owl_mux_get_parent(struct clk_hw *hw) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw); +} + +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index) +{ + u32 reg; + + regmap_read(common->regmap, mux_hw->reg, ®); + reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift); + regmap_write(common->regmap, mux_hw->reg, + reg | (index << mux_hw->shift)); + + return 0; +} + +static int owl_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index); +} + +const struct clk_ops owl_mux_ops = { + .get_parent = owl_mux_get_parent, + .set_parent = owl_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h new file mode 100644 index 000000000000..834284c8c3ae --- /dev/null +++ b/drivers/clk/actions/owl-mux.h @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_MUX_H_ +#define _OWL_MUX_H_ + +#include "owl-common.h" + +struct owl_mux_hw { + u32 reg; + u8 shift; + u8 width; +}; + +struct owl_mux { + struct owl_mux_hw mux_hw; + struct owl_clk_common common; +}; + +#define OWL_MUX_HW(_reg, _shift, _width) \ + { \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + } + +#define OWL_MUX(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct owl_mux _struct = { \ + .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &owl_mux_ops, \ + _flags), \ + }, \ + } + +static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_mux, common); +} + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw); +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index); + +extern const struct clk_ops owl_mux_ops; + +#endif /* _OWL_MUX_H_ */