From patchwork Fri Jan 22 11:24:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 368849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE57DC433E6 for ; Fri, 22 Jan 2021 11:34:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F45A2376F for ; Fri, 22 Jan 2021 11:34:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727658AbhAVLdf (ORCPT ); Fri, 22 Jan 2021 06:33:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728236AbhAVL1l (ORCPT ); Fri, 22 Jan 2021 06:27:41 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 265C4C061788 for ; Fri, 22 Jan 2021 03:27:01 -0800 (PST) Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1l2uae-0000Wv-Im; Fri, 22 Jan 2021 12:26:56 +0100 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1l2uae-0007dF-1t; Fri, 22 Jan 2021 12:26:56 +0100 From: Oleksij Rempel To: Rob Herring , William Breathitt Gray Cc: Oleksij Rempel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team , David Jander , Robin van der Gracht , linux-iio@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: counter: add gpio-pulse-counter binding Date: Fri, 22 Jan 2021 12:24:33 +0100 Message-Id: <20210122112434.27886-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210122112434.27886-1-o.rempel@pengutronix.de> References: <20210122112434.27886-1-o.rempel@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for GPIO based pulse counter node Signed-off-by: Oleksij Rempel --- .../bindings/counter/gpio-pulse-counter.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/gpio-pulse-counter.yaml diff --git a/Documentation/devicetree/bindings/counter/gpio-pulse-counter.yaml b/Documentation/devicetree/bindings/counter/gpio-pulse-counter.yaml new file mode 100644 index 000000000000..dfa93956f15c --- /dev/null +++ b/Documentation/devicetree/bindings/counter/gpio-pulse-counter.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/gpio-pulse-counter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO base pulse counter + +maintainers: + - Oleksij Rempel + +properties: + compatible: + const: virtual,gpio-pulse-counter + + gpios: + maxItems: 1 + +required: + - gpios + +additionalProperties: false + +examples: + - | + + #include + + counter-0 { + compatible = "virtual,gpio-pulse-counter"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + + counter-1 { + compatible = "virtual,gpio-pulse-counter"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; + +... From patchwork Fri Jan 22 11:24:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 369594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9B5BC433E6 for ; Fri, 22 Jan 2021 11:31:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6D7C235F9 for ; Fri, 22 Jan 2021 11:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727994AbhAVLbe (ORCPT ); Fri, 22 Jan 2021 06:31:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728347AbhAVL2a (ORCPT ); Fri, 22 Jan 2021 06:28:30 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F614C061793 for ; Fri, 22 Jan 2021 03:27:02 -0800 (PST) Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1l2uae-0000Ww-Im; Fri, 22 Jan 2021 12:26:56 +0100 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1l2uae-0007dO-2n; Fri, 22 Jan 2021 12:26:56 +0100 From: Oleksij Rempel To: Rob Herring , William Breathitt Gray Cc: Oleksij Rempel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengutronix Kernel Team , David Jander , Robin van der Gracht , linux-iio@vger.kernel.org Subject: [PATCH v3 2/2] counter: add GPIO based pulse counters Date: Fri, 22 Jan 2021 12:24:34 +0100 Message-Id: <20210122112434.27886-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210122112434.27886-1-o.rempel@pengutronix.de> References: <20210122112434.27886-1-o.rempel@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add simple GPIO base pulse counter. This device is used to measure rotation speed of some agricultural devices, so no high frequency on the counter pin is expected. The maximal measurement frequency depends on the CPU and system load. On the idle iMX6S I was able to measure up to 20kHz without count drops. Signed-off-by: Oleksij Rempel --- drivers/counter/Kconfig | 9 ++ drivers/counter/Makefile | 1 + drivers/counter/gpio-pulse-cnt.c | 244 +++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/counter/gpio-pulse-cnt.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 2de53ab0dd25..9ad1d9d49dd1 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -29,6 +29,15 @@ config 104_QUAD_8 The base port addresses for the devices may be configured via the base array module parameter. +config GPIO_PULSE_CNT + tristate "GPIO pulse counter driver" + depends on GPIOLIB + help + Select this option to enable GPIO pulse counter driver. + + To compile this driver as a module, choose M here: the + module will be called gpio-pulse-cnt. + config STM32_TIMER_CNT tristate "STM32 Timer encoder counter driver" depends on MFD_STM32_TIMERS || COMPILE_TEST diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index 0a393f71e481..6a5c3fc6f2a0 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_COUNTER) += counter.o obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o +obj-$(CONFIG_GPIO_PULSE_CNT) += gpio-pulse-cnt.o obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o obj-$(CONFIG_TI_EQEP) += ti-eqep.o diff --git a/drivers/counter/gpio-pulse-cnt.c b/drivers/counter/gpio-pulse-cnt.c new file mode 100644 index 000000000000..9454345c77ad --- /dev/null +++ b/drivers/counter/gpio-pulse-cnt.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Pengutronix, Oleksij Rempel + */ + +#include +#include +#include +#include +#include +#include + +#define GPIO_PULSE_NAME "gpio-pulse-counter" + +struct gpio_pulse_priv { + struct counter_device counter; + struct gpio_desc *gpio; + int irq; + bool enabled; + atomic_t count; +}; + +static irqreturn_t gpio_pulse_irq_isr(int irq, void *dev_id) +{ + struct gpio_pulse_priv *priv = dev_id; + + if (!priv->enabled) + return IRQ_NONE; + + atomic_inc(&priv->count); + + return IRQ_HANDLED; +} + +static ssize_t gpio_pulse_count_enable_read(struct counter_device *counter, + struct counter_count *count, + void *private, char *buf) +{ + struct gpio_pulse_priv *priv = counter->priv; + + return sysfs_emit(buf, "%d\n", priv->enabled); +} + +static ssize_t gpio_pulse_count_enable_write(struct counter_device *counter, + struct counter_count *count, + void *private, + const char *buf, size_t len) +{ + struct gpio_pulse_priv *priv = counter->priv; + bool enable; + ssize_t ret; + + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + if (priv->enabled == enable) + return len; + + priv->enabled = enable; + + if (enable) + enable_irq(priv->irq); + else + disable_irq(priv->irq); + + return len; +} + +static const struct counter_count_ext gpio_pulse_count_ext[] = { + { + .name = "enable", + .read = gpio_pulse_count_enable_read, + .write = gpio_pulse_count_enable_write, + }, +}; + +static enum counter_synapse_action gpio_pulse_synapse_actions[] = { + COUNTER_SYNAPSE_ACTION_RISING_EDGE, +}; + +static int gpio_pulse_action_get(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + size_t *action) +{ + *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; + + return 0; +} + +static int gpio_pulse_count_read(struct counter_device *counter, + struct counter_count *count, + unsigned long *val) +{ + struct gpio_pulse_priv *priv = counter->priv; + + *val = atomic_read(&priv->count); + + return 0; +} + +static int gpio_pulse_count_write(struct counter_device *counter, + struct counter_count *count, + const unsigned long val) +{ + struct gpio_pulse_priv *priv = counter->priv; + + atomic_set(&priv->count, val); + + return 0; +} + +static int gpio_pulse_count_function_get(struct counter_device *counter, + struct counter_count *count, + size_t *function) +{ + *function = COUNTER_COUNT_FUNCTION_INCREASE; + + return 0; +} + +static int gpio_pulse_count_signal_read(struct counter_device *counter, + struct counter_signal *signal, + enum counter_signal_value *val) +{ + struct gpio_pulse_priv *priv = counter->priv; + int ret; + + ret = gpiod_get_value(priv->gpio); + if (ret < 0) + return ret; + + *val = ret ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW; + + return 0; +} + +static const struct counter_ops gpio_pulse_cnt_ops = { + .action_get = gpio_pulse_action_get, + .count_read = gpio_pulse_count_read, + .count_write = gpio_pulse_count_write, + .function_get = gpio_pulse_count_function_get, + .signal_read = gpio_pulse_count_signal_read, +}; + +static struct counter_signal gpio_pulse_signals[] = { + { + .id = 0, + .name = "Channel 0 signal", + }, +}; + +static struct counter_synapse gpio_pulse_count_synapses[] = { + { + .actions_list = gpio_pulse_synapse_actions, + .num_actions = ARRAY_SIZE(gpio_pulse_synapse_actions), + .signal = &gpio_pulse_signals[0] + }, +}; + +static enum counter_count_function gpio_pulse_count_functions[] = { + COUNTER_COUNT_FUNCTION_INCREASE, +}; + +static struct counter_count gpio_pulse_counts[] = { + { + .id = 0, + .name = "Channel 1 Count", + .functions_list = gpio_pulse_count_functions, + .num_functions = ARRAY_SIZE(gpio_pulse_count_functions), + .synapses = gpio_pulse_count_synapses, + .num_synapses = ARRAY_SIZE(gpio_pulse_count_synapses), + .ext = gpio_pulse_count_ext, + .num_ext = ARRAY_SIZE(gpio_pulse_count_ext), + }, +}; + +static int gpio_pulse_cnt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_pulse_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + if (gpiod_count(dev, NULL) != 1) { + dev_err(dev, "Error, need exactly 1 gpio for device\n"); + return -EINVAL; + } + + priv->gpio = devm_gpiod_get(dev, NULL, GPIOD_IN); + if (IS_ERR(priv->gpio)) + return dev_err_probe(dev, PTR_ERR(priv->gpio), "failed to get gpio\n"); + + priv->irq = gpiod_to_irq(priv->gpio); + if (priv->irq < 0) { + dev_err(dev, "failed to map GPIO to IRQ: %d\n", priv->irq); + return priv->irq; + } + + priv->counter.name = dev_name(dev); + priv->counter.parent = dev; + priv->counter.ops = &gpio_pulse_cnt_ops; + priv->counter.counts = gpio_pulse_counts; + priv->counter.num_counts = ARRAY_SIZE(gpio_pulse_counts); + priv->counter.signals = gpio_pulse_signals; + priv->counter.num_signals = ARRAY_SIZE(gpio_pulse_signals); + priv->counter.priv = priv; + + ret = devm_request_irq(dev, priv->irq, gpio_pulse_irq_isr, + IRQF_TRIGGER_RISING | IRQF_NO_THREAD, + GPIO_PULSE_NAME, priv); + if (ret) + return ret; + + disable_irq(priv->irq); + + platform_set_drvdata(pdev, priv); + + return devm_counter_register(dev, &priv->counter); +} + +static const struct of_device_id gpio_pulse_cnt_of_match[] = { + { .compatible = "virtual,gpio-pulse-counter", }, + {} +}; +MODULE_DEVICE_TABLE(of, gpio_pulse_cnt_of_match); + +static struct platform_driver gpio_pulse_cnt_driver = { + .probe = gpio_pulse_cnt_probe, + .driver = { + .name = GPIO_PULSE_NAME, + .of_match_table = gpio_pulse_cnt_of_match, + }, +}; +module_platform_driver(gpio_pulse_cnt_driver); + +MODULE_ALIAS("platform:gpio-pulse-counter"); +MODULE_AUTHOR("Oleksij Rempel "); +MODULE_DESCRIPTION("GPIO pulse counter driver"); +MODULE_LICENSE("GPL v2");