From patchwork Fri Jan 22 12:21:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 368835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90561C433E0 for ; Fri, 22 Jan 2021 12:28:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5276823437 for ; Fri, 22 Jan 2021 12:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727204AbhAVMX7 (ORCPT ); Fri, 22 Jan 2021 07:23:59 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:7566 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727148AbhAVMXE (ORCPT ); Fri, 22 Jan 2021 07:23:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318183; x=1642854183; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=7rYGNcTg/1HVKG5Q5+jhx/w2uW/fXDa0rnOsfsil3bI=; b=cI132cSG/3Aa2/nyxMcdY9joPmqgFxQxtLU4tY05fen8uGNFztx7j3en +E41PeTddL9t8fMLF1SgeT5SVD0+muzrCGTQ6o6YXbdVuTUYKJrILJP0U K2EDgAO9urf+COO+pGkBCZ9qCZxlJV0PeEKBudRFfDpROYfQOXHIPjNRs zo2Qr/7Otf2TKdo7yToUzUydJmk4xzyrTRoxw991iKcHldu51anB/i+Gn Btqwjl9LcO4xxLb5JhxhI9wqQHOvPLdkGiwL+kJ7qcSzVzd10AxkDA7F5 MLbNtGRUVonecauTi6N5zVq82Y64sd2ihSVEh0u72L+isU7JH73eRouac Q==; IronPort-SDR: b6SCs0xzQiTO+6xlEO4WbAgc4JSGLfhhKitszkZewA72GYGpCil08H/NjDbxlIkvkcx56twSsX kis68F4tFxG9PmHvP0cJqvgtRX9lAb7MzLAaYexoN20+pHpgAUSO6YiW2mmB73kSj1uoUtRCUt 0VAzkSnzReZ4nIBZYeDmD/QUahQQqeVwz43q2GNt4ccBt+vwg8ul+X7lcN0lmofGsR51aEvOCK MB54hRIWjhMYItrejjpWriA4SYyXopRMTQe04+WdZgjX8wIoDuIG2rilBml2R7l/PGNGDnWRhG f28= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="112079684" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:21:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:21:48 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:21:44 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 1/7] drivers: soc: atmel: add spdx licence identifier Date: Fri, 22 Jan 2021 14:21:31 +0200 Message-ID: <1611318097-8970-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SPDX-Licence-Identifier. Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 1 + drivers/soc/atmel/soc.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 728d461ad6d6..1a6cb4bc7d67 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 Atmel * diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 5849846a69d6..3dc19c44e3a8 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2015 Atmel * From patchwork Fri Jan 22 12:21:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 369580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D473C433DB for ; Fri, 22 Jan 2021 12:27:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F420223A5F for ; Fri, 22 Jan 2021 12:27:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727847AbhAVMYI (ORCPT ); Fri, 22 Jan 2021 07:24:08 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:27722 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727570AbhAVMXI (ORCPT ); Fri, 22 Jan 2021 07:23:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318188; x=1642854188; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=vw00xgEn68i9C4mmR34lRmSRWa9lb5jp8d2mih7WHzw=; b=XxtLdReB6jlwjePn+k8wcYF5r5lGrC2OaQR77/O6oa8F4enjMwpGrxoi DUemdc43VrNYI2k8rkU7flS8jdtRftK0ONNLoc8IuDI7EzB/ZSjSaVpt/ UhGqbxj4H03M5lBlL1R/y5BM5uoDm4KdXxxprzODkA3PBh6B2kD29Dh6F +VXT9MCsR23hKf1e9eCijE8yHbc5GJrFknPTJANG5F1R5zSRQLV37p4qs EFRtD6PAiy6l6VtNHtad9ENv61FekV5hHUDg2AYzIZIQ7DeeRS3FSAdk0 3QkQLRR5ZEXGLRGLpVtqOk1cH4T7OjinQrfB8+IKVxDaMl6Kzw1xvq4q2 w==; IronPort-SDR: xVQWQgeiiCEYOND7mGIgdrf6VCKbtQ6rJZinh3Gj/JMmIzdUNPHfqeU7hcI1y1m0lB5G8U9g0P enNSxh59Zl7Ft/bIl4R8QXPlrCf/mK1R6zcrTd0CeTou1E5MH08TobcPOidMVPdZcs+Umso0M9 gfyOhUdISB59sxBlvcfv3fphaxZ7RmpOTt6A+MfSJfY9cXEqUhTDfMS+8kfB3bU5TdlwjBrjef e6zzbofHWADVWUiojCGXXdPIDsWyiKK2ppO/CAog/pWV4Iund+f7LX5cOQfV5G/K8OAsMugRU9 zOc= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="106908940" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:21:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:21:52 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:21:48 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 2/7] drivers: soc: atmel: use GENMASK Date: Fri, 22 Jan 2021 14:21:32 +0200 Message-ID: <1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use GENMASK() to define CIDR match mask. Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 1a6cb4bc7d67..ef591b622583 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -28,7 +28,7 @@ #define AT91_CHIPID_EXID 0x04 #define AT91_CIDR_VERSION(x) ((x) & 0x1f) #define AT91_CIDR_EXT BIT(31) -#define AT91_CIDR_MATCH_MASK 0x7fffffe0 +#define AT91_CIDR_MATCH_MASK GENMASK(30, 5) static const struct at91_soc __initconst socs[] = { #ifdef CONFIG_SOC_AT91RM9200 From patchwork Fri Jan 22 12:21:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 368834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C773C433DB for ; Fri, 22 Jan 2021 12:29:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BFB022202 for ; Fri, 22 Jan 2021 12:29:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728009AbhAVM22 (ORCPT ); Fri, 22 Jan 2021 07:28:28 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:27722 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727376AbhAVMX6 (ORCPT ); Fri, 22 Jan 2021 07:23:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318238; x=1642854238; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=wWtTJIMWC1g5SNBwfFQV6VJAAcc5lnSYixiNCayZhp8=; b=PS+XHMBLFkAL08uXMkX+AuPv+AyRWNduUl/lSBniYy9/UaaMULCz6k2Z ERh0ErTI/YHD+qmw96QoR1WBscS1DLlwB5x/+mcBcGHaVkBRqHL61Yeuw ZbxIBJLK7FCMDtMWyLyObM8qAJLECUAYtToVr0HtH6Hp1RdO4fgobYdjp x0MDEdkzE0hauPXJHXt3jcV7aPljlPzOmu3yTO35F19wsQhVB3mJeDexo BjTzPMxfHH/ZGICjxhusaBtNNoOpMhQdkCro3qXCrxCzwto0HCQI2csWR BuZhQ0UKfgBiIeCB5qoOrxjPQXfdfXZ74R70W0PmPO0XiIVHsLOyunDCp w==; IronPort-SDR: LMNcMZExVxPlwhmRYyQCeLTlZqEMRXYhQMKQC2w/osLv1OZHnV2Z9vANB0IqtEMCFxRmYpPIK4 BFd5fx9SJ75SoUOzSI2y3/aZCu155LGd5FvYr1u2kpdXeIdrjFiNazt3NJ4TJ0CxBfQFG3owVQ bh5LK8FjjMEN9VEnkCz2M3kTyoTpPexyo/tYUx4EgpKqA9+H7AeW/p6coZ1oNdQwaDVSW/dF5C GKoZW6FvFiplCoJv57h6Tl3jVcWckBDwZ7qGHqeunNLAUEwo/0gYKk7L1O1aaUEkWYEKEBfJoH 2Z4= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="106908946" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:21:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:21:57 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:21:52 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 3/7] drivers: soc: atmel: fix "__initconst should be placed after socs[]" warning Date: Fri, 22 Jan 2021 14:21:33 +0200 Message-ID: <1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix checkpatch.pl warning: "__initconst should be placed after socs[]". Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index ef591b622583..9d10a526cd3c 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -30,7 +30,7 @@ #define AT91_CIDR_EXT BIT(31) #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) -static const struct at91_soc __initconst socs[] = { +static const struct at91_soc socs[] __initconst = { #ifdef CONFIG_SOC_AT91RM9200 AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), #endif From patchwork Fri Jan 22 12:21:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 368837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C07AC433E0 for ; Fri, 22 Jan 2021 12:24:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5683F2376F for ; Fri, 22 Jan 2021 12:24:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727439AbhAVMYR (ORCPT ); Fri, 22 Jan 2021 07:24:17 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:37463 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727758AbhAVMXR (ORCPT ); Fri, 22 Jan 2021 07:23:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318197; x=1642854197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=4ZZbR+gfy81D0z3Xa1K28E9lwpQ/XAas5cIRZrYBinw=; b=W5ctgfCllYjl3uMCLnb20lNSLF9xt1uPKiIzuZboQatq2jTbt1+RMrHT 2ZX2DHxZX3SeePKRiZLfHIUTl2ZvCrynXkc2Tv5kulvUPE+4jodHrewSk ZH74OoOkAaYCiRpKHZWXZh6f5z9Hj/7Etya1On8vuZTsqrnlzDd89q1tN 4VJxwwSmXp4xMQSMKei797Z7Q7qJgowlHBt/+7f5cFIUgfcaRbvP1w5NL sEYExvIWjmuK/+NpXKExjpS9K2Xa/gMC2kPguV9KgnD7axK9i/9hlCVMg t8bJOsqOmV/4c8ZW72Sjrf4yqDseSgST/w8UiuVet6oeNq2KgD26bQSfE g==; IronPort-SDR: QNmEYipg4tuHZC/6y0tjxplJX1fSHmntBZK8YcBvbu570+XeVt3BCD5po0ycYgw5ojg8X4nKTh Aq+Zy/vzSfg6P5NC7JWAUH5RHuUt4OO+G9zrGx7IpcSB2RzHweZJKSLLCVycer5jkJevX1qbkK 7+7NhA0lwnP66hiK7ZCmycm3UBSH+DVLcMmMFmHs+trHg9Pn+idud/onNSLdd53suBhb5Rz8au OleaqT6l8AGRQB6VmFw1q0ICs330eU2vSd2871EW5ZK1R8o9RJVKPxZ/6nQUSFTUPEIVR7+qdM +gg= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="106393529" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:22:02 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:22:01 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:21:57 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 4/7] drivers: soc: atmel: add null entry at the end of at91_soc_allowed_list[] Date: Fri, 22 Jan 2021 14:21:34 +0200 Message-ID: <1611318097-8970-5-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org of_match_node() calls __of_match_node() which loops though the entries of matches array. It stops when condition: (matches->name[0] || matches->type[0] || matches->compatible[0]) is false. Thus, add a null entry at the end of at91_soc_allowed_list[] array. Fixes: 960ddf70cc11 ("drivers: soc: atmel: Avoid calling at91_soc_init on non AT91 SoCs") Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 9d10a526cd3c..a196e171f6cc 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -276,7 +276,8 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = { { .compatible = "atmel,at91rm9200", }, { .compatible = "atmel,at91sam9", }, { .compatible = "atmel,sama5", }, - { .compatible = "atmel,samv7", } + { .compatible = "atmel,samv7", }, + { } }; static int __init atmel_soc_device_init(void) From patchwork Fri Jan 22 12:21:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 368836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A9B8C433E0 for ; Fri, 22 Jan 2021 12:25:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 522CF23444 for ; Fri, 22 Jan 2021 12:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727888AbhAVMYU (ORCPT ); Fri, 22 Jan 2021 07:24:20 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:18204 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727889AbhAVMXb (ORCPT ); Fri, 22 Jan 2021 07:23:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318210; x=1642854210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=q+m8LsLA6F8v6Kkugs0dTBlGeUc4B5l4sL7shKYp1+Y=; b=w1nCRJL5vrCOp7K2zqxYi5hPAw+C1BACHr9/XrjcVdiRbM/dljcl6Pws vuPV0ggOe6c4AWDHOqQdbDmWYDhqv6/Q86tvz0agZ+ehWqRd/nzgh1jg0 37ratT3YZMXOx2maTm2e6OZmagQReZUWDmeE1jEcwRjwWAQ4FKIDCT7lm KULZa/vPgKsfgprOeTQgZgOiKtrq8awIKhUVRhQYgPKWFiQaNbaMuXCBA ViENrxwk9m75bNH4uASd5ygUsuMDWGZ8dQbLOl3IWUQ18uc9sdt4Tv3h/ 6NK1agun/rtBdG+94SX5AslfGkkD8pnwVtY+KVFbvbzQHNrLqfYSFRtiQ A==; IronPort-SDR: D4JPDgN8jY4Y/3B0t+S91kLC9yyg5nzzvi5bOQKPYEmkHtU+v+Yi7dWIoXmIpm+1V4rBfnetzm +Pf3WAYEqClFFnYCK5lcGCLTAAfPiPvBhpg59ePihnF1HzGOOqsv7M16lBikRzu0X2oElcbJ4k w8AElB5Lyf1S1t+/ejb5LYg/u2FZec6TcpsLCEVx0AZID1WDO1wcvNIWsJBbjowILaK7hdomUV TsztA+oVtO2/3sXtE5f3fHT35BIY+rcBzGdewiaklXHS9tNhtRd/qyeDVcuT3hg/ief82mWoOC jVs= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="103833122" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:22:06 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:22:06 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:22:01 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 5/7] drivers: soc: atmel: add per soc id and version match masks Date: Fri, 22 Jan 2021 14:21:35 +0200 Message-ID: <1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SAMA7G5 has different masks for chip ID and chip version on CIDR register compared to previous AT91 SoCs. For this the commit adapts the code for SAMA7G5 addition by introducing 2 new members in struct at91_soc and fill them properly and also preparing the parsing of proper DT binding. Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 199 ++++++++++++++++++++++++++++++++---------------- drivers/soc/atmel/soc.h | 7 +- 2 files changed, 140 insertions(+), 66 deletions(-) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index a196e171f6cc..54339b8243cc 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -26,135 +26,200 @@ #define AT91_DBGU_EXID 0x44 #define AT91_CHIPID_CIDR 0x00 #define AT91_CHIPID_EXID 0x04 -#define AT91_CIDR_VERSION(x) ((x) & 0x1f) +#define AT91_CIDR_VERSION(x, m) ((x) & (m)) +#define AT91_CIDR_VERSION_MASK GENMASK(4, 0) #define AT91_CIDR_EXT BIT(31) #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) static const struct at91_soc socs[] __initconst = { #ifdef CONFIG_SOC_AT91RM9200 - AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), + AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"), #endif #ifdef CONFIG_SOC_AT91SAM9 - AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL), - AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL), - AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL), - AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL), - AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL), - AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH, + AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL), + AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL), + AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL), + AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL), + AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL), + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH, "at91sam9m11", "at91sam9g45"), - AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH, + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH, "at91sam9m10", "at91sam9g45"), - AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH, + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH, "at91sam9g46", "at91sam9g45"), - AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH, + AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH, "at91sam9g45", "at91sam9g45"), - AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH, + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH, "at91sam9g15", "at91sam9x5"), - AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH, + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH, "at91sam9g35", "at91sam9x5"), - AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH, + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH, "at91sam9x35", "at91sam9x5"), - AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH, + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH, "at91sam9g25", "at91sam9x5"), - AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH, + AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH, "at91sam9x25", "at91sam9x5"), - AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH, + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH, "at91sam9cn12", "at91sam9n12"), - AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH, + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH, "at91sam9n12", "at91sam9n12"), - AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH, + AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH, "at91sam9cn11", "at91sam9n12"), - AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), - AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), - AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), + AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"), + AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"), + AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"), #endif #ifdef CONFIG_SOC_SAM9X60 - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, + "sam9x60", "sam9x60"), AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, "sam9x60 64MiB DDR2 SiP", "sam9x60"), AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, "sam9x60 128MiB DDR2 SiP", "sam9x60"), AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif #ifdef CONFIG_SOC_SAMA5 - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, "sama5d21", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH, "sama5d22", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH, "sama5d225c 16MiB SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH, "sama5d23", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH, "sama5d24", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH, "sama5d24", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH, "sama5d26", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH, "sama5d27", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH, "sama5d27", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH, "sama5d27c 128MiB SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH, "sama5d27c 64MiB SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH, "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH, "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH, "sama5d28", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH, "sama5d28", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH, "sama5d28c 128MiB SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH, "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"), - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH, "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"), - AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, + AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH, "sama5d31", "sama5d3"), - AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, + AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH, "sama5d33", "sama5d3"), - AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH, + AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH, "sama5d34", "sama5d3"), - AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH, + AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH, "sama5d35", "sama5d3"), - AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH, + AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH, "sama5d36", "sama5d3"), - AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH, + AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH, "sama5d41", "sama5d4"), - AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH, + AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH, "sama5d42", "sama5d4"), - AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH, + AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH, "sama5d43", "sama5d4"), - AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH, + AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH, "sama5d44", "sama5d4"), #endif #ifdef CONFIG_SOC_SAMV7 - AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH, + AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH, "same70q21", "same7"), - AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH, + AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, "same70q20", "same7"), - AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH, + AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK + AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, "same70q19", "same7"), - AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH, + AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH, "sams70q21", "sams7"), - AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH, + AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH, "sams70q20", "sams7"), - AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH, + AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH, "sams70q19", "sams7"), - AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH, + AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH, "samv71q21", "samv7"), - AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH, + AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH, "samv71q20", "samv7"), - AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH, + AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH, "samv71q19", "samv7"), - AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH, + AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH, "samv70q20", "samv7"), - AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH, + AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, "samv70q19", "samv7"), #endif { /* sentinel */ }, @@ -192,8 +257,12 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) { struct device_node *np; void __iomem *regs; + static const struct of_device_id chipids[] = { + { .compatible = "atmel,sama5d2-chipid" }, + { }, + }; - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); + np = of_find_matching_node(NULL, chipids); if (!np) return -ENODEV; @@ -236,7 +305,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) } for (soc = socs; soc->name; soc++) { - if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) + if (soc->cidr_match != (cidr & soc->cidr_mask)) continue; if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) @@ -255,7 +324,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) soc_dev_attr->family = soc->family; soc_dev_attr->soc_id = soc->name; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", - AT91_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr, soc->version_mask)); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { kfree(soc_dev_attr->revision); @@ -267,7 +336,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) if (soc->family) pr_info("Detected SoC family: %s\n", soc->family); pr_info("Detected SoC: %s, revision %X\n", soc->name, - AT91_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr, soc->version_mask)); return soc_dev; } diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 3dc19c44e3a8..0d2d27c30172 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -17,14 +17,19 @@ struct at91_soc { u32 cidr_match; + u32 cidr_mask; + u32 version_mask; u32 exid_match; const char *name; const char *family; }; -#define AT91_SOC(__cidr, __exid, __name, __family) \ +#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid, \ + __name, __family) \ { \ .cidr_match = (__cidr), \ + .cidr_mask = (__cidr_mask), \ + .version_mask = (__version_mask), \ .exid_match = (__exid), \ .name = (__name), \ .family = (__family), \ From patchwork Fri Jan 22 12:21:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 369581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93869C433E6 for ; Fri, 22 Jan 2021 12:24:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4AACC238EE for ; Fri, 22 Jan 2021 12:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727850AbhAVMYS (ORCPT ); Fri, 22 Jan 2021 07:24:18 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:37486 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727894AbhAVMXa (ORCPT ); Fri, 22 Jan 2021 07:23:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318211; x=1642854211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=poKO1QLD7vI0zCPnPL2EEcKhUF8lVOuEF/XvYo+LqT8=; b=PgwEP33rodw35pbEaZyh1OA6zBuGUBTbsVD55Dcs8VTToBlW8ly22Q5Z eLKnC1q9I3P2G2JfyPFTXqxe3nYfzKlVGk85UBtlYHv5ZxyBacWxPGxQJ 1xP4cRr+0TTsis+XcAJs58+IikbLw80dcgSVcbuTiuOnrB2fDz7XESdLq ih9gIQ3fZyorUj04bvzc6fWrYJ8hzqkmRqhsLQLu3wO5Hz7jG2i/NmLhI cImRCQsYfCUAn/MaxM1R84mZ4/WxqCnxIFwqxWmrWv7jB1AicI+pEioVM VEwNpRkTgN5tJ/ueVwJqd10vpRdRef2hHO2d/9e6VKfigZHvpZa4lPeBl w==; IronPort-SDR: zeRhjFLAE7mQi8FbHPLx8jxnmM5ZM41fqOs4fRI9fU/8qayj6MCjx0tJzB46e2pOABnVjsO4Xv pWbOOkpfb91iZBfXOMWHcs2TRZazjegbHHm6HCTKm94Knf/uEUWK3Bk8a1vKkfb8HsYZXfB5rk N987pAVQYkRYQ6g0qfSGohrxySZd06xMsKRyCwAAtw96JE4d+mMGxTZltsP33u1JWyJ4wIA+J0 aTr7xDmRubEtN+5AYTLF6BYEwQGS+dqF/lzXM+FHXyQ0i9ZUZYIDcVj3hUlHlX0BRzRFRX8l9d wWo= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="106393561" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:22:12 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:22:11 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:22:06 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 6/7] dt-bindings: atmel-sysreg: add "microchip, sama7g5-chipid" Date: Fri, 22 Jan 2021 14:21:36 +0200 Message-ID: <1611318097-8970-7-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT binding for SAMA7G5's CHIPID. Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 62cd4e89817c..67719f15eb4c 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -1,7 +1,7 @@ Atmel system registers Chipid required properties: -- compatible: Should be "atmel,sama5d2-chipid" +- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length PIT Timer required properties: From patchwork Fri Jan 22 12:21:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 369579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B8CC433DB for ; Fri, 22 Jan 2021 12:28:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78B6B239D1 for ; Fri, 22 Jan 2021 12:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727812AbhAVM20 (ORCPT ); Fri, 22 Jan 2021 07:28:26 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:18204 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727478AbhAVMYF (ORCPT ); Fri, 22 Jan 2021 07:24:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1611318245; x=1642854245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=xolhp4dgjUflUoqeBH1NUJ0euOxQfNgfon0sTm4wQ74=; b=AUrocmAztTq7rXwHvmsJP1jKeyiy6CUc+qMWltUdcbwRBBt3HRSsmMFo NUqXyIstq5uBv/voHtFKGJSbxhQK8Tl6RmIgej2m7RWM6e1tFd+GydkIS Jcpy1Gy8zqYfmOzjOkCwD92CZrkLiawBbpmej0qfyO1leRDp4urbqXmho L8+8XU443rWJh4tVEJxElwiIyN4BCCZ2+7QjczvU0uryTTOuR7kWZYY4K Nr+5sLkIQPHKAsz5szCCiNjBtFzQXPgkdANDH+S+shFgCD0EFl8IOhFnM X+DjeP15V+KbENp9ZEeM4LYN3nUp+ijmEE8PBS+fcGa+nZDuouL3/Dcpx w==; IronPort-SDR: drbhi+s8XmtQVheCwa3Df3MK84J5Bz8OFYQvH3GUR6PUR5Eq1uGuolitiTbQcEoiaLJ81WEUTE 9eYQHcx/bgX3YPbFXCrv2oz4WQAy5kConWvHW5tejynbmlCzU9YwQHhbGfjgRlLqRgpJFJOJFu Bz+vp9rvdWjXZn7Rvy0hjpA4TmkbMlciFx4Jz0PHoofz3szF8NyjqtDS1xSLtWGqFbkzubZUpw 35KerdbVHoGmcTd83KBlP2k0bm1cWf9FQsl+E6zfl9T2HKZ6X1TgzC948PasWKD9oODeToICE/ Maw= X-IronPort-AV: E=Sophos;i="5.79,366,1602572400"; d="scan'208";a="103833137" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jan 2021 05:22:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 22 Jan 2021 05:22:16 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 22 Jan 2021 05:22:11 -0700 From: Claudiu Beznea To: , , , CC: , , , Claudiu Beznea Subject: [PATCH 7/7] drivers: soc: atmel: add support for sama7g5 Date: Fri, 22 Jan 2021 14:21:37 +0200 Message-ID: <1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> References: <1611318097-8970-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for SAMA7G5 SoCs. Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 18 ++++++++++++++++++ drivers/soc/atmel/soc.h | 6 ++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 54339b8243cc..fb9d9cf8faf2 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -28,8 +28,10 @@ #define AT91_CHIPID_EXID 0x04 #define AT91_CIDR_VERSION(x, m) ((x) & (m)) #define AT91_CIDR_VERSION_MASK GENMASK(4, 0) +#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0) #define AT91_CIDR_EXT BIT(31) #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) +#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5) static const struct at91_soc socs[] __initconst = { #ifdef CONFIG_SOC_AT91RM9200 @@ -222,6 +224,20 @@ static const struct at91_soc socs[] __initconst = { AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, "samv70q19", "samv7"), #endif +#ifdef CONFIG_SOC_SAMA7 + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, + "sama7g51", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH, + "sama7g52", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH, + "sama7g53", "sama7g5"), + AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH, + "sama7g54", "sama7g5"), +#endif { /* sentinel */ }, }; @@ -259,6 +275,7 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) void __iomem *regs; static const struct of_device_id chipids[] = { { .compatible = "atmel,sama5d2-chipid" }, + { .compatible = "microchip,sama7g5-chipid" }, { }, }; @@ -346,6 +363,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = { { .compatible = "atmel,at91sam9", }, { .compatible = "atmel,sama5", }, { .compatible = "atmel,samv7", }, + { .compatible = "microchip,sama7g5", }, { } }; diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 0d2d27c30172..b2824b49096d 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -49,6 +49,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 +#define SAMA7G5_CIDR_MATCH 0x00162100 #define AT91SAM9M11_EXID_MATCH 0x00000001 #define AT91SAM9M10_EXID_MATCH 0x00000002 @@ -70,6 +71,11 @@ at91_soc_init(const struct at91_soc *socs); #define SAM9X60_D1G_EXID_MATCH 0x00000010 #define SAM9X60_D6K_EXID_MATCH 0x00000011 +#define SAMA7G51_EXID_MATCH 0x3 +#define SAMA7G52_EXID_MATCH 0x2 +#define SAMA7G53_EXID_MATCH 0x1 +#define SAMA7G54_EXID_MATCH 0x0 + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0