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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id j9sm614894ooq.1.2021.01.20.14.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 14:37:32 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: clock: qcom: rpmhcc: Add sc8180x rpmh clocks Date: Wed, 20 Jan 2021 14:37:40 -0800 Message-Id: <20210120223741.1610344-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Qualcomm SC8180x to the list of compatibles for the RPMHCC binding. Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.29.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 12c9cbc0ebf9..167b018effcc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,sc7180-rpmh-clk + - qcom,sc8180x-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk - qcom,sm8150-rpmh-clk From patchwork Wed Jan 20 22:37:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 367201 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp53375jam; Wed, 20 Jan 2021 15:56:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1HUnPsHlOU5nbwBtlIAvFdwQSpHI0eXMGyc+nIaDMy7mSPwhFu+cPobqXlMawDKDGVGeI X-Received: by 2002:a17:906:40ca:: with SMTP id a10mr7807490ejk.295.1611187001322; Wed, 20 Jan 2021 15:56:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611187001; cv=none; d=google.com; s=arc-20160816; b=Fkm606uQxn2hv01RW/8ckJz31+ONHwdlfjeOFFMi5BPhKrgP8hrL2O2I/e2ZUi5x9r 5KFbgXawLs0/wAveCLnSotawa4Ux+OkoR1upqt4w0o5AC9ulHsk+ptl9lBqeRM9iXKn4 tOIOCRC8OCr6F2IhMkdSN5xcoJ/sllYZk8Jn9CA2MTcNO4Z6I8vCDxIMQ4kbnAVbYhY2 AEt+/sWOBIRtyzVxd2jkHzDNri/Zu49k4/4HcZbWzzgSnqYvfMLpQBda0PPK5fSTZCKH BORZ4artraNzqt8KceXZrgvWsOjtuUgm/Lw8qfjq/beBxzNGcWdfMql/Oh6ZCY3k/1Qi GnnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6dk3qEQlAxZmfI82OkyXmz2gwMMTg8wFXIlLMCIVZCs=; b=NT8IDGt8irRUX4k5C4tgR9Kb6R4H8u0dusMSxJVHHjXe+YM7a1rWa/RCZaJQBNnuBd 4hvgs+ndvPIoTVIM2cYfVgAEC4JQd/O+UGmOkFieauo3ZR7P8WE15OqQpXX7vIjAoQ9F I1fHp7yKmA9YFzKPgTX6wLioaTHtxLdlaM+6kggfB9GjmwCsoKiZyL3EbOlMUMmnKgtt XZN9Ehj+aE+Mv3EIGUaTjnlY3Gfe1YYJyFLJCApDsA8zAeImgZuLLsFMP0IFR/yTxX91 mJmhxkzDrU/s00mKRwn015jeckIn9xWcwEprvdcG/X7f2K2abK/GTpR6fDtSXtmGQWG3 Ih5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D54trIQy; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id j9sm614894ooq.1.2021.01.20.14.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 14:37:33 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] clk: qcom: rpmhcc: Add sc8180x rpmh clocks Date: Wed, 20 Jan 2021 14:37:41 -0800 Message-Id: <20210120223741.1610344-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210120223741.1610344-1-bjorn.andersson@linaro.org> References: <20210120223741.1610344-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clocks provides by RPMH in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-rpmh.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.29.2 diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6a2a13c5058e..e356291f3ce7 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -348,6 +348,10 @@ DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); +DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); @@ -431,6 +435,26 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = { .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), }; +static struct clk_hw *sc8180x_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, + [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, + [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, + [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, + [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw, + [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sc8180x = { + .clks = sc8180x_rpmh_clocks, + .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), +}; + DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); static struct clk_hw *sm8250_rpmh_clocks[] = { @@ -570,6 +594,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, + { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},