From patchwork Thu Mar 1 06:57:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130109 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452289edc; Wed, 28 Feb 2018 22:58:09 -0800 (PST) X-Google-Smtp-Source: AG47ELs2oK/tEURKT8xqcAZGSyrrqC49/quTFOsUI7lvnU9ZjC03t+6au7P9W75J7oHv1lYsFOV3 X-Received: by 10.167.129.67 with SMTP id d3mr917704pfn.108.1519887488909; Wed, 28 Feb 2018 22:58:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887488; cv=none; d=google.com; s=arc-20160816; b=toABQhy0GyxfTxmZZCr4MGCfOib013RA4R0Zqt8TGYsAqVXZ4Qcqos8hDAPABCNjjA 4EfLIeuwnu+EfDCGp5UetJzsm46BMKOq8zoAeVlr1FzFgGIG86qEoAASbf91q3V/pkm6 urQcGPn/Wuue7Cxf7onU+8hxunt9Lp8TgsUS+xyKAu5HUzoqd3aNe1bmmBxBoyqfUcmu hOABc51fafn+xRjJdYxDEo/VMoMgMDP8Slga18gd9eC1iV3DUPuKcsWyJtEqsqeVfU7C 2T7lHqDaKUV6UmIaYznBL+Zk0kxg3k46engJdkVC2mxDBelMVa++Dag14Ecyucu0PNoF A34g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=bd0b6YwFnPgSIxGREise3mTeaEVfY+e/9Oub5BXJZb0=; b=QUJgO3sGPoINLzLCVYprWhEGxRrU4KvimtHLSE3IKqBGO/GESoahagHdXQ3nBiMFt2 f79neL48eGbXOO31o11YCK1kcRHPEBtjpD2GnBaljUB9OCx2yonBjGVVocWUynhfrJzc NH3DOMhtnvO8+0UvbvTbz4g+puiB76AdcARpaNB4joB7f1qcelXQThO2GFBfQsQwCkyE u2j+QTQkrr0xeDOEnhtJYpa3DeITU17sN878JklVRDbuoBBwBmCD3lUhuj5rNgj2UUGz IepkqpfqgRTeb9M05f8HQ8UHJjG3m4yanjbDK/f5rFJ47XZ+JAUYbMfE/uk23cWWnqSH ftng== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Cjf5Bq+t; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id q25si2541007pfl.289.2018.02.28.22.58.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Cjf5Bq+t; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3395C22423854; Wed, 28 Feb 2018 22:52:00 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8F9692242384D for ; Wed, 28 Feb 2018 22:51:58 -0800 (PST) Received: by mail-pg0-x241.google.com with SMTP id l131so1971034pga.2 for ; Wed, 28 Feb 2018 22:58:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZXGYrKCbwlIxDn7EQlJvo+VP5AeLWXCh9RIif8O+dJY=; b=Cjf5Bq+ttx0Yt30LYm9anBLXnB1NnMLgCyyxZI8oG4VUOKIcOWdpzhScIKD9C+WirZ WvgNalUJse6IFXIW3Bh2N0gKXr17bFbjSlvJZh0TrNEdRzpmy9TxwOc8wF7nyJjHwE8m ZiXXHnpHn2V+Sopr9TRvlSEdu4wJL6D5I4aNI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZXGYrKCbwlIxDn7EQlJvo+VP5AeLWXCh9RIif8O+dJY=; b=YS4a+pVNi4iaSQPdwFy2bxMtAS5B8xBZxPQH6qx7U1x+KZNrOlWHfWIfraHT/FzRD+ 0wTpVEKK0WQZKDn7GR4tyJb21+klvX26qWLbCK6RiSOhfDZUGAcQtgQGE9KNLYfTlHS4 O9q0SRUH3Bt7DmI5s45SqQZwSvncBWfMFBhbpu6W07/8wT+ovdllb/MAwyu65nCuwGcE hPaVGdF/R+eIIrLNkqCtYU19wIVDi7rN9NetdIBCKr+ufxGlQrL4vuOTlSKvWxaGYf+B DsrFX+WP68IOq1kzPgXsnhIvL875x5DnCz6Rgx2bi4kn5qYBxBvuV5RW3N9lRUqRIjV7 KR1Q== X-Gm-Message-State: APf1xPDchS0FMl4aM7+P+GHgh4bE2801uleQ8CBmQbICeOe3W4AwUUb7 G5MPc9SqC5yIjaroW2cXRkWHJNnMIdo= X-Received: by 10.98.228.3 with SMTP id r3mr901702pfh.77.1519887486360; Wed, 28 Feb 2018 22:58:06 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:05 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:19 +0800 Message-Id: <1519887444-75510-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 1/6] CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Ard Biesheuvel , Heyi Guo , Laszlo Ersek , Prince Agyeman MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Use ZeroMem to initialize all fields in temporary PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but helpful for future extension: when we add new fields to PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can safely be zero, this code will not suffer from an additional change. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Maurice Ma Cc: Prince Agyeman Cc: Benjamin You Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Ard Biesheuvel --- CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Ard Biesheuvel diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index 6d94ff72c956..c61609b79cce 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -319,6 +319,11 @@ ScanForRootBridges ( *NumberOfRootBridges = 0; RootBridges = NULL; + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + ZeroMem (&PMem, sizeof (PMem)); + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); // // After scanning all the PCI devices on the PCI root bridge's primary bus, From patchwork Thu Mar 1 06:57:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130110 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452324edc; Wed, 28 Feb 2018 22:58:11 -0800 (PST) X-Google-Smtp-Source: AG47ELta9Ta8ZxVJ0TAlr9rqEbwDXRKO8mQ8cHGC8pZp1Cp2gsse1ltlVNzoY1X25yXVrvf8J2vz X-Received: by 2002:a17:902:b7cc:: with SMTP id v12-v6mr935243plz.249.1519887491300; Wed, 28 Feb 2018 22:58:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887491; cv=none; d=google.com; s=arc-20160816; b=bAhUwHoCluqp0r8rc/W/L8Gbk+hykBDc76P5Al7agdE6IdmKLrrcm2Zte45WxzA8tQ 9Kl4XHnqmrzBk5t/QKH6Ot507DdY0yfI1odqUIC1okRcF6Yd8Z27W2331u7ktR+FO9yy 10qZ12SvInexdYd0lKfT+FNSuss9hsYtzYCz61jMKPTvy8gd+DUshHprmqEQGt8nD5Th 1BWcOrktwT70EevFP3kdb3179iWCkd9EoxMOOU2mCIOuktVo2q6nO4/pxvGvtWstBBPv Vxm6wd5JnQ+vKc01zVfuioxI04au5KdeBoDYDUUb895aaQZMZYt5PDQddJ4BDxt8Xx+8 vufA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=66gD7dCe1w4giWEnI/n+YfmkUrAANJol0htP5JuYe4w=; b=GsNRNrOeMC1QvxbLOCKitqkIqBvuF3xII0ZPX9ICjaicyeqoXT7C+4W1hnnjoFHU2q c2Syt7SWHmcDZgWZk/VtVbfQE6NQD0WmXnMFZHge8LH89/Y+3vqa8yiAaxpFtbPgE3P2 FolLgugl6odnx5crUkQWqQCl1eX9saWR14hq7ddi0w9n69vL2gex0IAotIzEP9h6jjll L0YbxgfVCNzrLCL3ZJA5xwJZWdebTmO8H9jrPEoPMnwkxQhnXcf2KNhJmDlDbkotpk2C 39/wzKphqVFsSedb8xFmprWyq/KJSQ2956+8L7NlgKwDTkAj+lVrVBvLz+WJ9fIoqAkc fM2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dO/KtnJB; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id t1si2082598pgv.668.2018.02.28.22.58.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dO/KtnJB; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 97C6322423853; Wed, 28 Feb 2018 22:52:02 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 669282242384D for ; Wed, 28 Feb 2018 22:52:01 -0800 (PST) Received: by mail-pf0-x244.google.com with SMTP id u5so2088003pfh.6 for ; Wed, 28 Feb 2018 22:58:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+l5P3SpoNzVI01jT5vur2BeNu3YylFW+/juKckuFnnk=; b=dO/KtnJBVCu7ze11YE11rbbETwxMSEgKRna1aCPfOCX82qtthEfdbHYy6W+r8+j4TV jXkAzhd8iE7BZdHR/Unjp9d6o6sv7BnpIoETIdTopYU7BDU1RI66mEwOhyCX5gx/2L/a U8Vxlmo7pwXVsv2l4Fk4wLQZ3YqmBmVwIR1pM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+l5P3SpoNzVI01jT5vur2BeNu3YylFW+/juKckuFnnk=; b=GIvDsctF3uarKOiMZqurZbHm6H41iuSalOLKKeQ3ZEO+5pBFcmxCWCXPjzkojSphix 31s5HveL40EE92jRo5mfA5y8ITWFap+9Mg1bFFHx4ecod33MCMkSanMo2zU/6Ndhlo91 rJNm6QcgMsbdej1NXHvHywydjXAJb0JbGREOUOeQh0TMerfF6nPdOybJvSw1mT/9HAsG B0ZnjDk/tp2rixeHGjJWRVLbD8fJYmR2CYe4hYhj6/2aS4pRS5VWSYJa+WyGft1a40nK 77yaIMEw4EwyokRBci/duvRNHF+YZvMLNN/eyRy5xArZj/00UJVcBvYvRH0CfjweEEWk W1hQ== X-Gm-Message-State: APf1xPBzF+S7xkLdSad8CRFIubbNpvhfie3hYXCNYXEtenK3pS27IzrD GN4H4yJTKBkNZ9EA34C77MVCLGdPKsA= X-Received: by 10.98.70.89 with SMTP id t86mr896406pfa.215.1519887489011; Wed, 28 Feb 2018 22:58:09 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:08 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:20 +0800 Message-Id: <1519887444-75510-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 2/6] OvmfPkg/PciHostBridgeLib: Init PCI aperture to 0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Ard Biesheuvel , Jordan Justen , Heyi Guo , Anthony Perard , Laszlo Ersek MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Use ZeroMem to initialize all fields in temporary PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but is helpful for future extension: when we add new fields to PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can safely be zero, this code will not suffer from an additional change. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Jordan Justen Cc: Anthony Perard Cc: Julien Grall Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Ard Biesheuvel --- OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 ++++ OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 5 +++++ 2 files changed, 9 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index ff837035caff..4a650a4c6df9 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -217,6 +217,10 @@ PciHostBridgeGetRootBridges ( PCI_ROOT_BRIDGE_APERTURE Mem; PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + if (PcdGetBool (PcdPciDisableBusEnumeration)) { return ScanForRootBridges (Count); } diff --git a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c index 31c63ae19e0a..aaf101dfcb0e 100644 --- a/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c +++ b/OvmfPkg/Library/PciHostBridgeLib/XenSupport.c @@ -193,6 +193,11 @@ ScanForRootBridges ( *NumberOfRootBridges = 0; RootBridges = NULL; + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + ZeroMem (&PMem, sizeof (PMem)); + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); // // After scanning all the PCI devices on the PCI root bridge's primary bus, From patchwork Thu Mar 1 06:57:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130111 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452365edc; Wed, 28 Feb 2018 22:58:13 -0800 (PST) X-Google-Smtp-Source: AG47ELvZuVqHJMXSUREoWvogsxJ162RL9av4CgoKnJtZbiUb9B+6HiwOaBE8TQVlAMrEO8OTuhN5 X-Received: by 2002:a17:902:4301:: with SMTP id i1-v6mr376867pld.227.1519887493715; Wed, 28 Feb 2018 22:58:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887493; cv=none; d=google.com; s=arc-20160816; b=gwSSSJB45Y8mrpAGAUsTmE+VRNlHKfvUvArD+tUDCQMjYBsear2JNxnPrnCtC5pcC/ iedorJWflrQ/nCf2sdix62UgIzJLqN7y/CQjY6mF6O1WkrCIu/ZqTDJftbKP6WWIpT/K 1Zyc16aTTm35r0zz4fI4xIdmfEN5vx1x7n7uN/ayIGj6qtAUVo+ojz//Y0FeTmmYO0pS TzIqfS/YiFfA13OcgEmWEP3J5eq9Fc58iYo5Xqe6dAdYTjZzG5wrlJlAa+h7zY94vDS9 SvK51RmDMJtz/vYuVz9mi4fs/GQ5L+ScOUx6YLnQ8PYyQD0J83j5IEwIK7PRihElZwsh hgIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=fFeUJGovordShiH9sgOxWCZLg0cQQLXqEjk3EivqNik=; b=VJ1Qsk0Shhm5UhVY/SazJopMioezr95FJUvtJ7sM7/ZzN6jxd3QQIbCPXx2FW6GHle NVS/nEjr7/FQ9WAKgvkRcfitNwvEnulhI+yazvf7WMc3o+T2z6ViFo7Cllrhl6HL7Whj qAz9/6QmI9GgQTqqcSPpXmVITmkChBPfTHP07Drw4A6UnD1N2vQV8Bu5GU/70QxHwmh1 r/Om02H0UHKeLAPRSC4tUFjJFPM6LceTOxYkeU3CfkwjmQhEWvVLPeNn+5bpRlM++uZU 2Qxz36r0iM4yu56rMs51k9svTr9UwZMZrJkVWjxW/F+qNM30W5g122uzu1zVL/6+P+AM i+6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Yn2WaFMl; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id f1si1693409pgr.761.2018.02.28.22.58.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Yn2WaFMl; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EE4B42242385B; Wed, 28 Feb 2018 22:52:04 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x243.google.com (mail-pf0-x243.google.com [IPv6:2607:f8b0:400e:c00::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CB3DD22423858 for ; Wed, 28 Feb 2018 22:52:02 -0800 (PST) Received: by mail-pf0-x243.google.com with SMTP id a16so2083481pfn.9 for ; Wed, 28 Feb 2018 22:58:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3GDIjan80cUAO1zWBjouETK+quCYmkK8qXQ6hlijggY=; b=Yn2WaFMlUIauQuGaa+wFWZffxZYVooPRh43kc+86tA36kXQEyup/w7rPM9eeQBIYW7 xq62fCzc8d35EngHMKFGWF/ZnK8+vIGIqiyOZW7tXvNhYpWxqG/icVRIGDwigjAYuQyb F8u8hh6y29FIlJ9Q4Reg5YsXNeFP2bdT1pyiY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3GDIjan80cUAO1zWBjouETK+quCYmkK8qXQ6hlijggY=; b=htiXZIbxzUldANqxuvjs2L+Xa4LBoWx5aQnoxbpgBpa+ObUpHv1jqkH5RZuvrnlkOB sEdXq0NuGwQX8Wxw9ezBpRhbdgxvlft5Kywx4HgV9p0pNgA0bpa8m16vSQrptuVeinTd byiYEcdAtKGHx8vKESz3sm2Uwmur0y/VQasLJJ7tMP6HuYLWp0DCyPD4dWrv96SS9dFv 93Jq7HbOEyfeqcSxXOAP4o9jVcLCSteRRhuH8Jrt/wCaoz+pe1ZOnMDZVdNEncU5kZQZ MWAWkMN6Y5uZmRQtXE9dxXCxgJo0zHHm0xjguJzmxoxA7GwppFr9zN5qOaxxFNznGxtD nEgg== X-Gm-Message-State: APf1xPBUakJrGKs3qe2Vteh2t6Z2+NcOX+8QR6k6lfFYSsP4SPl7wUyM eoWwJcLQX4HsvIEjcSKhH2f6na00TDw= X-Received: by 10.98.219.129 with SMTP id f123mr901934pfg.195.1519887490479; Wed, 28 Feb 2018 22:58:10 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:10 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:21 +0800 Message-Id: <1519887444-75510-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 3/6] MdeModulePkg/PciHostBridgeLib.h: add address Translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heyi Guo MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add Translation field to PCI_ROOT_BRIDGE_APERTURE. Translation is used to represent the difference between device address and host address, if they are not the same on some platforms. In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the Starting address to convert it to a PCI address". This means: Translation = device address - host address So we also use the above calculation for this Translation field to keep consistent. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo --- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h index d42e9ecdd763..18963a0d3821 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -20,8 +20,27 @@ // (Base > Limit) indicates an aperture is not available. // typedef struct { + // + // Base and Limit are the device address instead of host address when + // Translation is not zero + // UINT64 Base; UINT64 Limit; + // + // According to UEFI 2.7, Device Address = Host Address + Translation, + // so Translation = Device Address - Host Address. + // On platforms where Translation is not zero, the subtraction is probably to + // be performed with UINT64 wrap-around semantics, for we may translate an + // above-4G host address into a below-4G device address for legacy PCIe device + // compatibility. + // + // NOTE: The alignment of Translation is required to be larger than any BAR + // alignment in the same root bridge, so that the same alignment can be + // applied to both device address and host address, which simplifies the + // situation and makes the current resource allocation code in generic PCI + // host bridge driver still work. + // + UINT64 Translation; } PCI_ROOT_BRIDGE_APERTURE; typedef struct { From patchwork Thu Mar 1 06:57:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130112 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452394edc; Wed, 28 Feb 2018 22:58:16 -0800 (PST) X-Google-Smtp-Source: AG47ELs4O/kWVm4zItTsM04EyYN4oxtL2syc+KjSnh1J1BLBGGe3aD37wtzb3OQxKE/WMrPx8sRb X-Received: by 2002:a17:902:b7c1:: with SMTP id v1-v6mr935607plz.315.1519887496068; Wed, 28 Feb 2018 22:58:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887496; cv=none; d=google.com; s=arc-20160816; b=0m4Z/1Fh11a6AcjzusIQZutAtiN6q6MpaGg0sN3LnTjQyI/lSbOZd2ygFqfCS12TPk Mh0YM5va3GlAExVX71i2JJbFM1zqpyKSZTSmj3nerhe+BfP0eo2yHCLhA/i+fAIKMLhu +18XfrqgbFHs/t8RP9KN1zoocOyTdKnApjapEi3QfodHvaym8hldKTqak0Fm0EXguc5K wb17rczy5AsZpAmrmn1aLTd6NGyhBqcIE6BeSv0KwWYMJbLSMAJRYEd41+BqYUBzhctC ww7uF5ov8kYHEuEMNhD54TagnAUJaSN5L4bAX4h6uq9x9fkdEAOUqlSqkzCrFxtN+ey1 3oWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=fYzc+roUTfYYoPUhE4QTspoVAbRPBe9eRFJ1NPVnXZw=; b=fDArmAXJlxuFDDhbH517KSUPa56u51m3WWwvhPQ64nuof7qkbKrGwcRi1HrZEl9jHg HCSsZa2pOxwx5HGyJLp2enTfwXGmmsfPSVNOqI+9T0BPBuuLB50OwN/yl4veRA1yS4aW QAEqRDFo6X4x0CCqIkJOuu33501k4MHyS+IofB1045v+Do1VojNTRN0n5p7qVvWb+c/T O6Y1H7Nt0ME5v5jkbVunoF1j+LJ/OrUh2goAHZebsnpmIx9ZyULFwuRmZ0p0OjxjqKP6 YAVdEQ8F6sJkXFyCSR6dpDKX+Nk+Tqlf2f6TLyJ/oDL0ecYj0L+DFtvNU9aelRXxFkvs 6vVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=H7iEekCW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id s87si2507142pfj.396.2018.02.28.22.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=H7iEekCW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5C6B62242385A; Wed, 28 Feb 2018 22:52:07 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9308322423858 for ; Wed, 28 Feb 2018 22:52:05 -0800 (PST) Received: by mail-pf0-x244.google.com with SMTP id z10so2076230pfh.13 for ; Wed, 28 Feb 2018 22:58:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wGXO0mzCbQcpJPjJx5XiE5mFEURMgmtnrY+sWYQYImU=; b=H7iEekCWTy8bxCKfKH4P1xVi5tR8hjjvr319IQxQ6enmRUhkO0cgwlOLvuSkKAmBQh aa75u8j9Zv6vD7aSMGqj3R9Q22QP3LuNxBEKzO5urb5IZo5U0q//o5YZoFQYbHrPXBtD +ZkzSzhFFyQzkM8TYbK9/hTYvAHOOV4qS7kiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wGXO0mzCbQcpJPjJx5XiE5mFEURMgmtnrY+sWYQYImU=; b=E9UmDwl6onXz8v3s55ibiUwQ/Kb40ZNBB9VXnpTZldcd+gG05zwk3gp2EIf4kAfzEt 2tR6GTXKy6Vg20smc7aC2GKegxytHUGjclAzet+T7qXPYoZwLzKbowow/wRg0FKYHWhM ar+KMWPeLZg0h4bS7TR3ZCrnRcGPM5OrtsSWzTGm8QJ1jfG2XrKQ2i5ozcJQ/xC86XNW zye8aEM/P3IU0GC1K/oka3QTkMChGXSlNvBY89dTCbuTkuiz8C/nyPOGmqbPR2ogR6mA 03KtMt3KlKaq+1QxwwMo46rdFFYNUjlczo6h5Nv+7IwvIXLQPMwwLgk2Khmj380l044o dksQ== X-Gm-Message-State: APf1xPBt8k9d30c/V900HE/NRDpEzL9VSHGeuuPiMIU59/WO8gx0drX2 X/cabJKNvCiTqfmo6um1OjVmnoPq6Os= X-Received: by 10.98.86.151 with SMTP id h23mr893389pfj.79.1519887493122; Wed, 28 Feb 2018 22:58:13 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:12 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:22 +0800 Message-Id: <1519887444-75510-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 4/6] MdeModulePkg/PciHostBridgeDxe: Add support for address translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PCI address translation is necessary for some non-x86 platforms. On such platforms, address value (denoted as "device address" or "address in PCI view") set to PCI BAR registers in configuration space might be different from the address which is used by CPU to access the registers in memory BAR or IO BAR spaces (denoted as "host address" or "address in CPU view"). The difference between the two addresses is called "Address Translation Offset" or simply "translation", and can be represented by "Address Translation Offset" in ACPI QWORD Address Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the definitions of QWORD Address Space Descriptor, and we will follow UEFI definition on UEFI protocols, such as PCI root bridge IO protocol and PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the Starting address to convert it to a PCI address". This means: 1. Translation = device address - host address. 2. PciRootBridgeIo->Configuration should return CPU view address, as well as PciIo->GetBarAttributes. Summary of addresses used in protocol interfaces and internal implementations: 1. *Only* the following protocol interfaces assume Address is Device Address: (1). PciHostBridgeResourceAllocation.GetProposedResources() Otherwise PCI bus driver cannot set correct address into PCI BARs. (2). PciRootBridgeIo.Mem.Read() and PciRootBridgeIo.Mem.Write() (3). PciRootBridgeIo.CopyMem() UEFI and PI spec have clear statements for all other protocol interfaces about the address type. 2. Library interfaces and internal implementation: (1). Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. It is easy to check whether the address is below 4G or above 4G. (2). Addresses in PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode are host address, for they are allocated from GCD. (3). Address passed to PciHostBridgeResourceConflict is host address, for it comes from PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode. RESTRICTION: to simplify the situation, we require the alignment of Translation must be larger than any BAR alignment in the same root bridge, so that resource allocation alignment can be applied to both device address and host address. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- Notes: v5: - Add check for the alignment of Translation against the BAR alignment [Ray] - Keep coding style of comments consistent with the context [Ray] - Comment change for Base in PCI_RES_NODE [Ray] - Add macros of TO_HOST_ADDRESS and TO_DEVICE_ADDRESS for address type conversion (After that we can also simply the comments about the calculation [Ray] - Add check for bus translation offset in CreateRootBridge(), making sure it is zero, and unify code logic for all types of resource after that [Ray] - Use GetTranslationByResourceType() to simplify the code in RootBridgeIoConfiguration() (also fix a bug in previous patch version of missing a break after case TypePMem64) [Ray] - Commit message refinement [Ray] v4: - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType [Laszlo] - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and gDS->AllocateMemorySpace [Laszlo] - Add comment for applying alignment to both device address and host address, and add NOTE for the alignment requirement of Translation, as well as in commit message [Laszlo][Ray] - Improve indention for the code in CreateRootBridge [Laszlo] - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE definition [Laszlo] - Ignore translation of bus in CreateRootBridge v4: - Add ASSERT (FALSE) to default branch in GetTranslationByResourceType [Laszlo] - Fix bug when passing BaseAddress to gDS->AllocateIoSpace and gDS->AllocateMemorySpace [Laszlo] - Add comment for applying alignment to both device address and host address, and add NOTE for the alignment requirement of Translation, as well as in commit message [Laszlo][Ray] - Improve indention for the code in CreateRootBridge [Laszlo] - Improve comment for Translation in PCI_ROOT_BRIDGE_APERTURE definition [Laszlo] - Ignore translation of bus in CreateRootBridge MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 21 ++++ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 3 + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 129 +++++++++++++++++--- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 118 ++++++++++++++++-- 4 files changed, 245 insertions(+), 26 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Ruiyu Ni diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h index 9a8ca21f4819..c2791ea5c2a4 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h @@ -38,6 +38,13 @@ typedef struct { #define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) // +// Macros to translate device address to host address and vice versa. According +// to UEFI 2.7, device address = host address + translation offset. +// +#define TO_HOST_ADDRESS(DeviceAddress,TranslationOffset) ((DeviceAddress) - (TranslationOffset)) +#define TO_DEVICE_ADDRESS(HostAddress,TranslationOffset) ((HostAddress) + (TranslationOffset)) + +// // Driver Entry Point // /** @@ -247,6 +254,20 @@ ResourceConflict ( IN PCI_HOST_BRIDGE_INSTANCE *HostBridge ); +/** + This routine gets translation offset from a root bridge instance by resource type. + + @param RootBridge The Root Bridge Instance for the resources. + @param ResourceType The Resource Type of the translation offset. + + @retval The Translation Offset of the specified resource. +**/ +UINT64 +GetTranslationByResourceType ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN PCI_RESOURCE_TYPE ResourceType + ); + extern EFI_METRONOME_ARCH_PROTOCOL *mMetronome; extern EFI_CPU_IO2_PROTOCOL *mCpuIo; #endif diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h index 8612c0c3251b..a6c3739db368 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h @@ -38,6 +38,9 @@ typedef enum { typedef struct { PCI_RESOURCE_TYPE Type; + // + // Base is a host address + // UINT64 Base; UINT64 Length; UINT64 Alignment; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 1494848c3e8c..42ded2855c71 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -33,6 +33,39 @@ EFI_EVENT mIoMmuEvent; VOID *mIoMmuRegistration; /** + This routine gets translation offset from a root bridge instance by resource type. + + @param RootBridge The Root Bridge Instance for the resources. + @param ResourceType The Resource Type of the translation offset. + + @retval The Translation Offset of the specified resource. +**/ +UINT64 +GetTranslationByResourceType ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN PCI_RESOURCE_TYPE ResourceType + ) +{ + switch (ResourceType) { + case TypeIo: + return RootBridge->Io.Translation; + case TypeMem32: + return RootBridge->Mem.Translation; + case TypePMem32: + return RootBridge->PMem.Translation; + case TypeMem64: + return RootBridge->MemAbove4G.Translation; + case TypePMem64: + return RootBridge->PMemAbove4G.Translation; + case TypeBus: + return RootBridge->Bus.Translation; + default: + ASSERT (FALSE); + return 0; + } +} + +/** Ensure the compatibility of an IO space descriptor with the IO aperture. The IO space descriptor can come from the GCD IO space map, or it can @@ -366,6 +399,7 @@ InitializePciHostBridge ( UINTN MemApertureIndex; BOOLEAN ResourceAssigned; LIST_ENTRY *Link; + UINT64 HostAddress; RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount); if ((RootBridges == NULL) || (RootBridgeCount == 0)) { @@ -411,8 +445,15 @@ InitializePciHostBridge ( } if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) { + // + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // For GCD resource manipulation, we need to use host address. + // + HostAddress = TO_HOST_ADDRESS (RootBridges[Index].Io.Base, + RootBridges[Index].Io.Translation); + Status = AddIoSpace ( - RootBridges[Index].Io.Base, + HostAddress, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1 ); ASSERT_EFI_ERROR (Status); @@ -422,7 +463,7 @@ InitializePciHostBridge ( EfiGcdIoTypeIo, 0, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1, - &RootBridges[Index].Io.Base, + &HostAddress, gImageHandle, NULL ); @@ -443,14 +484,20 @@ InitializePciHostBridge ( for (MemApertureIndex = 0; MemApertureIndex < ARRAY_SIZE (MemApertures); MemApertureIndex++) { if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) { + // + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // For GCD resource manipulation, we need to use host address. + // + HostAddress = TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Translation); Status = AddMemoryMappedIoSpace ( - MemApertures[MemApertureIndex]->Base, + HostAddress, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); ASSERT_EFI_ERROR (Status); Status = gDS->SetMemorySpaceAttributes ( - MemApertures[MemApertureIndex]->Base, + HostAddress, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); @@ -463,7 +510,7 @@ InitializePciHostBridge ( EfiGcdMemoryTypeMemoryMappedIo, 0, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, - &MemApertures[MemApertureIndex]->Base, + &HostAddress, gImageHandle, NULL ); @@ -654,6 +701,11 @@ AllocateResource ( if (BaseAddress < Limit) { // // Have to make sure Aligment is handled since we are doing direct address allocation + // Strictly speaking, alignment requirement should be applied to device + // address instead of host address which is used in GCD manipulation below, + // but as we restrict the alignment of Translation to be larger than any BAR + // alignment in the root bridge, we can simplify the situation and consider + // the same alignment requirement is also applied to host address. // BaseAddress = ALIGN_VALUE (BaseAddress, LShiftU64 (1, BitsOfAlignment)); @@ -721,6 +773,7 @@ NotifyPhase ( PCI_RESOURCE_TYPE Index2; BOOLEAN ResNodeHandled[TypeMax]; UINT64 MaxAlignment; + UINT64 Translation; HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This); @@ -822,14 +875,43 @@ NotifyPhase ( BitsOfAlignment = LowBitSet64 (Alignment + 1); BaseAddress = MAX_UINT64; + // + // RESTRICTION: To simplify the situation, we require the alignment of + // Translation must be larger than any BAR alignment in the same root + // bridge, so that resource allocation alignment can be applied to + // both device address and host address. + // + Translation = GetTranslationByResourceType (RootBridge, Index); + if ((Translation & Alignment) != 0) { + DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned to %lx!\n", + __FUNCTION__, __LINE__, Translation, Alignment + )); + ASSERT (FALSE); + // + // This may be caused by too large alignment or too small + // Translation; pick the 1st possibility and return out of resource, + // which can also go thru the same process for out of resource + // outside the loop. + // + ReturnStatus = EFI_OUT_OF_RESOURCES; + continue; + } + switch (Index) { case TypeIo: + // + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // For AllocateResource is manipulating GCD resource, we need to use + // host address here. + // BaseAddress = AllocateResource ( FALSE, RootBridge->ResAllocNode[Index].Length, MIN (15, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1), - RootBridge->Io.Limit + TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1), + RootBridge->Io.Translation), + TO_HOST_ADDRESS (RootBridge->Io.Limit, + RootBridge->Io.Translation) ); break; @@ -838,8 +920,10 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1), - RootBridge->MemAbove4G.Limit + TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1), + RootBridge->MemAbove4G.Translation), + TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit, + RootBridge->MemAbove4G.Translation) ); if (BaseAddress != MAX_UINT64) { break; @@ -853,8 +937,10 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1), - RootBridge->Mem.Limit + TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1), + RootBridge->Mem.Translation), + TO_HOST_ADDRESS (RootBridge->Mem.Limit, + RootBridge->Mem.Translation) ); break; @@ -863,8 +949,10 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1), - RootBridge->PMemAbove4G.Limit + TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1), + RootBridge->PMemAbove4G.Translation), + TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit, + RootBridge->PMemAbove4G.Translation) ); if (BaseAddress != MAX_UINT64) { break; @@ -877,8 +965,10 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1), - RootBridge->PMem.Limit + TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1), + RootBridge->PMem.Translation), + TO_HOST_ADDRESS (RootBridge->PMem.Limit, + RootBridge->PMem.Translation) ); break; @@ -1421,7 +1511,14 @@ GetProposedResources ( Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;; Descriptor->GenFlag = 0; - Descriptor->AddrRangeMin = RootBridge->ResAllocNode[Index].Base; + // + // AddrRangeMin in Resource Descriptor here should be device address + // instead of host address, or else PCI bus driver cannot set correct + // address into PCI BAR registers. + // Base in ResAllocNode is a host address, so conversion is needed. + // + Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (RootBridge->ResAllocNode[Index].Base, + GetTranslationByResourceType (RootBridge, Index)); Descriptor->AddrRangeMax = 0; Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS; Descriptor->AddrLen = RootBridge->ResAllocNode[Index].Length; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dc06c16dc038..5dd9d257d46d 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -86,12 +86,35 @@ CreateRootBridge ( (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"", (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L"" )); + // + // Translation for bus is not supported. + // DEBUG ((EFI_D_INFO, " Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit)); - DEBUG ((EFI_D_INFO, " Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit)); - DEBUG ((EFI_D_INFO, " Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit)); - DEBUG ((EFI_D_INFO, " MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit)); - DEBUG ((EFI_D_INFO, " PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit)); - DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit)); + ASSERT (Bridge->Bus.Translation == 0); + if (Bridge->Bus.Translation != 0) { + return NULL; + } + + DEBUG (( + DEBUG_INFO, " Io: %lx - %lx Translation=%lx\n", + Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation + )); + DEBUG (( + DEBUG_INFO, " Mem: %lx - %lx Translation=%lx\n", + Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation + )); + DEBUG (( + DEBUG_INFO, " MemAbove4G: %lx - %lx Translation=%lx\n", + Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation + )); + DEBUG (( + DEBUG_INFO, " PMem: %lx - %lx Translation=%lx\n", + Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation + )); + DEBUG (( + DEBUG_INFO, " PMemAbove4G: %lx - %lx Translation=%lx\n", + Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation + )); // // Make sure Mem and MemAbove4G apertures are valid @@ -206,7 +229,12 @@ CreateRootBridge ( } RootBridge->ResAllocNode[Index].Type = Index; if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) { - RootBridge->ResAllocNode[Index].Base = Aperture->Base; + // + // Base in ResAllocNode is a host address, while Base in Aperture is a + // device address. + // + RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (Aperture->Base, + Aperture->Translation); RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1; RootBridge->ResAllocNode[Index].Status = ResAllocated; } else { @@ -403,6 +431,28 @@ RootBridgeIoCheckParameter ( return EFI_SUCCESS; } +EFI_STATUS +RootBridgeIoGetMemTranslationByAddress ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN UINT64 Address, + IN OUT UINT64 *Translation + ) +{ + if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) { + *Translation = RootBridge->Mem.Translation; + } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) { + *Translation = RootBridge->PMem.Translation; + } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) { + *Translation = RootBridge->MemAbove4G.Translation; + } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) { + *Translation = RootBridge->PMemAbove4G.Translation; + } else { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + /** Polls an address in memory mapped I/O space until an exit condition is met, or a timeout occurs. @@ -658,13 +708,25 @@ RootBridgeIoMemRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Read needs to be a host address instead of + // device address. + return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + TO_HOST_ADDRESS (Address, Translation), Count, Buffer); } /** @@ -705,13 +767,25 @@ RootBridgeIoMemWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Write needs to be a host address instead of + // device address. + return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + TO_HOST_ADDRESS (Address, Translation), Count, Buffer); } /** @@ -746,6 +820,8 @@ RootBridgeIoIoRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -753,7 +829,13 @@ RootBridgeIoIoRead ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Read needs to be a host address instead of + // device address. + return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer); } /** @@ -788,6 +870,8 @@ RootBridgeIoIoWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -795,7 +879,13 @@ RootBridgeIoIoWrite ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Write needs to be a host address instead of + // device address. + return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer); } /** @@ -1615,9 +1705,17 @@ RootBridgeIoConfiguration ( Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + // According to UEFI 2.7, RootBridgeIo->Configuration should return address + // range in CPU view (host address), and ResAllocNode->Base is already a CPU + // view address (host address). Descriptor->AddrRangeMin = ResAllocNode->Base; Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; Descriptor->AddrLen = ResAllocNode->Length; + Descriptor->AddrTranslationOffset = GetTranslationByResourceType ( + RootBridge, + ResAllocNode->Type + ); + switch (ResAllocNode->Type) { case TypeIo: From patchwork Thu Mar 1 06:57:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130113 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452426edc; Wed, 28 Feb 2018 22:58:18 -0800 (PST) X-Google-Smtp-Source: AG47ELuejmXWRY/h9KIdr4bQ4Ez6LgkGWxlWmBMiAmlJ+U/o9ZTCdOngMJ2l+6IT1RTJmQ8QBlnM X-Received: by 10.99.117.76 with SMTP id f12mr753564pgn.410.1519887498445; Wed, 28 Feb 2018 22:58:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887498; cv=none; d=google.com; s=arc-20160816; b=R6M/oMRzzUBM9k0YIkJuGeavae2Mg7JeCsVFpCLqW9a7qyIge1XDmv6p8XbedN31NG GQYDtjTSFYe6++gp3Fz1nYEUwdDWF2fvCIo3PeKPbHe31oKv5nb8MK8cTKlNPKMkg7g1 oYslK9DwXy83H2cn7u4yRfZnhhg2DsJZK13qjsfwUyVTYQhPZ6PLej1SOdH2STLifN/H oLzca4cbIlkczNwOxEKUai+6AtU4AZXi4byqaD5wYtA0SRtCVPXhu5v73Rf5yIJNxUoX RRhGcdumlTtu9AcWCryv3Oh/McvXeqlg5Dn6+C1jERlmi2N/oYLOQnOEkg3x87lZIuy2 Tlmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=UDNdoFR4SAy+V/us9MtJt2m1KC6lQkSITkNyl/kAPmc=; b=rB7D9kcJkxQnqgLktUxBWc9NcF5wh573h0soa9oZvW38Ste9AkOUdMu1mVvi51baYp MWvcyI5tN1qR+bm9nbi7sys0OlBSz96QTxjXsRKS/uxI/60Wc9U7wdl8CjM7suWUbGNh 6hBAatdMd82MAB7GTPu6bByBcrbQHqIVM+sncr8kambnFyRJJeCia/bcjZsctp90itiz Iksswb6BMtXRE6Rdl8sflEukRVw97HMXnW3qsM5oazvUYlRC4dltN4w6IRduUjlZWW0q 94Q04DCWKDS4wRBsfVtmU//IBB0E3fBozemZNeR031UM0gY/WJ/wBht05H5UkQylPPCS Xyow== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aaPDSb9i; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t28si1271896pfk.309.2018.02.28.22.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aaPDSb9i; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BD4E22034D8E3; Wed, 28 Feb 2018 22:52:09 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7CB332242384D for ; Wed, 28 Feb 2018 22:52:08 -0800 (PST) Received: by mail-pl0-x242.google.com with SMTP id 93-v6so3127957plc.9 for ; Wed, 28 Feb 2018 22:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AYSvTpkKH3HkKndCwIKm4x8MwR03fLPgznyqaVdDMa8=; b=aaPDSb9iNRBZGRVw9Tl6EWkzr/pSosfiiv04t850nnMzRzL6NOCgIVPCR36xnXMf4d WSuJ8Vo4zCXS4jXO5n/3xRl53CgYmte47zlA4InVIWKC++SL+7WYnYaAEngjoEtXYLfV KNkvKF/VcCswgYpOiSfhcW8sY/ZZ5Q5FK0oR0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AYSvTpkKH3HkKndCwIKm4x8MwR03fLPgznyqaVdDMa8=; b=BbmxM6lxN8B7+/00OWV/TGNgHYPLaTQDTPKpEQkbRIe3A3B1zqCU9mtIsyn0qU6TDx 8XUT0IPQhjdqKI4FjT+/nI61dZJmoh7+WcYb2Zj4K0GBgFlVr/gw2Ir2ooxEXXhP0BXY iM0bIBMMOSV8oJUb53u9SnUySPv8SVU9tQAhHVziWGuSNPE1DXUirkf70SS0i/gx96tO k3zGmmVKg+gUrAW4k8gJeqaPGkDkAG/UNvoHqMUpQ/LC0RsLdr8saRtUBIflwV20sXLb yVcmjJiSg3ZDfWGhCm/8QwG3zPltYBZtn67ZVH9+rZD32EfGWV87LRvNiVq+w0y1ApTW 0pxw== X-Gm-Message-State: APf1xPCKWadWY9Ed/NVehbfyOfU32TRNmltdVPXUXcSPvjEnE/mPXu+M DLHvqr0KHcv9PlCRgXvY6Fq2CjUNuGo= X-Received: by 2002:a17:902:518d:: with SMTP id y13-v6mr955163plh.121.1519887496119; Wed, 28 Feb 2018 22:58:16 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:15 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:23 +0800 Message-Id: <1519887444-75510-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 5/6] MdeModulePkg/PciBus: convert host address to device address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" According to UEFI spec 2.7, PciRootBridgeIo->Configuration() should return host address (CPU view ddress) rather than device address (PCI view address), so in function GetMmioAddressTranslationOffset we need to convert the range to device address before comparing. And device address = host address + translation offset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c index 190f4b0dc7ed..fef3eceb7f62 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset ( return (UINT64) -1; } + // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration() + // returns host address instead of device address, while AddrTranslationOffset + // is not zero, and device address = host address + AddrTranslationOffset, so + // we convert host address to device address for range compare. while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) && - (Configuration->AddrRangeMin <= AddrRangeMin) && - (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen) + (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) && + (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen) ) { return Configuration->AddrTranslationOffset; } From patchwork Thu Mar 1 06:57:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 130114 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2452465edc; Wed, 28 Feb 2018 22:58:21 -0800 (PST) X-Google-Smtp-Source: AG47ELvxRfuD3w3xYEZ4nBIfeOUUEuUJKaAtHdW73kFu9mT5XOfPKNbGv1A0oeKdNBtZ0QJ/Gm9R X-Received: by 2002:a17:902:6c41:: with SMTP id h1-v6mr935137pln.25.1519887500994; Wed, 28 Feb 2018 22:58:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519887500; cv=none; d=google.com; s=arc-20160816; b=GCIoL6jjcEinh7i04b8JN+12A2Kuf6OFjh4ag3uF7NXYDBGeVaHJunucFXsahlSNI0 wTx89BcoD5qqcWL2V/IyqvycKiBH/0DCq7cqsOBHbSVQhxJ5FFgLd5xD5YDISIyqSCWQ F6b6dKFKnL1zxKj6vmnhlWT2zbtaUBaVgyHybKU2gjONaqHl37l6bBfxhKyjT/4Bx9ZT HKH7BCKAk5fOzLQVCAZnvnXP8dhacjKyZu/RwXytZ672DHX+K/Iull232KSXbPizUvcr VV1IKiBzoP4LTUmX08pYm5XAOvJ8p5a9HPnUOfVUqGqrD33SenzN0jYnWrMIPiRpNNFf a3Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=0iPwGD9JQnn0B0UAzD0LuG74bkPk98YIgY5wXyApgpo=; b=qjyKc0zxm5X1qCgmzIx1Cz2uj3+LOzy8rzytS0MBeK78udEXMs7CaiR+84zU/cN25Y du/V04DbokNINt32VBeCgC1T+hNKrdpSxVcVZ07gJqskF+PrSL/8IHVXv+AKRo/yNOvT K14TGIVVEpVAvsZuZXb7WmKs4fsQ25W5uo0CkDxfzVKgrMQ8wTMwrGfeYRyYIaUFRrFh +tVGto6tqJ2I7kAFsWo8x4KTzD3cY5unwxFGMeVYELBxHKOoXJ+/QD5TwfxaXYas+8Vf 6vN+aPAdKKENA21ZpE6GOFcRIGQeSTsMDWz3yHhjbcKDGCDBXTx3NSXZXnxev4i/S/t1 b0fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=C0Z7fC2l; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 21si2548867pfj.306.2018.02.28.22.58.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 22:58:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=C0Z7fC2l; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2BEFC2034D8F8; Wed, 28 Feb 2018 22:52:12 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BFA692242384D for ; Wed, 28 Feb 2018 22:52:10 -0800 (PST) Received: by mail-pl0-x242.google.com with SMTP id c11-v6so3152165plo.0 for ; Wed, 28 Feb 2018 22:58:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KY/TY1vQXahnUmVIDRxMzVNKvNFaI0EiawWm+wlL7A4=; b=C0Z7fC2lCygcR8cvpPcq0bUD4ZmjjeZr0xha3Cs/Qun/jdFt+mLavFHZISVjL3whhB JYCobcH3faygDsS2RnmUO1GYnIxN9fflqvJdU5oDOfcUJkrn91DI7ED+FQUF/08KxT3K Mydy9d6g6AIKpGxoxSSI4coAYc2U3B5ZjvDFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KY/TY1vQXahnUmVIDRxMzVNKvNFaI0EiawWm+wlL7A4=; b=TDII5gcmMVz4NNKHzX3Co492OtD86rPL7KsHgA7dAZd03QJaIJ/zCDwNs4lgqzRjLG MHnGoDzxVF2ka2qv2J+v9O3zkKn44w8S5c/3uD0QGNBr53PTCPOhLc1qGuhD0ZgLiXvE AECU+34FGJ3jblf1C/5IWgPUGjzjLB+qHKvgNWVvd816Qu9+rwYkF/Oem9KH1YVlu4IN +7bK3xWDI0cgWJtKxgky2yo53mr6K0BW8BB6R0ra2x7x1AMbwBThSAkpn5zXClIUcieU js8jadNEs3RIZKzTCl7FeAMOXF3ufprHu7PbtknIexvvtx49+57KRk00UTqcah+phO0E nbbg== X-Gm-Message-State: APf1xPDQvdf2pnZaDHrBxP6Gw49LbIVmwOS6mBPpnIQwD/aDCjtg6Ydr JxlAM+TpW2P2fprtekLyxeKIuiJRR00= X-Received: by 2002:a17:902:5596:: with SMTP id g22-v6mr942437pli.4.1519887498609; Wed, 28 Feb 2018 22:58:18 -0800 (PST) Received: from localhost.localdomain ([45.56.152.115]) by smtp.gmail.com with ESMTPSA id p63sm6489867pfk.74.2018.02.28.22.58.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 22:58:18 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:57:24 +0800 Message-Id: <1519887444-75510-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH v5 6/6] MdeModulePkg/PciBus: return CPU address for GetBarAttributes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" According to UEFI spec 2.7, PciIo->GetBarAttributes should return host address (CPU view ddress) rather than device address (PCI view address), and device address = host address + address translation offset, so we subtract translation from device address before returning. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c index fef3eceb7f62..62179eb44bbd 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1972,6 +1972,10 @@ PciIoGetBarAttributes ( return EFI_UNSUPPORTED; } } + + // According to UEFI spec 2.7, we need return host address for + // PciIo->GetBarAttributes, and host address = device address - translation. + Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset; } return EFI_SUCCESS;