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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id p9sm4123698pgs.89.2018.02.28.08.48.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:48:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 08:48:13 -0800 Message-Id: <20180228164816.24110-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org> References: <20180228164816.24110-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [RISU 1/3] Add aa64 sqrdml[as]h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- aarch64.risu | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.14.3 diff --git a/aarch64.risu b/aarch64.risu index 02e9183..c1a29f6 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2932,6 +2932,30 @@ FCVTZUsi A64_V sf:1 0011110 type:2 1 11 001 000000 rn:5 rd:5 \ # UnallocatedEncoding: type >= 2 FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5 +# +# AdvSIMD v8.1 extensions +# + +@v8_1_simd + +# SQRDMLAH (vector, scalar) +SQRDMLAHvs A64_V81 01111110 size:2 0 rm:5 100001 rn:5 rd:5 +# SQRDMLAH (vector, vector) +SQRDMLAHv A64_V81 0 q:1 101110 size:2 0 rm:5 100001 rn:5 rd:5 +# SQRDMLAH (element, scalar) +SQRDMLAHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5 +# SQRDMLAH (element, vector) +SQRDMLAHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5 + +# SQRDMLSH (vector, scalar) +SQRDMLSHvs A64_V81 01111110 size:2 0 rm:5 100011 rn:5 rd:5 +# SQRDMLSH (vector, vector) +SQRDMLSHv A64_V81 0 q:1 101110 size:2 0 rm:5 100011 rn:5 rd:5 +# SQRDMLSH (element, scalar) +SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 +# SQRDMLSH (element, vector) +SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 + @ # End of: # Data processing - SIMD and floating point From patchwork Wed Feb 28 16:48:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130011 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1754257edc; Wed, 28 Feb 2018 08:50:56 -0800 (PST) X-Google-Smtp-Source: AG47ELtXaQihd2gR7E/gH95i/OTRRKrF962wONNnVL3uCNlPtkHFb2LHICbzSSybivUEM/aJiVpA X-Received: by 2002:a25:e0cd:: with SMTP id x196-v6mr12109441ybg.177.1519836656765; Wed, 28 Feb 2018 08:50:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519836656; cv=none; d=google.com; s=arc-20160816; b=BNMFl8Bvh0hP9/Flqq6w2AP+IlONd/L/3jw6A0zugJz5cJzeKaHfUffzgT9YlbzZwK 4pySOiLTF7bpCmiD3NrgSRMXrkS8YplA1E7xTkQNMhPK9xQYlfVNJVZKS5SSNeqVypW1 vVnbgqAPswNn9PylodNYnIDGhoQ7dUtvnFei2W4ITmLzWqAxg9cYAoWxreFgMtg6AnMA 76USvGC750d0ZFtvFh0WG6RAt3ran1qUuPLet4/g3Mz28wMnOmy4F+FK5pBwR3id+E22 uA6vZA8dBTtj2gZUNt40XHCBdKdIM5+zyM956XC6SO8SMOQUqsUbxuReQNaOszYEjOUB lhoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=08y15+ahNwJBI8xqM1r6NIgh9yeaghjMLRrnTxZZVdo=; b=MYWW2oTmNuzNDr73Hq4m8cvTQXfT3rI+ath9QbX5UCrALM/ny3JVR26WLnir33NRvq EnnKcfKB5zU3J5WUNjqaXWRSVpHON5mL1Vb5tG+G3qf0hwZ61YSTncOSHRhBDbVZRD4Z q+DsT/pEc9kdAgj+x9/Szz8SjSxyrtCIu4x+DVK3vkHdhYFS3S4q/1jdz3gRv6n9fMhs 5k/CXj7GWPyONXbHP2lJ6NBFW7jD0908BmowTxYvRLwZGRNfdGgODxTdBMHXdnum/y6C nK80ji/2zpBOO7VzGl3eqbzqonC4VHenxpV8AbNNV76JgXp9sgtD3mkmTTKNtDPIs7t7 AyuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fe0HppRb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id p9sm4123698pgs.89.2018.02.28.08.48.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:48:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 08:48:15 -0800 Message-Id: <20180228164816.24110-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org> References: <20180228164816.24110-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [RISU 2/3] Add aa64 fcadd + fcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- aarch64.risu | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.14.3 diff --git a/aarch64.risu b/aarch64.risu index c1a29f6..a5c92e9 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2956,6 +2956,19 @@ SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 # SQRDMLSH (element, vector) SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 +# +# AdvSIMD v8.3 extensions +# +@v8_3_compnum + +# FCADD (three registers of the same type) +FCADD A64_V83 0 q:1 101110 size:2 0 rm:5 111 rot:1 01 rn:5 rd:5 + +# FCMLA (three registers of the same type) +FCMLA A64_V83 0 q:1 101110 size:2 0 rm:5 110 rot:2 1 rn:5 rd:5 +# FCMLA (vector x indexed element) +FCMLA_idx A64_V83 0 q:1 101111 size:2 l:1 m:1 rm:4 0 rot:2 1 h:1 0 rn:5 rd:5 + @ # End of: # Data processing - SIMD and floating point From patchwork Wed Feb 28 16:48:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 130014 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp1754638edc; Wed, 28 Feb 2018 08:51:19 -0800 (PST) X-Google-Smtp-Source: AH8x227R2eqnRiiu+xAHF1iFzF6DbHXsjwL2Esp6FnNup1sUp8tMw4wiWEzNwo2dElkKrLuSDZ11 X-Received: by 10.129.52.88 with SMTP id b85mr12462862ywa.189.1519836679457; Wed, 28 Feb 2018 08:51:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519836679; cv=none; d=google.com; s=arc-20160816; b=r9oMRY0I9YM0BZYIVxJ/g1uP204D+AWThFCkrqAR41hE6q5yZ6wWZBrD67k+Fi/cde gts/x2Rt0k+1x/FDnO2TwM0wrKfz8iF+N7JpYOOBAOMLDdihdbZfp7mRtI7FtqxEd8Tr jrZXKhTmGtErNiv6M6CmRDWTONeGtFLAuawqdff1StEtMIp69opsTrgFQ//iA2VvEavw CKA4ESp40WW8UNZ8Bvxo2azuglGkZu0MdNlzlWLJ3Duz0JWaXkY0epDJzYrqAPF1/xX4 j71GuYkKGf7ZEywcFUq4UJV10S0CnQyAc9/yaPiROq+OcQHVRXGNlwc3nTGVlfZZhTIM orkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Qyv7V4h0pVSz27pY8T3TlOZf7AIVP9a7Bm88uviW7zo=; b=xVN+yQbGJ2woLNSdyo4N4s1aCKxe2WRaSW/VNuGCp7a2UCwbo9YohQxjKl1MXksWsa jPDHV9VBQ3bGroyb1aWEYgvTOFRKqHQDZ8druGhhp97P1UFEaSOKd5x6nzUJcmJUROEg ITKMFW93HouMSTttz3nm3Q34AzJggwi6/MzCRlzbGgHgKX2pi3rbJWG7F/vzNj/R0AJf NEscP53KVoLDVigSXvP2w+hNxfhacYvVioylwP7l2rxTDPZT2f3VIYkdnspz1M7ICEj0 6BHQ2uf8cqLYB9E0LpLcX/WtftcRE9LnDyRO9L5FcnfCoCS33DhSWU8IA0KtzGUBn0Sx YkgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iFvj3iyq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id p9sm4123698pgs.89.2018.02.28.08.48.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:48:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 08:48:16 -0800 Message-Id: <20180228164816.24110-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org> References: <20180228164816.24110-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [RISU 3/3] Add arm and thumb vqrdml[as]h, vcadd, vcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- arm.risu | 25 +++++++++++++++++++++++++ thumb.risu | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) -- 2.14.3 diff --git a/arm.risu b/arm.risu index 13ea019..af73345 100644 --- a/arm.risu +++ b/arm.risu @@ -831,3 +831,28 @@ VCVT_rm_neon A1 1111 00111 d 11 size:2 11 vd:4 00 rm:2 op q m 0 vm:4 # Note that sz == 0b11 is UNPREDICTABLE (either UNDEF, NOP or as if == 0b10) # as is cond != 1110 (either UNDEF, NOP, cond-exec or unconditional exec) CRC32 A1 1110 00010 sz:2 0 rn:4 rd:4 00 c 0 0100 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH A1 111100110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH A1 111100110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD A1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA A1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s A1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } diff --git a/thumb.risu b/thumb.risu index bf7556b..b8afa59 100644 --- a/thumb.risu +++ b/thumb.risu @@ -437,3 +437,28 @@ STR T2 11111 000 0100 rn:4 rt:4 000000 imm:2 rm:4 \ # V8 only instructions CRC32 T1 111 1101 011 0 c rn:4 1111 rd:4 10 sz:2 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH T1 111111110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH T1 111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD T1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA T1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s T1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; }