From patchwork Mon Jan 18 02:02:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B39EAC433E6 for ; Mon, 18 Jan 2021 02:04:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8096D224DF for ; Mon, 18 Jan 2021 02:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726592AbhARCEi (ORCPT ); Sun, 17 Jan 2021 21:04:38 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:23242 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbhARCEb (ORCPT ); Sun, 17 Jan 2021 21:04:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610935472; x=1642471472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OxZeZALk6A0U48gWNj8ztjhQy+hUu803QWSi9piqU7E=; b=OFas/Mukni3FGy0qnzL5ai9pvI01Xu70aDwAp1xJZqunn2ucwQOdzO0y D9yJ5u9hQPtvxwHkkRtHHw5hg+aJc0C2Z1wwTyfvNTTWXRM8YIO1HlxX5 a3tJJrzzCZnuB/yVjGbW4OJ/9Ck+sH6mEKhJlWUTKMpLL4B32hs7mEZZv xx6bCY6KxHc6/fGy4wkkEu6AO+yWO+3hHMaTpIlPbIUcxZKwGF5sKSNZn wytEFKLLpFcJrtGJckg0L0c59E4N36CzhXRXLP3HlMqTiRyL0bNnGu1ti M4XFEliMO61WfRycWplxTgX4goYfNj8Q9nTbVZzvvnS19p8KImYd9rPmC Q==; IronPort-SDR: GuJ5/DttAbwgHYyoUKEQIzYx/5hC2xynXFQBfBnq4EHuHL1JjjTot7ASnM7DgPf724g613V6ty P2XL8VOZiwWl3C6w+5Hd4trFCMN6aH9jI1iiFZMAEeWQ2d9/i4IfF5WXCi7cZp0ddlEMWu7grw J0Y6jhCNgSpD6OZy/klEqdk39hkskieYbVvCYDizow0SyyJEdiyd4PY39qvhD/uVdiv1Lnf+QZ EBSTeIe73pTnQiCah273ekq2SvvBtrPeBrgsNtz1HDpHoVzwbKy897omxLtFgkxU2WV4FYJoLk UTI= X-IronPort-AV: E=Sophos;i="5.79,355,1602518400"; d="scan'208";a="158840853" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Jan 2021 10:03:02 +0800 IronPort-SDR: KJgawEfx3IxAmMMSsAjnDPaak3hiqcIhHT8i8YSgySz1hWUqjff1cZUD4TnLPrWWgy0IhxrkIJ 5OozwDeE2kGzD3WWNDn1DABvPXCtEYXf1wgwiHeA8Cs/aLzCylgbEdkfuX/Xe7juPAYR8A9juW sX/t4bYi16tlezk5UE+oIuJS2rlLkfy6tt7TLUa+O4nkvD2O9Uv5sJKfgnMcI0Y7jSrkgeU9Nz tTaFYkqKz7gDa1s0blUqNr/xH3oE74JDO+IV9KDfmSz7TP7DhoQ/gRyjlfHUSW4fTyOcRAUaao E8DsR99T4btGpAcMWm9M4ipF Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 17:47:40 -0800 IronPort-SDR: 5aRbhHDdZ8s4MmZwWXcSTYSctnmetJ2hzXvG3owDgvgnj3nkl7xbHMrUlSYuRIMXjxYQmbi/cd NPIzHkfAjnqoRWf0/ldZosMwZ7JpxyaiokiXoBJX8QGNq589VLRcPxxOvOTBUx8j2a8LvL1atw cqiuhnDBlLHC87DBkBdLDG6OPYSaILwvll9Wpej6udFLuFH8AUNaZjaec6A3heFZKftW5i6XiP sQ5OzrS8pd15SJnlwbURJATKm6YfsX3+g82oOO4H90pJDP6rQ1TRRx7TY8BbI+ZxB6VxFkmC9K cb8= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:00 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 03/17] dt-bindings: add Canaan boards compatible strings Date: Mon, 18 Jan 2021 11:02:30 +0900 Message-Id: <20210118020244.103451-4-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce the file riscv/canaan.yaml to document compatible strings related to the Canaan Kendryte K210 SoC. The compatible string "canaan,kendryte-k210" used to indicate the use of this SoC to the early SoC init code is added. This new file also defines the compatible strings of all supported boards based on this SoC. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/riscv/canaan.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/canaan.yaml diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml new file mode 100644 index 000000000000..f8f3f286bd55 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/canaan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan SoC-based boards + +maintainers: + - Damien Le Moal + +description: + Canaan Kendryte K210 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sipeed,maix-bit + - const: sipeed,maix-bitm + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-go + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-dock-m1 + - const: sipeed,maix-dock-m1w + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maixduino + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-kd233 + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-k210 + +additionalProperties: true + +... From patchwork Mon Jan 18 02:02:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0236DC433DB for ; Mon, 18 Jan 2021 02:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC77A2250E for ; Mon, 18 Jan 2021 02:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730897AbhARCEw (ORCPT ); Sun, 17 Jan 2021 21:04:52 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:17309 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbhARCEu (ORCPT ); Sun, 17 Jan 2021 21:04:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610935491; x=1642471491; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0gydr514UdHfaLZyMWZlPzEDnEe7NJxvNWRTRtcTWlQ=; b=NgAtTA7KdhBFgkw8y12OOmMSoknyWvNXKeBOP5IfCIq3QvJuxvJM4vz5 ET/wdeJAm438oR8Qx3wzOQ01NZ8UmoQ5/5wZUZBDu/3YOu4nRPlIIllBp 4P6EXaX4EBBuSyW4+SH7NoWH3P1lh6Ai1eyoqQN0jw7Xs4bUad6dMlNU4 i0dYABdsqkgg/fvr+h/ud3swmoqKdPy3NEpFTu+FCMxuIbd1o3pp13T+q mHL/T+0hmRbygZKvCysChwRzHiHHp2QDBS/NGcDLWhv9eYlHC6lRLsIvM l8/uhbWv1hCViDizA+ZFd9/bhNGiJEN4owLfXwxlxHzw0P4XMSmy4UnCX g==; IronPort-SDR: wxDeh9mva7nLToqAJJ9pMaobOPOfGQxqiY0yFAan6D9dmZ/X4Zh1S4gHXJRWGMGF3kZwXeCcad 9xehUcgyrhaXTZYVSdBX8dtxnosIshXy04QOrSXSjPcpw3x9334sovVSbcX3LwSR/B0hCFIf7t KbDOyA45TGsZ/d8UQ4FoPbE+3Ldmx4YVo3l1P6Hn6Xim5SYkEsbiSuAw9F0+5wDxCgqaUETqP1 sRMDnP+OHijBsLyCGBGEH6U6aHvopNrcgWy/0pbVOASKLwHGGDE64R1ssFUf7+9uafSw6xXUaI KGY= X-IronPort-AV: E=Sophos;i="5.79,355,1602518400"; d="scan'208";a="158840859" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Jan 2021 10:03:04 +0800 IronPort-SDR: X/rBmh52+ri+yrP7MqwZY9XRSc3QWHgWmh+7m/bM0gvOKwUB/xaw7zzc/k0QjF95ec1/Qgdya8 zjQ6c/chCuIcs0yJ9a5T8V6yC85/9m/kPsArCNGskJXwwlciTwJW9/svyM+jReAX0/3gtRCnwH iz0cAjjsx9COHMt7vwnd7HYHRPcJp3oOtDlBViaVhmnFIkDGUDgaUfPGlZabVQiAaQy3v1cDqq NqhInma0alRpFGn9Dipa0a4mrbic/RqD8Rq0L7Z365/RH1DlmKRU31y75KsnYzhcBdj+ipqT6q i7T+dbfFgv+qqaibtXDHCJTK Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 17:47:42 -0800 IronPort-SDR: ppN5KI0KQdC3mGewT3XHqaxtTQ9UjFrZe3c8k4kBhLPXO2RbJ2mDjoafqK1n/Q+Jh0hNZKoei3 z2OK+emUUm+fdHL/8pmmyKuMZTaWUGQZ8X2n/Du/dc8cI/wdshFjBtcAOMN+q9RalNMLTOmI4e zX8BlcPFVq4AuQuwqP4ES1i6DLIyVQE7My6B6wExOGiAp40ABrTo//q3BeKyKP/PishQKWN0oc iZeJcUQ1412+1C4y2AKK5WJfOvW1wSrBCuqSJZ2PoypostktPuHK5UJSjGlB9DM51oFViSscHo 6+M= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:03 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 04/17] dt-bindings: update risc-v cpu properties Date: Mon, 18 Jan 2021 11:02:31 +0900 Message-Id: <20210118020244.103451-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: From patchwork Mon Jan 18 02:02:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D951C433E0 for ; Mon, 18 Jan 2021 02:05:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 090062250E for ; Mon, 18 Jan 2021 02:05:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730925AbhARCFT (ORCPT ); Sun, 17 Jan 2021 21:05:19 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:23242 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730866AbhARCFS (ORCPT ); Sun, 17 Jan 2021 21:05:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610935518; x=1642471518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PieD+HEsZTf13C6UeofD+u83C3BRDKwXIiv/iI9JJO8=; b=r8l0WiYHEUFnVRnTHq6Dvl47ZFi7b444OjNMItzaSVJfVLVAs4hxz1Tb kkmKxFo8tgwuzGXvHi89qHFRXfiVF3o5Qc1jkSx/UMsHi9TEnLv2E/1wT XV4jcfjwr9Zzvxk33UcCnbBoTbaBidI8puvWzkGK0FDRKisPI9bsRbjX3 QIYHU/QGO4VklIx9wIBEENkCgiU7ixK1zD50FbbYWdDE3EMkc+5cOFMP/ xHO85ZmUWSplMu4HWtiVVW5jbMHf9TOa653PbvrnLcC1eTl5GUZx9xYTw 8kf+7OW7MpzPdlt6PJP7pBn6pUjWrkIZYF3MwGpjt9Lq3ABjfCinGLsQa A==; IronPort-SDR: t2FK/Tpnqd4eo1LNAY2rNynQI5FtgWZ9YpdO8yRWfUtw9o0K3cl809KYjDEEee70JcsJL5F39P yRPXZvlO0goZsE/y57GaB41MTSApOlHAx1R2MMLCawYOoqHoFTEYQJGfAfwAPjrf8kB7LYSOTI VEuTTOPHJWyP2u+5RcMRn42kXKAGcJ7nOzNGBQcKb/PgGZPmAvMxF384n2ljVpnzYVo//d/cCl kCXYb94kpUaK8GqhhTDhGvfPktezGulyemxrXvdyij1kK73eFCVsHrsXoXNCArXOk0C8muZeJV 1c4= X-IronPort-AV: E=Sophos;i="5.79,355,1602518400"; d="scan'208";a="158840871" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Jan 2021 10:03:08 +0800 IronPort-SDR: La2YSdPjhKFZhcVtSvqHbrvL43HTLZAbkhsK+bOhx7gjAoL7J5If+xvZjNtxd5zjJSVYLUFlGE Ro7PcV/zJ5ZHvdqn0fPSZFgKg3Eg7tZ+xPqmgmYcsfe2hVdtCMt42EK2ciKoSAGONrVHrgJ0qH 0RDQicNrpXOK4bei3BFlk5MW9pOO0aYWE5nTtK2v1o0o/rAy7MaoZ9Gfsqd2T0PzCYi8BrzY6P bZOs+coukozOTTpSOeMfIIH3hCvaug23Tf/cKBJA0iaRLLrvLF8skaeOtJnnOIdd4uGDTWaEXq vfwHzoJClEsaK/U3VO176CHy Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 17:47:46 -0800 IronPort-SDR: +eewbUvStbtrd8VXQzuiJPmiWKzWwEw52/p1fgyMiGX5Ftfm5zNefsSgZQd27X//NLaHmeGQ1p Z6410CvTIOqoKBLWCT6EvptSZw2sL8SgsuLUCfu4LdVh0kmWmn0K2h1oFnkNZpfA7wAY0/qTbt gXNQFu/e/t8rQ5V/pRT8VLdkdRLXiPlZ64BWLc/5gz41sTbr2A31ttb6lYd8wqKI8FdJ5DJD7r N0OsCBUDgqsOqkDqYQvDTNygC9a46IzIfgc4B6at90E5L9l0MwKCeeR8lj6yh6sQNntNabDJjD YlI= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:07 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Anup Patel , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 06/17] dt-bindings: update sifive clint compatible string Date: Mon, 18 Jan 2021 11:02:33 +0900 Message-Id: <20210118020244.103451-7-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the "canaan,k210-clint" compatible string to the Sifive clint bindings to indicate the use of the "sifive,clint0" IP block in the Canaan Kendryte K210 SoC. The description of the compatible string property is also updated to reflect this addition. Cc: Anup Patel Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Anup Patel --- .../bindings/timer/sifive,clint.yaml | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 2a0e9cd9fbcf..1a7d582a208f 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,16 +22,23 @@ description: properties: compatible: - items: - - const: sifive,fu540-c000-clint - - const: sifive,clint0 + oneOf: + - items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + - items: + - const: canaan,k210-clint + - const: sifive,clint0 description: - Should be "sifive,-clint" and "sifive,clint". + Should be ",-clint" and "sifive,clint". Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated - onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive - CLINT v0 IP block with no chip integration tweaks. + onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and + "sifive,clint0" for the SiFive CLINT v0 IP block with no chip + integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details reg: From patchwork Mon Jan 18 02:02:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E380C433DB for ; Mon, 18 Jan 2021 02:05:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D31C422510 for ; Mon, 18 Jan 2021 02:05:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730941AbhARCFz (ORCPT ); Sun, 17 Jan 2021 21:05:55 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:23241 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730940AbhARCFz (ORCPT ); Sun, 17 Jan 2021 21:05:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610935555; x=1642471555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HnJ883zL+t4xSM63wnXK5D+H6FssPdmgykJIZOwLcLA=; b=GXQgNmlj01SU44vJWRI4Nw4EOr5Y2TISJ8acqd5Dg8ai4pG3zorrwp6a dvBThnzzY1Q8nsVQxH+eVcZ+aNXB7gebW8Kx/fkfi92QVBmzdcVBGY7O2 dfU8S8FMKHyV5wfYwIBUb93QmPPxQhwpXmgFwpwcX9fku0DrfYZwBKlwy 9WY42gmQJ5QyGO/h6WxiBMam4hinoDX/dqkt70tTdjMO2cT1qW/Lvy6jD FIVXNKxwZD94tO5I4dDo6Y45m1lCnH3BrsCS2Q8r/uDAuBsF69FVUkZQc 7omQOimAvaUDrHx9Kxef1sKQ65QJedhi2lfgMV8nwcUqucwqKDJObJyXG g==; IronPort-SDR: mgszxdzxjRRErFlnctmEP1zsOX4HItrqdUFac2uBCA8BOcW/XvkjkRPgjho1F5mAhIZAaI+S5i 9DFvsNsiVMdxpY5/5/x+ZOWMmXN5kXA3evhKVFYK60UOyPpFS3p+Yn2dTa3Q57eiaJryYmh0m5 ziPYWjBBE1u1OPnf8Maju5dbXMwVJ3lc6VQy0KM4wbFJQzjlUXwhkrAe12W59xfkpRGlTW7WG4 Uy7U7FYd7M3GsgUT8RsSalXSYK2eJnSnVGyz+ZkdK/YIcqv9SAOQ1cAAmFo0qPT4Ny37oRbaOR ZA4= X-IronPort-AV: E=Sophos;i="5.79,355,1602518400"; d="scan'208";a="158840883" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Jan 2021 10:03:12 +0800 IronPort-SDR: sIyPOnuuTKOuswzhCa8C2CYx206D87peeyO+DClOdo18RIvpGl2rJb+NV+mUrY0DpWxPnjlItN /5otqqffM2VXcykWI01A2KZy54V+aNsNWvXeS+DXFO0SrA7W7DXToPtUhoSgTrzsxQxMHJNL26 cMKHu7XWQ1RIzxK9Mu81isT3mqMv6ZCJzc+lLDsTMWYcwAdE1pKfkuiF8fSCdpHEMAwZZF7AcT dRWTFvG5Q261w5pJKUZiNqkaKS5ssDMRIDiBeFvcBYqSZF0Z7iian8lhPE+NYWnaI9j9xNSze9 mssvA2zi08Dus/i0KQ61eVqP Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 17:47:50 -0800 IronPort-SDR: QrNUiJfzoKM6fXZiFKAMFSCSOI+R03Cb6vvw96EpFCrKreBvi0MzINZKrEb989HCZrw0hZyTwp d/ckJMJYQgRH/V2tYslAirAPBN9qLkVfZY3SB6RkvpTjqhn1dAW4QqXd0yLQD/xJS6ahCbsSrE vIRAUt76OyFonmQ05+al0xWhwwWUy2NnNDCU7WGW4O+D/cq/4x7nYwJpizm8jI5Yh0qPZpuVTm SHFV6sYJNSp55OaiK5WHdzuW98sfP7NC8VBIdGTqwbQBpOKeH7yWMVbmO6tchHRbjw9KY128iU B/k= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:11 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 08/17] dt-bindings: fix sifive gpio properties Date: Mon, 18 Jan 2021 11:02:35 +0900 Message-Id: <20210118020244.103451-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string to indicate the use of this gpio controller in the Canaan Kendryte K210 SoC. If this compatible string is used, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio IP block. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..2cef18ca737c 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + interrupt mapping one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,10 @@ properties: "#gpio-cells": const: 2 + ngpios: + minimum: 1 + maximum: 32 + gpio-controller: true required: @@ -46,10 +51,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples: From patchwork Mon Jan 18 02:02:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6BB0C433E0 for ; Mon, 18 Jan 2021 02:06:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69D43224DF for ; Mon, 18 Jan 2021 02:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730934AbhARCGT (ORCPT ); Sun, 17 Jan 2021 21:06:19 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:17309 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730940AbhARCGR (ORCPT ); Sun, 17 Jan 2021 21:06:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1610935576; x=1642471576; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3+AZXlQYL+Oi9isOvjtJAUNCWKaUzQuawdKiXp5Ssaw=; b=PweY8LEhmaDPPgwoeOV4dKgQ2Dtyy8v3QuRVfmzwSSXlxdGL7DY+YEYq 24PzuCIJ0SQJ3ACfCOGvN9CHdp8YSULCbECKaF6hGFkuI7j4IXu105Xko 5dz9/4/CRXssY3nD/Qazu9quaqUR21gwVee9DDnznvPHFHPTtCI9OrTGV Ws4nI1MsSvktplSzxd8NrTNJeB5CmWFLFKWA6Fuwkdyg4HGbQzeLkgML4 9kG9L0lPPyoS0e4hrTGZm7zkl2wtf0PguHeVNwnEkf2b9Th/Ph3vysN9+ Y/+nfEpUf/cmbEkuTyZgWjNpO6axAwCf7cXtW9x18ijzEsbQVDNCb8ZDa w==; IronPort-SDR: 4/MJRh6ae1ymoUFqNpA4yPTNPW5w2CfuAU1GHJtELK7fTZvykZhZDpBVAhF6an8tdvrdcT43xm pLQw1g0CdrIdc8BBBB+w5k2Uecy/k4bZz8RSQ4s3LWVrTnPs5qqmQaySa6kGtcXn+MnRKv3jWT IELZ3+ogamrGy5VXBYyFPcpGBGO6BAyyjRgdU0/l1AYSt4wRBJ54NfyW1GufMefWrSx2azX6l5 2Ra30+wKYkTUin3YWqg1iLvC6tkWk6H1Z8as6bXqTOafIIswIaytiCSR6vvfdtCoopF+HpgEgR 72c= X-IronPort-AV: E=Sophos;i="5.79,355,1602518400"; d="scan'208";a="158840892" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Jan 2021 10:03:16 +0800 IronPort-SDR: SbSp/vTdkg4WXqnDiJP+YPLaJi+2Y8MN2BAM1I3/eSwn4F2PbPFqReSsW1VK4Bm/ECFeFEHmtr hLT5+9IeNvdvjbj6kJ3CtgdaCI39WTOIS19ISSoceztmYndE/6GRuPmGTqzrAdIRWSOINrsHWj SYQJcz8TKh5hYPutt0l2tWyj6lZtyHtGy66/wMOgmZs0dNkpw5KACQ2x1KI7p40PydG+s1oP+E bngiylEpB88UbYQ2ODILYbaX3gJ++8JIo9agbPExLzDFSixIkwCwTUgORYkDoTO1KAVZQ5iRov ut36ey9F0iLJXC6VhJmSlJTF Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 17:47:54 -0800 IronPort-SDR: biTUO9A9TZHIbew6Zug5Jpp4ArST2/xtiji3H18ZiVgiidKzHeRrIY2Y5Pyou7y+Umzjk5N+/s 7v3T3tG8/HXp1JQzv2CSqQg1FwRDH7PLeshnyiWdRLoxupEsNXclGrU3B2U8/1Swt86b1BStK/ Bl9IdQ0XRwhw3OirjcED2tBryX5S/4l/dRsNpnIRn1vyCxe43GAvfKHzHUJU5M8nxKD1vGgdkk pc1jUl+RqBs4GlMd/1i+IPFoYKS2pfTgEV3GP1h4dnoQqxex8PUx44EWesUhUkcN7BZFGiYFz7 4mo= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:15 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 10/17] riscv: Update Canaan Kendryte K210 device tree Date: Mon, 18 Jan 2021 11:02:37 +0900 Message-Id: <20210118020244.103451-11-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the Canaan Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default value selection of the SOC_CANAAN_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes this generic device tree suitable for use with a builtin initramfs with all known K210 based boards. These changes result in the K210_CLK_ACLK clock ID to be unused and removed from the dt-bindings k210-clk.h header file. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the K210. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/canaan/k210.dts | 23 - arch/riscv/boot/dts/canaan/k210.dtsi | 535 +++++++++++++++++++- arch/riscv/boot/dts/canaan/k210_generic.dts | 46 ++ include/dt-bindings/clock/k210-clk.h | 1 - 5 files changed, 554 insertions(+), 53 deletions(-) delete mode 100644 arch/riscv/boot/dts/canaan/k210.dts create mode 100644 arch/riscv/boot/dts/canaan/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6402746c68f3..7efcece8896c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -51,7 +51,7 @@ config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN depends on SOC_CANAAN_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/canaan/k210.dts b/arch/riscv/boot/dts/canaan/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/canaan/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 354b263195a3..63c1f4c98d6c 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include / { /* @@ -12,14 +14,33 @@ / { */ #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210"; + compatible = "canaan,kendryte-k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; }; /* - * The K210 has an sv39 MMU following the priviledge specification v1.9. + * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". @@ -30,14 +51,14 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <0>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -46,14 +67,14 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <1>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -64,10 +85,15 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { @@ -81,40 +107,493 @@ in0: oscillator { soc { #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210-soc", "simple-bus"; + compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + debug0: debug@0 { + compatible = "canaan,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + status = "disabled"; }; clint0: clint@2000000 { - #interrupt-cells = <1>; - compatible = "riscv,clint0"; + compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; }; - plic0: interrupt-controller@c000000 { + plic0: interrupt-controller@C000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + #address-cells = <0>; + compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; - riscv,max-priority = <7>; }; uarths0: serial@38000000 { - compatible = "kendryte,k210-uarths", "sifive,uart0"; + compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "canaan,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "canaan,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "canaan,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio-port@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + ngpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,k210-spi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "canaan,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "canaan,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "canaan,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "canaan,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + canaan,k210-misc-offset = <&sysctl 84>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "canaan,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "canaan,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; }; }; }; diff --git a/arch/riscv/boot/dts/canaan/k210_generic.dts b/arch/riscv/boot/dts/canaan/k210_generic.dts new file mode 100644 index 000000000000..396c8ca4d24d --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pins>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pins: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pins: uarths-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index a48176ad3c23..b2de702cbf75 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -9,7 +9,6 @@ /* * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_ACLK 0 #define K210_CLK_CPU 0 #define K210_CLK_SRAM0 1 #define K210_CLK_SRAM1 2 From patchwork Mon Jan 18 02:02:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71444C433DB for ; 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17 Jan 2021 17:47:58 -0800 IronPort-SDR: 4B1bnfDrdtRhHkIZpcewlBwTvk0HUStm2Kwa5VVPMQ3vvetNtARwOW4rvdQH6C0PjYwLPtZjMD SsPWfsZ/mVlT4ePjU6+lLMbjiL/W1anWl4kr8XC3EJ3bclwrDY7H3hT87KByLtX9JI+NokG3Dc L+tZFUBCdrv/9O9UrdvaeX7BU4gEwh60+BO+6T/gyOeZpFuvEZCagYcNJuOJ03rJHv7B2/XKpe rl75FGY3VwTwhdEoAK7oB0kwTCOf0GSKXqhNRNnlMwikrRcQVT7dj7s54iDyqvP/owIRWQCqcH 9A8= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:18 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 12/17] riscv: Add SiPeed MAIX DOCK board device tree Date: Mon, 18 Jan 2021 11:02:39 +0900 Message-Id: <20210118020244.103451-13-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_dock.dts for the SiPeed MAIX DOCK m1 and m1w boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maix_dock.dts | 236 ++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts new file mode 100644 index 000000000000..fae0149a8740 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX Dock"; + compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* + * Note: the board wiring drawing documents green on + * gpio #4, red on gpio #5 and blue on gpio #6. However, + * the board is actually wired differently as defined here. + */ + led0 { + color = ; + label = "blue"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "green"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "red"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Mon Jan 18 02:02:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 365708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D5ECC433DB for ; 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17 Jan 2021 17:48:01 -0800 IronPort-SDR: q/IgvxQldYFLTeNAzniOrqgdkA1Ro03m5iyjnM/dW1YrFqJNx1EwzmHMpQcYcPpWSAdheWdrgs nt4zbTPqjkqiCJCuUFRI998K9QaSRk4UJQlGOrkLPaU1mOfwn0hE8N81yIUnIzHovVhtuyw1L7 8Lb0ZH3txq3raZeGU081u4Sjj7cnK7PdFRMoUgvjzeP7+dfz8kVEqpS2b6jC9fWqkRblVfrNnQ sOpEjfSmK/oh8tTxkNhhQszGg+KfZGpzzTGtxyVS22RFFiJfad/UKUBovHraa5fHrhBuLkEC3i 6gQ= WDCIronportException: Internal Received: from cnf011319.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.70.208]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Jan 2021 18:03:22 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v13 14/17] riscv: Add SiPeed MAIXDUINO board device tree Date: Mon, 18 Jan 2021 11:02:41 +0900 Message-Id: <20210118020244.103451-15-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210118020244.103451-1-damien.lemoal@wdc.com> References: <20210118020244.103451-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maixduino.dts for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maixduino.dts | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts new file mode 100644 index 000000000000..804edc45eeeb --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; + + vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + power-supply = <&vcc_3v3>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};