From patchwork Mon Jan 18 04:43:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 365459 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1925992jap; Sun, 17 Jan 2021 20:44:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJwCi3Boa2LnN+ssS7sjHn9kZd1Y8U7RB4S9HowGiC+HEkcZEPb6e/KRyJuJ5ry0QTDjF6BP X-Received: by 2002:aa7:cf85:: with SMTP id z5mr17842678edx.274.1610945075045; Sun, 17 Jan 2021 20:44:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610945075; cv=none; d=google.com; s=arc-20160816; b=k6W1rjffdNHt1Bi4hz/aCU2nYY5v/oc0fx7yUV/vKE8U//RTB3XjC6sQz2qyNlIYVv bX65YqbnpZjZQVSRwaAo9BNpk18fI0DS0SuNH7kwaQXEsplKCzuOoXRu4bl5dEUIkXYL Ql/KER/hob5XW/9OACt4p+DTDxVo0Zf12PMBDEyUeFVZSrplAVxmQD03bbzbJLdstLsN j/VhOx/U1/VEyrifziFk/BoWwHG0/vf7j/01awJbZwSipJIjmj+A2TENDxDfHhBD842V aqRddGf9XDUczdw8wl2gb0LAjmfHHwzlx4JuVNFS7ZtGyVrEUEnufzTBNCs9ODTVxpcX MOCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=683W22EGa9sfpPqiD1cgo3Eou3RQzllrvaOP7U1PtVE=; b=C+tF7vuRysKmnD4sAPLjLCljymjIhZ7diof5jae7lrI+KOaqRTZd2WJi7nfh/XCVBz UP/ab3fDa00itWhd/hxbPnhPPXJn0YWw+EijoLTtpxGKsZB/CTaIEwJE2/SjBho6SIT2 oEiAT+2IW8b7dSBkWAREBPO0WRCR/WRrY+9YODh09DtAAuOm2932bQWIXkjeZ/BceEUw avbIEdDK6HHYRoD7vbcCFe3s41Pt0/w33Tvi3wgDCrJ9RXIufRBxB8NBW00mgCs3CEBb w/M1RUyTR4wmkHBBJ5I+1t+XOAqKX6FDwh2WJmKW6mEp5vRV5tUTsf0x7x8NC7y6lN/V dVJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QQI6ctGx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id yd15si987179ejb.577.2021.01.17.20.44.34; Sun, 17 Jan 2021 20:44:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QQI6ctGx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730951AbhAREod (ORCPT + 15 others); Sun, 17 Jan 2021 23:44:33 -0500 Received: from mail.kernel.org ([198.145.29.99]:56792 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730652AbhAREoc (ORCPT ); Sun, 17 Jan 2021 23:44:32 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id C22D322512; Mon, 18 Jan 2021 04:43:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610945031; bh=6z7J0nXcSYPrbRD9ikeD2XiTuiVWtgpwGcxMh9Zj5v4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QQI6ctGxdssTdkiCZAFgkxZUgw0MjVoGnpjTFB/pL40DQ35rLUS/usdChZ1861tvl vryOlNLbPHoeoa3wD12jT6IKHQDTNwzGjRl5T9PBp4iX+O5ZZdLOGnjtd9JyZ44V50 bPdy/xrm8LkW67hzSzG1520FnLWVfmmVqhAWT34BEuQySX3LsN0EoicuFV2GuPwqro XkafDNt1O/IvSw3b7loj+xtQ7ieIugkvfdrESrFDh2h+64zAz6nzC+s9+BFb6qLEck 3izb7acXzbXhV9i5n49UE5MxqIh2XCDeCGuR5eCLldJLDueCdWmBzGOLgMcz3mgPpo b565KyQYuiYtg== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/5] clk: qcom: clk-alpha-pll: replace regval with val Date: Mon, 18 Jan 2021 10:13:17 +0530 Message-Id: <20210118044321.2571775-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118044321.2571775-1-vkoul@kernel.org> References: <20210118044321.2571775-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Driver uses regval variable for holding register values, replace with a shorter one val Suggested-by: Stephen Boyd Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 21c357c26ec4..f7721088494c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -777,15 +777,15 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, static int trion_pll_is_enabled(struct clk_alpha_pll *pll, struct regmap *regmap) { - u32 mode_regval, opmode_regval; + u32 mode_val, opmode_val; int ret; - ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval); - ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval); + ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); + ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); if (ret) return 0; - return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL)); + return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); } static int clk_trion_pll_is_enabled(struct clk_hw *hw) @@ -1445,12 +1445,12 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure); static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 regval; + u32 val; int ret; /* Return early if calibration is not needed. */ - regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); - if (regval & pcal_done) + regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); + if (val & pcal_done) return 0; /* On/off to calibrate */ @@ -1476,7 +1476,7 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; - u32 regval, l, alpha_width = pll_alpha_width(pll); + u32 val, l, alpha_width = pll_alpha_width(pll); u64 a; int ret; @@ -1497,8 +1497,8 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); - regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); - if (!(regval & ALPHA_PLL_ACK_LATCH)) { + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (!(val & ALPHA_PLL_ACK_LATCH)) { pr_err("Lucid PLL latch failed. Output may be unstable!\n"); return -EINVAL; } From patchwork Mon Jan 18 04:43:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 365460 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1926676jap; Sun, 17 Jan 2021 20:45:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJww5aprTfYx+U2PnkrNYZnC4mdDGiw3cTG6oxoX8o7hHYuJ0gwmZXVs8mYosnldrzVs0XXa X-Received: by 2002:aa7:c78c:: with SMTP id n12mr18125045eds.363.1610945155901; Sun, 17 Jan 2021 20:45:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610945155; cv=none; d=google.com; s=arc-20160816; b=ePydaelvdTC/CKWJ6h2x4IHXpOSd4FsPt7ZD+4F03/d9yCwl3zXgkD71HpyLEi2X+I ApLRMah5ou4XF1Uxecog/CqVk74ISrAR0diK1eyRQz4DprbtfSRnDVtbegY5T2eCZMrV 8D5icLGg/VqIrHGFvyqE0eK7xU3okRWo6CnTrpc49vewOTciMo5N1cW4ahSylgRH4FvO Xmz3oMP3nTuc4pf7gawyasClicAnjlqYN2klRZOgVW5IQ5DqsN6I64Z54bKTH8SABxS+ v7m8YjN4T7HihyJMzMh/UGVo8JADUzMSMWAGGcP51KYn5qB/e00Wqg7Xuuhw34rGw1BG jBAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MU7juveuXkkRoW7++LWkMDXlMlgCfEcwLZnY4L7TTHg=; b=pKpxEwDlNjEg88J9TE/I598hQ1jqA3etu8JMigcNFjnqwKeZIYn/MeYoX9qMRugZtM JXN6AKeBeddTBl/0/bs5aiamj3GBtVi7AO+2vqf7ZOnf9Wx4eQi3VhDeM9yb4xfF8+Ss YGoi8YM5LVjoSBa+H5ee61bYg3Moc697BCjctHQeMchOFHw+56q/UizUrXHx4+Ky5rKp hCWQ6Kn8bffRUj2Mikr6hT0vIDqgBVL4bwqVHAkJJ0sNSOvE19pvFCfSdcflutbvs1BE 6SoDJCtUZSSYZ/Yy5/foIbkpg+AFLbMwhzFkBfgqOvYw92bNS/+MFPKmJWrGVYunBKcy 11VQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HU7jygma; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c25si5954937edx.588.2021.01.17.20.45.55; Sun, 17 Jan 2021 20:45:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HU7jygma; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730652AbhAREok (ORCPT + 15 others); Sun, 17 Jan 2021 23:44:40 -0500 Received: from mail.kernel.org ([198.145.29.99]:56830 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731039AbhAREog (ORCPT ); Sun, 17 Jan 2021 23:44:36 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id DF64A224B8; Mon, 18 Jan 2021 04:43:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610945036; bh=ujekwcrP8/ZvXDo6NAzxT624d7YlfKOIsh1MNlzQXL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HU7jygmakiUs7elE/rEdfOsgxh+dqEtdpy7Rx57OM7tc9IJOmxvMy7Wn67vUf3Y6n sw5frbfK34dMU5lPFectduXcGK/V7leInaGVL58RKWyd9SF9BV/Slm34gGac432/PD G6iNcBG9F6HuPRsRMpjtKMRp0zV9Fv+hrBvyW/b8OoyDToHq4DntUTUuuTwprks4sE A0KPXXUuo31rZW2iWXbjsDYXy0EaXSxYYl/p5/B/j/s8BedJMiPKWkjA3Qay5pKcXt jSdf74Scb8ZJjd6cIlV2X7VdlDUZzNe7x1jkm+ms11FphfpUVD1OVO4vk8NG+AHdEv GhNkJYCvGBZeg== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate() Date: Mon, 18 Jan 2021 10:13:18 +0530 Message-Id: <20210118044321.2571775-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118044321.2571775-1-vkoul@kernel.org> References: <20210118044321.2571775-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but with different registers. Modularize these by moving out latch and latch ack bits so that we can reuse the function. Suggested-by: AngeloGioacchino Del Regno Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f7721088494c..a30ea7b09224 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1471,8 +1471,8 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); } -static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) +static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate, u32 latch_bit, u32 latch_ack) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; @@ -1490,22 +1490,20 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); /* Latch the PLL input */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, PLL_UPDATE); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); if (ret) return ret; /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); - if (!(val & ALPHA_PLL_ACK_LATCH)) { + if (!(val & latch_ack)) { pr_err("Lucid PLL latch failed. Output may be unstable!\n"); return -EINVAL; } /* Return the latch input to 0 */ - ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), - PLL_UPDATE, 0); + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); if (ret) return ret; @@ -1520,6 +1518,12 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); +} + const struct clk_ops clk_alpha_pll_trion_ops = { .prepare = alpha_pll_trion_prepare, .enable = clk_trion_pll_enable, From patchwork Mon Jan 18 04:43:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 365462 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1926694jap; Sun, 17 Jan 2021 20:45:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJwN3nO1Q8NdbwFcXNwkSMWWnFGdnsvjkqVdtz/YKrhXPPo+WvaDf1P8NALyqpT0FY+Ane/1 X-Received: by 2002:a17:906:f1cc:: with SMTP id gx12mr15430474ejb.164.1610945159112; Sun, 17 Jan 2021 20:45:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610945159; cv=none; d=google.com; s=arc-20160816; b=PA0xgtwiJ9Y4w2mwS0QtG0c99CEfGss5RxE8F8jNFqRSITs/htr1lOwkV39BNt1tX6 AI/Iv7rdr5Gqe7S2ZiY2T7NR499CsS4gu66xP/oXoiGWgvS3CXZZJ9jKOdZ6iVDSiZ8y r6pI9iHjM7owmsP0xM7wIRK5dgrhoEEYMXw2+Nr3WItq+wA5nlYimuAJchTt/WC2aRbH LDNTKY4NcmGhzX/XcYLNVV0KdsRZGaJzy05F9yLOxzdlFNtl0KEYl0rwjCanb8PugL7l V9x9RX3TXF00C6CPpGR9zg8a1+XsdW6Ek3eA/DhQVO+BVAreizjZBtDbWUZ0T7uvvgij wOmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NBJXRdkMZeftsH5CKBa6/m0XJ4ArJREFVX9CfluPOIE=; b=U6SUUuZ06MHEPsFueCEZl262+f5K9am08bQ9azWCxUUm9N2J2E4fyQCeJrfJeLYsHX 817M853UXDcGNVC961s58xKaDV1sWIsmADTw7jFpAtggwqN3E26JKYtzO9mfufApD9OW G252tWJl8dVkgLcrXvZjVFA637183w9Dp2jhjvgo5dGQYyCLBJyXLvoguLpITBKRNeQ9 dhJMZeGiNo1xwWEtdXUBfFCPd1CtGnLfqv3ombTFOh/UZvRxUsk8N6HOzEpbwYDdl+1K Z+KrTHsYTnh3bYt4xwwDiqKBBPKGXk9GfmIgVe10yn+sPbCnYbMbnVdhUrAxih0aKKjt WV4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="JxCF5/Lw"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c25si5954937edx.588.2021.01.17.20.45.58; Sun, 17 Jan 2021 20:45:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="JxCF5/Lw"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731245AbhAREoo (ORCPT + 15 others); Sun, 17 Jan 2021 23:44:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:56852 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731139AbhAREon (ORCPT ); Sun, 17 Jan 2021 23:44:43 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id E444F22513; Mon, 18 Jan 2021 04:43:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610945042; bh=ZeoeQRZluUpfUTzdColqsD0FJk5rDN19ZksfzGRLdxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JxCF5/Lw81Ae63NqRWBmbtAsMViWsZOO8Vrx3H4WHacCm3TsnfTKG/oPbCpXHZes1 mPosl4lRar2mLlX4agLpqe7rIK8R797zdKcBVyc6nQQoVLJaQQ+NOrAJ58i/3rgYxd 4iKKWzAYK1yVJWrElbEFrin0cS1tjr7iV46yfvekh5hdRSRps5KpHHeQvojWMawkCC T5OBPwaptgLOsu9T6gF+8U4jQSygFjxCMmsWuruzt4/5wHgJf2qb/tSx9U057haTYA i3TUE63ZTitgdp/erPK7AQHpy/cg4FjBvhj3903MGgd3W3kR6CxSgimHug+dLcMrT0 zGA6cq9CDZfJQ== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vivek Aknurwar , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeevan Shriram , Vinod Koul Subject: [PATCH v4 3/5] clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL Date: Mon, 18 Jan 2021 10:13:19 +0530 Message-Id: <20210118044321.2571775-4-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118044321.2571775-1-vkoul@kernel.org> References: <20210118044321.2571775-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vivek Aknurwar Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar Signed-off-by: Jeevan Shriram [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 173 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 + 2 files changed, 177 insertions(+) -- 2.26.2 Reviewed-by: AngeloGioacchino Del Regno diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index a30ea7b09224..f9c48da21bd1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -156,6 +156,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* LUCID PLL specific settings and offsets */ #define LUCID_PCAL_DONE BIT(27) +/* LUCID 5LPE PLL specific settings and offsets */ +#define LUCID_5LPE_PCAL_DONE BIT(11) +#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) +#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) +#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) + #define pll_alpha_width(p) \ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) @@ -1604,3 +1610,170 @@ const struct clk_ops clk_alpha_pll_agera_ops = { .set_rate = clk_alpha_pll_agera_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); + +static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + /* If in FSM mode, just vote for it */ + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { + ret = clk_enable_regmap(hw); + if (ret) + return ret; + return wait_for_pll_enable_lock(pll); + } + + /* Check if PLL is already enabled, return if enabled */ + ret = trion_pll_is_enabled(pll, pll->clkr.regmap); + if (ret < 0) + return ret; + + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + if (ret) + return ret; + + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); + + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + + /* Enable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); + if (ret) + return ret; + + /* Enable the global PLL outputs */ + return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} + +static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; + int ret; + + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return; + + /* If in FSM mode, just unvote it */ + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { + clk_disable_regmap(hw); + return; + } + + /* Disable the global PLL output */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + if (ret) + return; + + /* Disable the PLL outputs */ + ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); + if (ret) + return; + + /* Place the PLL mode in STANDBY */ + regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); +} + +/* + * The Lucid 5LPE PLL requires a power-on self-calibration which happens + * when the PLL comes out of reset. Calibrate in case it is not completed. + */ +static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct clk_hw *p; + u32 val; + int ret; + + /* Return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (val & LUCID_5LPE_PCAL_DONE) + return 0; + + p = clk_hw_get_parent(hw); + if (!p) + return -EINVAL; + + ret = alpha_pll_lucid_5lpe_enable(hw); + if (ret) + return ret; + + alpha_pll_lucid_5lpe_disable(hw); + + return 0; +} + +static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __alpha_pll_trion_set_rate(hw, rate, prate, + LUCID_5LPE_PLL_LATCH_INPUT, + LUCID_5LPE_ALPHA_PLL_ACK_LATCH); +} + +static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + int i, val = 0, div, ret; + u32 mask; + + /* + * If the PLL is in FSM mode, then treat set_rate callback as a + * no-operation. + */ + ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); + if (ret) + return ret; + + if (val & LUCID_5LPE_ENABLE_VOTE_RUN) + return 0; + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + for (i = 0; i < pll->num_post_div; i++) { + if (pll->post_div_table[i].div == div) { + val = pll->post_div_table[i].val; + break; + } + } + + mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + mask, val << pll->post_div_shift); +} + +const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { + .prepare = alpha_pll_lucid_5lpe_prepare, + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); + +const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops); + +const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, + .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0ea30d2f3da1..6943e933be0f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -144,6 +144,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; extern const struct clk_ops clk_alpha_pll_agera_ops; +extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,