From patchwork Sun Jan 17 01:31:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 365240 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1106859jap; Sat, 16 Jan 2021 17:32:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJzNt4JeiRpiYeaxDOnQOq3axu8QPCMoPCKTU4CYxRAwZossXxPc7ucrlkd5yVIhA5w2xUp9 X-Received: by 2002:aa7:cfd7:: with SMTP id r23mr14613858edy.298.1610847177332; Sat, 16 Jan 2021 17:32:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610847177; cv=none; d=google.com; s=arc-20160816; b=wtyZkFsj4b+JrnS6CBqlxOcQJLoyhEw0A7P6dFTvPMDr2vpRgZrTALTv2DUuQGVqd/ 3TNWxnEqIvsCXVGjJjdf0dkFXhjwPunoscVaLzI9CNZ1Hp/rMXH7CP252pARBGk5GYtk YjNeoiJrpy25SvpPnGgpKOcgSFWWqXKkV6C12Ws3IocWE15sDur0SXhCg/+TwtaWB5I4 B4/VyQBhknTnoz7bLyw+W2oQoKrqpTb2hINYjalFDnes2v+ZYEvncQZJtWpPhlWuWTAV K3STtFnhrZaGrQrJK5AZoZ9kAca0G0X6xT0Tz4oz6kPL6uk2j+uFzle5YcwiDwAufnEG 7Jqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=lEAbgGXRDEkwocWBjCqT+YjaChbyzOIUnNPHnvqiPnH1i/MAyTgHisj4vBk+yRsxHj cLVZiWRqNLj3FAu3mfQ0xJ3w3ZFiPm9AhqWPQSwGuq/gBd1vV8A6IYoUkhE1fH5aoCzE OZDxNVgs8a6YudvxZN7PKPHggFGR4Wbxxt0Gvu9IH33txGN47j/u1roNoGYLX2KP0XcX h8NoxvKWM/diiOJgp6itmj1rhuBsCq68oSypPKP3F2oQQox2AeYso6BIiT2pXRwxjcRH bhH2NQYnuwRRsSlyy+rFNjYKQDvdSpIMyFAnOTFT/3vG3DI6IhI3JQn7SnUUBhBe9w6t K9lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SUINPn4n; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hk25si3317705ejb.7.2021.01.16.17.32.57; Sat, 16 Jan 2021 17:32:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SUINPn4n; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727407AbhAQBcC (ORCPT + 15 others); Sat, 16 Jan 2021 20:32:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727520AbhAQBcB (ORCPT ); Sat, 16 Jan 2021 20:32:01 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 302D9C0613C1 for ; Sat, 16 Jan 2021 17:31:20 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id f17so14498989ljg.12 for ; Sat, 16 Jan 2021 17:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=SUINPn4nDwhozYtpjAYsdnMatmtyWqHA6TxOdxuoy66Gg//CsIyk/0UP5HlNlxe0WA 2HQGxdrqNP+dBZ1JmwWKwoCWXpmql1QDN2NkExL7SzEMas7auT73JQ/EZjIrwl15dlLC Jr6ulZmwqC3IuPL/lC0SVx36WrNATUjdHDg5PBDGaOjGQcAOgPD057tYKf55Z2YbRcKR ATQERCJSRvK9z0NUAvGYre3baY52oiGlR+SnPwsKvirN0oU7k3Ab+Jwt5awYTuPVm7YQ J7KO52y3q2hI4FFLg40Kxt+rDgTQga42FiDilL3fW3QBg6Eh70pDLZHDqWfJTeTaTz1C h+4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=VZSm+QRqujPbk1P2dVeVwvfs7TR4Lx7pxdvckKOTllCwt68A53G+5L5T2OLTBu2wAb 9QbP/foUC9rnHVKd3vfm2E1jIqumkPy2qHJiulFmuCap2zU51caOAGDDeeXByvXJ0d8h k5FwjOHeKQApA11O+VLCTcuy+2Vxuq4i1Luh7QWlc8uw5X6O+wVTKJlY2isFym+Y4kzz jZkKOSj5ckrjaXvxrOqM7oZzAoFAAblHCK2PGWD5/kJ2G+GmnriMg0A8XKlXyRLsNaUO zz7sEC9mGEYNo6+DwX149T8U/FP2Z7hQ8MdJ4VoUnd1DZzag6p3qnO633SpaGZQYINwt Yh+A== X-Gm-Message-State: AOAM533hcroQsF4/j0wwL0K4ybKoSATqpS81423YOD8s53ouBJuHUyHY 21SXlU7W/SuO1d8M2EUkALj1VA== X-Received: by 2002:a2e:80d4:: with SMTP id r20mr7822175ljg.495.1610847078683; Sat, 16 Jan 2021 17:31:18 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.228.101]) by smtp.gmail.com with ESMTPSA id c1sm1286298ljd.117.2021.01.16.17.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Jan 2021 17:31:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v5 1/2] dt-bindings: pci: qcom: Document ddrss_sf_tbu clock for sm8250 Date: Sun, 17 Jan 2021 04:31:13 +0300 Message-Id: <20210117013114.441973-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> References: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Document this requirement in devicetree bindings. Signed-off-by: Dmitry Baryshkov Fixes: 458168247ccc ("dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC") --- .../devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.29.2 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..0da458a051b6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -132,8 +132,20 @@ - "master_bus" AXI Master clock - "slave_bus" AXI Slave clock --clock-names: - Usage: required for sdm845 and sm8250 +- clock-names: + Usage: required for sdm845 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "pipe" PIPE clock + +- clock-names: + Usage: required for sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -142,6 +154,7 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock - resets: From patchwork Sun Jan 17 01:31:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 365241 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1106866jap; Sat, 16 Jan 2021 17:32:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJyZdg6qki4E2KkWC3DIVi1Os7LgqTYdVW6MgVD5G8EcntJaNxf1+ShFdt+fvvCQso+ADOKO X-Received: by 2002:a17:906:351a:: with SMTP id r26mr12739863eja.409.1610847177930; Sat, 16 Jan 2021 17:32:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610847177; cv=none; d=google.com; s=arc-20160816; b=i4zsELpOXt1ZIyQDDjE9oFXIzrTTyc2i4LBNqIp1vVf54ndAATshSOmqvOaycJmSdZ 8XCRdA1WVNydRJbYLafo5x1v7v65k+q3QRRgvKH7FjxaKtwPaBmHFsX83//0sy6xiDbG 3GotJCFsnLe/tCECES8Jhdr5GShqQW0WzkH3hkFpF+9o/aL+fNWLkVnHUAmx/vDvJXDe 9OEo3ryCJljY+kGUuXN31h6udQCfp7/dbS7tZYnfRIKpsnQT3UKEY5/9twqaQm8olLI8 eUV9EKaPLWXQRRm2msTCSSnNYUmrBU8LSwJAHklz6MF8Mwi9EWbvbBDL3BxQRGYCX5Zh a7KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TqPs2Rrxfynaryc0Bxb5YregqUil4E5/ABS7A7T0BQ8=; b=xIZJycT/nXwAWMh60V5b6U/iIb1NLv7YCce0GbkQOcUn8/JLfS+qjv76lLiid9BWvM 4fccNq1zE1fM9PZfSxD0YJeE0bF5HPS25GQsf78+/6QeCTNXfEi2tQn+pEu6yXzADuhZ k41OzNhRA5lOcCBnlxxkSMUD5oi1sh+5rbdmfB5E1G5JpmY2R0/tyqL7k0IkZeYRap5i TuAYsb1/b11ACJph7DVC3aVeOXlW9w081wozASsKS+AoJm298uFOjAnDaStKPyS/SigL YvawLSm24w0ZtvxP5OKiouXutck/D7Xw0ATyr4P6IBtI7kp5YEX2fw1xbT09yO/aLlJc 0qEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KGBEtXkE; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) -- 2.29.2 Acked-by: Stanimir Varbanov diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..ab21aa01c95d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,10 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +/* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[7]; + int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1152,8 +1154,14 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + res->clks[6].id = "ddrss_sf_tbu"; + res->num_clks = 7; + } else { + res->num_clks = 6; + } - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) return ret; @@ -1175,7 +1183,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1227,7 +1235,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return 0; err_disable_clocks: - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); err_disable_regulators: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1238,7 +1246,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); }