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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/21] tcg: Introduce target-specific page data for user-only Date: Fri, 15 Jan 2021 12:46:25 -1000 Message-Id: <20210115224645.1196742-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Signed-off-by: Richard Henderson --- v3: Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. --- include/exec/cpu-all.h | 42 +++++++++++++++++++++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++ linux-user/mmap.c | 4 +++- linux-user/syscall.c | 4 ++-- 4 files changed, 69 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4b5408c341..99a09ee137 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -264,15 +264,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying code) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -287,6 +293,30 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); + +/** + * page_alloc_target_data(address, size) + * @address: guest virtual address + * @size: size of data to allocate + * + * Allocate @size bytes of out-of-band data to associate with the + * guest page at @address. If the page is not mapped, NULL will + * be returned. If there is existing data associated with @address, + * no new memory will be allocated. + * + * The memory will be freed when the guest page is deallocated, + * e.g. with the munmap system call. + */ +void *page_alloc_target_data(target_ulong address, size_t size); + +/** + * page_get_target_data(address) + * @address: guest virtual address + * + * Return any out-of-bound memory assocated with the guest page + * at @address, as per page_alloc_target_data. + */ +void *page_get_target_data(target_ulong address); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e9de6ff9dd..7bcb6663f1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -113,6 +113,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2740,6 +2741,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2754,6 +2756,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2767,10 +2771,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p->flags & PAGE_VALID) { + ret = p->target_data; + if (!ret) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 810653c503..c693505b60 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -792,7 +793,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = h2g(host_addr); prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d182890ff0..bec2ab7769 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4625,8 +4625,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { From patchwork Fri Jan 15 22:46:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363790 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp269808jap; Fri, 15 Jan 2021 14:48:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJyjXy175r7VKNpRlVrYbkcFbhpd3ku9SinL0SfA2Hfme4gv+d/u+d6RMbmmWwD15yMOygvD X-Received: by 2002:a25:5052:: with SMTP id e79mr22427868ybb.51.1610750881865; Fri, 15 Jan 2021 14:48:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610750881; cv=none; d=google.com; s=arc-20160816; b=vqKpDJgbJShxaNPA5J1LdBCKmFt5VWDbwSCvPcaEyd/RRv46KUwou6cerb6huXYgGd ccsEhsxFnOf7TZ5iXPpT/7pvp6O5cPpFthQKtCYNt8J/qK6vXxaQQRcHaoDxpuwjm4nP U9BqtzJ6u6nbea23LycDdZgo4fa8dK7UZo61yljgrP/HHCuUV4iTO4XrOoE0+TNzwmv5 Aglouq99FdzQfgVmgASbXiZnEF98bGhk1YbONmW3DBlc1FyUQ3bSWsjap9W2iLBOStcF HGtzdvolS8yG0ag2OmpfifOi5zBzjJrvlvpxJ8/kxurKD/LmoUDpcJGP+BLVEeIsylJj euNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kyzjq96nH0KWrOiii6echH6ofV70lplGMBMMhcVo2Uo=; b=OBq7tQXwAhqgWtNhNi/dXVX1BW7Hu8fykLnRS/fa9yMGdcGYCuLAvRnLusR2vdUBWI wJNOLKZIR8DVlFZlte/B3Ebj1hHx8Ermu6wNelw4CPVubGGL5+fMLkJvp1jtjxZZHWfU r5nRX7Y1MBms6myexrgrceJ7dVxgQCU+Q0Mjuqf+s5ai1S0xPhIR21KQzRFtLm2UGbzm obEMSOHtADA5uIdzGdwOs9Ln1KUbMFqHBTC0l1dUvBcWWc70UBONw9qEvmr3KFa8altp KvyzOxxX1u8sGGDIsW32ofAXRWgPVZM0uonRz8RR6v6byF/yMj+l0XfQto3StOYXYjvv ch0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NZ6mpl9g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/21] linux-user: Introduce PAGE_ANON Date: Fri, 15 Jan 2021 12:46:26 -1000 Message-Id: <20210115224645.1196742-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) -- 2.25.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 99a09ee137..c23c77589b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -275,6 +275,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleared. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index c693505b60..7fb4c628e1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |= PAGE_ANON; + } page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: From patchwork Fri Jan 15 22:46:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363792 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp271324jap; Fri, 15 Jan 2021 14:50:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJysunPgkDbOxMuyOpm/US0mLTt8NROcUbg5Bq7cs4LqkcOtHGIVIZT6vy3AAr+C4ECnqXB7 X-Received: by 2002:a25:bfc7:: with SMTP id q7mr19653777ybm.130.1610751057437; Fri, 15 Jan 2021 14:50:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751057; cv=none; d=google.com; s=arc-20160816; b=w+7OR8b0LJ0kwhi4CriBxZD8JiNgOc9z383LLlTs/D60y+dW73HmMx1qzLVKY2RcL8 ZneTVGkrWJAr/QTD7cyRoyy9jpg/1m8llpJK77T3Zpy9UIVV9jRcxvdOLyvDttnbiYbh D3rXRu5rM/GApiEpuVhu1478X1E/V2IsY3f6OBEpSMPrz6YnVh5LXU58UQH8gxwMwSKf al08GIEZLJSnZCv7S7jBFyiCNBc1592L9dzQXM4dKd8tRv7B18F1tNhZk6m66ElGNvjF OSCg1UTdxrhWrbSKC2zX/HK2vXnxKNyIY5lLoAhwmNrXs9KVwzAFHAdXVm1rsz4g1fIF fJNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q6Vn8EuRt3zWEIGcR+Vsso1EpzS5NZb4Sjnv0xY+IUE=; b=Py61iV6eLpRlSVwtO86IV8baJQSH46mVLAOwztdqbQHrlrfh2fpM2X22UGSQkmCrYj 4RrTy0Iwzsw4NHIOq7JlRNZtZ+iCdNrwNxiM5K8vX1+rxv+D8hOOoMkPXmRs6d7BzwLx zCbndt3bPvIlIKzn/oQkc2QmaricH1FGF9EwuPZkBr+Wy2KfAi/Y9JMbX8MzBOw0sgX/ HWMDIK3/0BKvlmPcq5c4WiWZ8I5JqN5ZusuHHwlJ4D+nklL2OJ6bLyP8XHH4Xwg2Fde2 W+enK3s0Pk388FGFRsn+QSbT86cc+GraumnJZ1B14BqosOhptQpfNzwnTZcunit+3SY2 VVXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PaMRsJ4A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/21] exec: Use uintptr_t for guest_base Date: Fri, 15 Jan 2021 12:46:27 -1000 Message-Id: <20210115224645.1196742-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c23c77589b..c52180e8e6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -158,7 +158,7 @@ static inline void tswap64s(uint64_t *s) /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient location. */ -extern unsigned long guest_base; +extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; diff --git a/bsd-user/main.c b/bsd-user/main.c index 65163e1396..5c8e6a4acd 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -41,7 +41,7 @@ int singlestep; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; unsigned long reserved_va; diff --git a/linux-user/main.c b/linux-user/main.c index bb4e55e8fc..2600245300 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -58,7 +58,7 @@ static const char *cpu_model; static const char *cpu_type; static const char *seed_optarg; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; /* From patchwork Fri Jan 15 22:46:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363800 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp275516jap; Fri, 15 Jan 2021 14:59:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJzKFGIiFswqoy+sAXs33iV71LOsYvboB4RDXe6OQbNLLYGKN1rg4nDCFeZx+K1rfwsbnXqK X-Received: by 2002:a25:af0d:: with SMTP id a13mr22470724ybh.453.1610751565419; Fri, 15 Jan 2021 14:59:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751565; cv=none; d=google.com; s=arc-20160816; b=LDycb/r90IIhEgfHAIjSiI/4V0fbTUp2wWKRW6amB2+NhBxkNMeMH6Od5DsAGwmJRr 6ZcSIPy2awjK5hk4KW4MtWcoSQZoMEsOR2xw4kuEE1DqT5cFjRKl3rlMzzXjaz7YP31e G80dfiQ/nvPDyq64tmI4JVBqSK2b8YeAMxqMQyREjcJIR7SNDMDKb1G62nJPQj3r8YL3 1f/gPoluMVb01gym80wSeeAtGIDrgH2zOFDfE15XGDQsRJNc4odCL/wvROVvkzXpYS+b 3DZ1X6UyJYOvREOE4Jru3rEI44lWRnbmWIzNadESQ8uy6A7DEkp0qDC3PWSbhN5wBkfZ sz4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uDiO56BD9yBVu0nwAI/hhOcXCMAfaRu426dsljY4dMQ=; b=z14Ai3zu7GBHO4XNcJNGobgn6YJ4g8x+363MZ8smZFT0L9WFxuJBmpcu0aoHGbcM1W 2jSJWoUJiDt0dzM3XQhVkfBaikpkMBw2k28mcEwCWq5B8xGazJjdIo9SthFPyPhuKh6p Zfw3Lkol2UpZ3Qr0BICoXv0kuKtH/d6NwRed+vO0DBU3kiH65HiMqykWUoQsn0B/mgIW o/Cuqy1mA7i66Qwi2QTUamP49SElvDUkuuqtlNvAPwR248O4OmHa+LK6cJnUgx8r2UUK hFD2zO2+cVY8VHoRfr7U3bLIR0JlAjtpolIEzGKYcXbBUWje5QIowvXJ7JOTD1CHDOyQ Rh/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ii11emU2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/21] exec: Use uintptr_t in cpu_ldst.h Date: Fri, 15 Jan 2021 12:46:28 -1000 Message-Id: <20210115224645.1196742-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f..3f9063aade 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -70,14 +70,14 @@ typedef uint64_t abi_ptr; #endif /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS #define guest_addr_valid(x) (1) #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) +#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline int guest_range_valid(unsigned long start, unsigned long len) { @@ -85,7 +85,7 @@ static inline int guest_range_valid(unsigned long start, unsigned long len) } #define h2g_nocheck(x) ({ \ - unsigned long __ret = (unsigned long)(x) - guest_base; \ + uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) From patchwork Fri Jan 15 22:46:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363795 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp273365jap; Fri, 15 Jan 2021 14:54:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJwCqeI9QjsmvaMywOAv8fSqwDpOI2KFJSpr0n2iuaXO++spwXXDtOPFOLDk6Uzx+4xUmn2r X-Received: by 2002:a25:e047:: with SMTP id x68mr19416317ybg.347.1610751290540; Fri, 15 Jan 2021 14:54:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751290; cv=none; d=google.com; s=arc-20160816; b=S6FHTd9e2RClz8U/y1NsIdRchADeAlTgyajVs32JHntgSH1AVYubPmNe8l1+e5797r 6cX6URWyrURms9SnJCPBXpoLFriu6c2oZLtUBG/EjrnFCjQYRqPPPGKKeN/HHQQ3yUg+ zsg2S5Aq3PsBNeDY6yigl9d0zTXh0ArSXhNgLw/CZ/LdPdAuUSDKGFyGUukQxrg91Yob QgCYLbd8nvQH6RQ/qPb/3dIgHVNhrSFYhow3QSPkAChhBDFecjzlXPhBf1J8EhsN4cmE 97xNR1YxNop+YcHC4KdPkhqorZzDGixxlFkN4HysTz9aReF6Bh4ArIwN8qt0iSll9Sm0 jkmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BPFkHBCfiYE2/tooUwU3w49LVJJCP7NOmKVnwS50G54=; b=JNqpXPN0cehzyAgHZeggWxC+QHHp4VEWrz3kucVf7yviTzwtgaMxHVkuFd9516Iamp BgKoobDfrKIJK6nkpom8aCJLtJAzqw1DQFK7M2W8LS6vA6iqwBzx1S/533FjjM5Ss+r6 E+XbqTtx0BvKyEzuETh+NKpEaRclL3rgOO5Cf4EG+jnw14l+Yo3qpqlf+9j7a+G3yWRT pOq0GXEBI4qKREMYTEhL6jqfdhZG0oETBRHH1N61b7QBkpaa3nnsZ/YCR+lEkNhrMrdJ 1D4Hx/0/2kBQUOdemE2yVvtwpdc1aoN/YJZyVA79nhJ3t9/AzSjNKQnkC5MXqa4ptJhD cJ4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="cVKi/EO5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/21] exec: Improve types for guest_addr_valid Date: Fri, 15 Jan 2021 12:46:29 -1000 Message-Id: <20210115224645.1196742-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Return bool not int; pass abi_ulong not 'unsigned long'. All callers use abi_ulong already, so the change in type has no effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3f9063aade..5e8878ee9b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; #endif #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } From patchwork Fri Jan 15 22:46:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363793 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp272986jap; Fri, 15 Jan 2021 14:54:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJxjQF40DUSRsCaatduQ/Wedr7+CsOQVKKefZq+YBbJp+dRx5z+rpC3XKqLWzN8QD/eyMR43 X-Received: by 2002:a25:497:: with SMTP id 145mr19992592ybe.275.1610751249404; Fri, 15 Jan 2021 14:54:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751249; cv=none; d=google.com; s=arc-20160816; b=aNENPqEf8ai+T/PsgxBqID5Xv31S86lnfKFkBWWutvsESlTO+NoiK7fk2IzH3Z6+db BVDD71jed19w3/RGhz/YXNQT1UVKlSSh5baj1TJtfZKbzK3blx+3rjN7tClCl9YoDHrf aAyQXwJPJ2qw/ifa7bDTZDf5SCR5o30DIJL+R5iqZclMlvWJ93NBG5+Cu4y5EkkvOv04 grklkjFVxB9WWGPyLFaVyLudTtGrFJnoaGbCNNgzcAGkzSP/m91Dw0aHSKqX+0/5Z4p+ TvcrBqLOHCN28jXRjOG9/23f9kul350cdQpN0o+zekK4WxiK7ZG2zTpyjsE4nReuUTY2 G+ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rr4uhte3iLsKjX8Cbli6gBSl01cB/KM2FqNYctfYPe4=; b=OxTkt0sTSz6EWWSk3FsnT39rCCOrFd21BfxViZhkD6x8O2GrQUejIdvU5G2J7Ephvu k3x5BRiEt72iur9ZvBAWbfVV6dLBv5N89v1+MUDKbK7FtvMyZO4zPBaYroFqwnjW2Zaw twNEAoL1aFcagBU8W+T5jYzTPCv2p9loS0fZGvcu/arnFvlzSxoJkivjXaFiee0sEDr0 6+YHjYrCZNS1ITsc03c7dUYwU3296n8cMOYoa7k6YcZ2wJJ++ZISxnuoi2b1xEUi2WRn o/XmvbgYdHZRvGXlHCWGbAJhEBjoVPQinflX3GwxiwRV5miCE3o/wSaIrZZQZNjN9Y0q 1RjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZwiPCxB+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/21] linux-user: Check for overflow in access_ok Date: Fri, 15 Jan 2021 12:46:30 -1000 Message-Id: <20210115224645.1196742-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Verify that addr + size - 1 does not wrap around. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..a0f670832e 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -489,12 +489,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size == 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size != 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type == VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/21] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Fri, 15 Jan 2021 12:46:31 -1000 Message-Id: <20210115224645.1196742-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/linux-user/qemu.h b/linux-user/qemu.h index a0f670832e..329a6de669 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -486,8 +486,8 @@ extern unsigned long guest_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -499,9 +499,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. From patchwork Fri Jan 15 22:46:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363799 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp275498jap; Fri, 15 Jan 2021 14:59:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJzJ/aKo/3zNjh8QGqIKil19ZwXDydQmfoj4ZER8pkxmDO6P5mghnK6shKv10OfMBzk7Ouv5 X-Received: by 2002:a5b:eca:: with SMTP id a10mr14546603ybs.91.1610751563558; Fri, 15 Jan 2021 14:59:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751563; cv=none; d=google.com; s=arc-20160816; b=SlcxEW+MpSq72AbjPlrXB8uEbbwIHIoEzgxnTTjV+t9UfqnPbU/q+mIVaFKPiCGHUV uu0WN1yVuPfYrbndl+hwnsiRkEjwsQqgmMvQWcEEzKk5pxnAmHaFI9Pa4bDHjHOLfkr2 NLjEzbBeRkqFZjtGLo/zgrEOFUoqtGiHbGhFThICkeyiMxGHbuVYuS0h2xhjXQICIPAB TKsR69fySuVam55aURMKJX+GLgHDOzgWrv+Io0QJ8gJvk0glHuOUecIm5ka1K3Yne+1D kA6sqA/DYmAobTgoFhnMigRmiGONZg8yg8r5sUzy7LaEWECxa6quXkh7/Hw/4v8o0V3h +Mmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cekQQRp0i5HZWYUW7TcRhFHir1r8zA6FY8NgWmITL0g=; b=rWntz3zBFOwgzDRyud8Fyb3FIed8HSF9G/Mu9n3ObFuh3rJs6WvN6gEMLuCyepxAl3 GPJjFKaauqV+eLR4M5gjl84j9HRyx0GY2mFRAT5g896XBC+HFk+4rrNkAqZxolr9CQdw uC4QM7HYYhslcakHWkbQRFfd1yTD9HUyrc8OtdlosvzztwHqAQZgMstsMvMEN+eufOT6 FTJ07AZR/vvXo4tr2STShZWVAQFecM1tICVTkl3N1tqfQDs+QaUi8baz2C7Z1fTzwDwl RfiFh7yepH711DKycuOXfm8O1MRU9ne5XMRS9kdzCvoHCiCm/xm0ADd8jgsr4Iu5O1cw XWTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jWLwcRYi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/21] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Fri, 15 Jan 2021 12:46:32 -1000 Message-Id: <20210115224645.1196742-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Warner Losh Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

This looks OK to me.

Reviewed-by: Warner Losh <imp@bsdimp.com>
 
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459..4076adabd0 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. */ From patchwork Fri Jan 15 22:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363798 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp273788jap; Fri, 15 Jan 2021 14:55:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJz9ITX80c60w6K1LXXrzx5bIF3kyhcOwarlaZU88v2/HnYL0ojajGv5/VcHAhJfIqHTT/7Q X-Received: by 2002:a25:73c7:: with SMTP id o190mr4634567ybc.482.1610751340231; Fri, 15 Jan 2021 14:55:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751340; cv=none; d=google.com; s=arc-20160816; b=eJTvLC1U8e6IrYIMdh/3mxQc6r1cvaS4/9cUTQCvv8txliv9WlXTbFoQE7f6AYAG5+ rqPfXbKAuyXYOJowZuVm1ygzqqrei/sD3u2P0SpOdT+lxlHLXb3UXS2fqKN5THDgURKo sssbnSCAljAN8sQPjoQqE5lbGH5THsojP+YycCKJ3+dlcDRZOFv5l4fzzj+ZYHdquGa1 jPqujbWuYpA3Gn1f3DE/ja9Z0eowdJZ4ew/qY4ipJcaHA9PYzXvucKkOiMTBaJa/4dES Oj6BkQf3wqeXodSdd7yRWwu/QYEdlfoBNG7sr3zSAbwdVKWDVIonwGUXER7johigJjxU /HUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4REF6cfdA8MQv8viPXefMUo/38x0z3uSDZzFVOD3Xwc=; b=ztmvYZRpp+O8xoI4ZB2Rr7bYRyoMzhldYCi/y1nfaKkr3j0f5fDZEiQ6FPelXyP9pQ kmq7LNUkzC1LM4xVLmaQIg1wwxbjo+M8b8wTsAYMqhrv6b0253p6mCtvoKtgZPixYXqm g8ZCOPDWqPLevGxxzHQxwtJv/Ybw8+WBF5am4cIv1epodG8HPQyna+nafRvvrP6gNgCX 8JVkGSc9YC98jL6lRvs2RGF/0doUD4I++hxk4YkDKFDuqlqfRzx9DtsVl4KLqIb1WTJX DpDdIa5q2vQPh7b0DWlD6CHDVJhTzBPHdwo1tXbHsIIUUIDLsbhmfl3lF+/rWSt1pDPR bOIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yKJEbBv+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/21] linux-user: Do not use guest_addr_valid for h2g_valid Date: Fri, 15 Jan 2021 12:46:33 -1000 Message-Id: <20210115224645.1196742-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Signed-off-by: Richard Henderson --- v3: Ditch type changes; retain true for HLB <= GAM (pmm). --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5e8878ee9b..4e6ef3d542 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,13 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } +#define h2g_valid(x) \ + (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ From patchwork Fri Jan 15 22:46:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363791 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp269819jap; Fri, 15 Jan 2021 14:48:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJynS1jAJVaLQ62Wti2EWN4mHwLnwbsBph54sFiqAEO5UwilVuF8HFbe9rX8bQ2lbiDJ/l3Z X-Received: by 2002:a25:aca5:: with SMTP id x37mr21164651ybi.392.1610750882984; Fri, 15 Jan 2021 14:48:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610750882; cv=none; d=google.com; s=arc-20160816; b=jKUDt++YWpWel++/M9oNlsjG6niwt4RyQNzd0BtikXwlbqBD16sBEN776B3Ngpwu+S xlrNMHA2An+4Ak7+a3HpUxH/UbunUxNuzX7u32H6GAkNmpcH23ky/egaNUAS79SIhKMR 1auSS83mqRda8nJNnbrQftYeqUtKf+lJHMWHvahJzw0jPkxtGiFA0Nmq3ImeuyXDRgJf YRUB28jtj8daIYxGkytpe1347Jg0ZAezKXx6kcwOHQZY2fwJTQoDc0J4YtcModemZ46d 4oGgcZZTRJ+hdqe5JeGtoIc6dlibvBdasiE7PWvnQEHao0MYK5Z1iyWqMxQeev+tmSzQ to4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XRNC7TN62/mhJ44h4TxsBn3p8qzX1+L1EKv8lKpxGuM=; b=CNCgWY0J5P0SRo8WWtjP1gDNtg3Byjxn118tuT6x9cmRqqSXTxd7U/8On0GG0k4rH5 oZgcgK4HEA2f3dY5Hjz3gZI01K1Zz313Ira7AYgEMLv3hUa4L68oOBJAAyeumDdGCCVW cLFpmc7fUHwkLJrcJELI7DWMlLeuDA9Bg9a+khrwij4o2QA9lm27WaYVJkFvlC0DUhIW KUTrxJQzB1lLYRt2Zm254zQkOIlZuORYvzAFgcTwXK75yF9sXZzACrO5RwQdAfMjcZO1 I9X87T2Uo8nGgTrpRsXfA310xQhZbMOA2Ui6xqClkdZrmGa7LydTrxz9sVLxyXoJfdYG DQKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=O2doYa6y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/21] linux-user: Fix guest_addr_valid vs reserved_va Date: Fri, 15 Jan 2021 12:46:34 -1000 Message-Id: <20210115224645.1196742-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 4e6ef3d542..e62f4fba00 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ulong x) +{ + return x <= GUEST_ADDR_MAX; +} static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { From patchwork Fri Jan 15 22:46:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363801 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp275741jap; Fri, 15 Jan 2021 14:59:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5y5vpjPSXhknHyoReekW/iRoztK2ccXQM1FbXyNyXvCeEd0ty+knLKpNAGAHjN4qHit4H X-Received: by 2002:a25:d1d6:: with SMTP id i205mr20869069ybg.199.1610751593989; Fri, 15 Jan 2021 14:59:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751593; cv=none; d=google.com; s=arc-20160816; b=CCziObgjAj/JbWXCfqGa0GQDOXeCO/hXyiaY+2cZI9Ny0RTNTff8i3ot42JoTxL6cU k4hpl8iCRsLgwz0tkPrfTcqgFOj73jS0GiGVE2xeKbNov//D2NSVTHglfHsn0gCD7Rcw A9VPPtH2G1ZUGfTH0diRBykh4giXR+BV5nd59e5+EsyHrjdPKqO04P1Nd4vqtTSKVlYo wd7WyEiFsr7CVMGdR0zX9qJb1krX3mu5of3k4YkOzrwJZQU8R7r2MjzfvGE6v6PmHWyv NvBrpoqPgN0U2/+oBnaJiGPH9sd7FehtDh0RaSDG9pp1i9op/+VoSl2KV69Lxs6gV7YU Zeug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X+LaZKuwwsvEvbJ+r5ztAOZO016eLRKSU8aYWIJf1AQ=; b=XBMqrriPNqz1aXBkyI9slNenZt01pq7cVFjnxS27m8xNclst87J+2SR4jfoK79lKmt Vdu0SzvuajQfM8iMs20biRYqX2rgl8GuL6DuyMxj91CE6Lmb1OAP7dg8LU+ylW+kUc8B IfJFkSxDeQPZW740JD3uCPUZLDVDiBoNL/rSnzOYsf0EocounJjsK+S5bagfhebSzcDA XDGD4sec/aawUs0gO3jSGrP2u+6avlGdGVqjze/VMQtsS7TwUawNSL2+7IIbMY37wJLy OpF6u+bUxRhaOurMG8qXjVt75yhEE5mMWHzwNH5z+DD62VQMeu71IJPeHJx76bJ9iqtB PERA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LcG7qzDJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/21] exec: Add support for TARGET_TAGGED_ADDRESSES Date: Fri, 15 Jan 2021 12:46:35 -1000 Message-Id: <20210115224645.1196742-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AArch64 Linux ABI has always enabled TBI, but has historically required that pointer tags be removed before a syscall. This has changed in the lead-up to ARMv8.5-MTE, in a way that affects the ABI generically and not specifically to MTE. This patch allows the target to indicate that (1) there are tags and (2) whether or not they should be taken into account at the syscall level. Adjust g2h, guest_addr_valid, and guest_range_valid to ignore pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok in the arm64 kernel source. The prctl syscall is not not yet updated, so this change by itself has no visible effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e62f4fba00..1df9b93e59 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif +static inline abi_ptr untagged_addr(abi_ptr x) +{ +#ifdef TARGET_TAGGED_ADDRESSES + if (current_cpu) { + return cpu_untagged_addr(current_cpu, x); + } +#endif + return x; +} + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) +static inline void *g2h(abi_ulong x) +{ + return (void *)((uintptr_t)untagged_addr(x) + guest_base); +} static inline bool guest_addr_valid(abi_ulong x) { - return x <= GUEST_ADDR_MAX; + return untagged_addr(x) <= GUEST_ADDR_MAX; } static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { - return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; + return len - 1 <= GUEST_ADDR_MAX && + untagged_addr(start) <= GUEST_ADDR_MAX - len + 1; } #define h2g_valid(x) \ From patchwork Fri Jan 15 22:46:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363802 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp275754jap; Fri, 15 Jan 2021 14:59:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJwYnNickDFuvb1jQX3CWCiPY0OA06YHD4HICfqg6R2rQvCaRZ71SU1uoAYJqT9M3GzRUJSc X-Received: by 2002:a05:6902:6d4:: with SMTP id m20mr22017424ybt.434.1610751595102; Fri, 15 Jan 2021 14:59:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751595; cv=none; d=google.com; s=arc-20160816; b=w7DvBxxWso8lDHRIezmalE0iyo93bLzu/MKe3DXniG1aE5tjf1jXYUEJHvfSDwyr+V bafjEt2gW6SZKiUIzCPVq4DjnKAIFwYYJnKc9y0Hrvq19VKTjiQT7yxyBVUCYZrPhCs9 50DFGnGWy2iDCoGOdgKtYEfs7/FM7dn7CVpM+zIgRIZ+90G8oG/1U9EMcPulN+aUziEN dkei2ZWy7HSdpYF+MyNJizqGxblLSKpTWIjXYYsufoiVy8Xagzif78NkzU29TRlt9Fla cU/MLhzcfPmXJDSmUE+K32Bi1GrjUX3t8+//OvdVmuQDMs5kMhOAZQpAMOBA1apY4Jda tz1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kevGJM1Q+4BI+TG/qeyrIdbD80I/diyx5FwIEqL89Lg=; b=um95svJK9mDfjTho3xWZstVGGscJT9ekJi73bOX4qlbcrQ9Pdb0zZgfON01oPGX6Op CVOtxCep5A33Axbw3ZJbWu8Q8BYcnDS5bbT28sn6BQkXN2/npr9MbbcEaOfx80pyEojT RdL20WL0Vu/2c1BtQaIPTtWGFj2p0ndMFRMT85E1XNNvxFaCtOYzXwhYY6tsslYMgRp4 g8ElnboJLeX98ANJTideS0w532fIGWkljo+wfqFF8/OBxQj1QrdCrXCf4fIMiNmXSxr+ Qw+dWd0vzaALvyltwmy7WfFViZLFWd96JxOdfzfTtQt+fwpR9LS0srWmPW12c7pP/Lei 7hjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yjl20JCz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/21] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Fri, 15 Jan 2021 12:46:36 -1000 Message-Id: <20210115224645.1196742-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 4 ++++ target/arm/cpu-param.h | 3 +++ target/arm/cpu.h | 23 +++++++++++++++++++++++ linux-user/syscall.c | 25 +++++++++++++++++++++++++ target/arm/cpu.c | 3 +++ 5 files changed, 58 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 3194e6b009..820601dfcc 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -30,4 +30,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6321385b46..f922aa0650 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3bca73d98..6ddfd9ebe6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -712,6 +712,10 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + +#ifdef TARGET_TAGGED_ADDRESSES + target_ulong untagged_addr_mask; +#endif } CPUARMState; static inline void set_feature(CPUARMState *env, int feature) @@ -3556,6 +3560,25 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) */ #define PAGE_BTI PAGE_TARGET_1 +#ifdef TARGET_TAGGED_ADDRESSES +/** + * cpu_untagged_addr: + * @cs: CPU context + * @x: tagged address + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + */ +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) +{ + ARMCPU *cpu = ARM_CPU(cs); + return x & cpu->env.untagged_addr_mask; +} +#endif + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/syscall.c b/linux-user/syscall.c index bec2ab7769..ebb4e2898c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10948,6 +10948,31 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env = cpu_env; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + env->untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE + ? MAKE_64BIT_MASK(0, 56) : -1); + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret = 0; + CPUARMState *env = cpu_env; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (env->untagged_addr_mask != -1) { + ret |= TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..abc0affd00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,6 +208,9 @@ static void arm_cpu_reset(DeviceState *dev) * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); +# ifdef TARGET_TAGGED_ADDRESSES + env->untagged_addr_mask = -1; +# endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { From patchwork Fri Jan 15 22:46:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363807 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp281356jap; Fri, 15 Jan 2021 15:08:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxiKx8hRK/Wl45okgY7VmG8153EC0uFMNiV9OdbekZ/w2JixDry09uiX4pjygbLzhUelo9R X-Received: by 2002:a25:ba0e:: with SMTP id t14mr15317450ybg.203.1610752111485; Fri, 15 Jan 2021 15:08:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610752111; cv=none; d=google.com; s=arc-20160816; b=EMMev8CQ1tLdK6M2fMRLGXAtJS33teUcMrEfDGfuAqxxJX/fTd0KRdAJGqZ3vOO/bk pWqqh/wpT7JXT7IH75EEaI39P0y8KriIBXMkIMzUzlFITHur9lvQ0qOo1ghNSY5BuZ0Y RfA+qdqcGIGkusjD187JKv9pip5aEVZ7k1wOwUq48YFpP/gYCMX0Th2JZq5dswaFtzcY tNDj3gfYgGq8qh+0ULWUvjfkDsU93fzspIhFP8i778+wLrd8ZdLI3FdCg8uvtYTbtwMN 9x96rdPO/XR+PoFkb4n+8rkMO6STm5FwsOTnHOgWBPgWvejs7ZJKbjWR8vFbgQNEXvBT tU4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tHmvo/lrgkE+wi7yTJ56b6ape2S0MwV/XIHtk24Q15o=; b=ouk/2p+eQXtr0OsOhVKGOXhfrsSCBuNrCBmVPfs/F3Gxl9iO3HbRDLm3lNBoRlV9tP 0vOJS/nPdRmUuLkMT8KWfwql/EKhO2eh0yppLW3GTHZUNfoBFSf5eWl3mbbK1vf6o1XP w0XbMw78PWZzQIFok34saYhq6A6uxMv6LhUs7jRmG0aaS0mQZVx8GQ0KkwyTC2GjK2M4 TOTWIVtRno/++ScnqX4JVEWC4K9fyONgbnB6qIIjfMzLqcTXrjqdWAYrzdQb6B8UKYR2 /TjTu2OjX2aYnCStA5GC9Ca3/kqDJK83nLGvddX0dDFICOlc4M84+Xmde+nO2oarf4UX ZNtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PVQmPkDZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/21] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Fri, 15 Jan 2021 12:46:37 -1000 Message-Id: <20210115224645.1196742-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These prctl fields are required for the function of MTE. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 44 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 820601dfcc..76f6c3391d 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -33,5 +33,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ebb4e2898c..0316497636 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10952,10 +10952,46 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= TARGET_PR_MTE_TCF_MASK; + valid_mask |= TARGET_PR_MTE_TAG_MASK; + } if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + env->untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE ? MAKE_64BIT_MASK(0, 56) : -1); return 0; @@ -10964,6 +11000,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { abi_long ret = 0; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -10971,6 +11008,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, if (env->untagged_addr_mask != -1) { ret |= TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ From patchwork Fri Jan 15 22:46:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363794 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp273009jap; Fri, 15 Jan 2021 14:54:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJwMrVNaeGa5a/ZUMzmr5BGWr2PB1ua9FNwR+BbwUk9TgpIRO492I8nMNJiNvGUPekN5esqZ X-Received: by 2002:a25:be44:: with SMTP id d4mr21867923ybm.219.1610751251300; Fri, 15 Jan 2021 14:54:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751251; cv=none; d=google.com; s=arc-20160816; b=TE3+c4+7CRhk3rwVdZEIWELIs2lNNDhqBB0EgzgxPcSGfhqKzyKRoWuAvF55sWXYLN ORcew82erWhxuk5sCb+THaI+OnWPgOGi2C+M5x+AC2bS6CQY3UXu79RbpZL5iBYpi+kk qWj2aNDDwQ2+Z8U3rDt6fgY8Qr1K54xRXk5DG9zmOz+f/ILolpsTFaxKMxTySNFeNc62 ZkxEk1IjvV6Bznk3mc2mugk7qOOsePbCjrdVBFVXmWXTbWMIkoNFBRnJPGqx+6Zh/3Gv f6RIQRgNge/hOD7uFjTtb8rz5zQoIZ/VStDg8/d4ykI5r11tpQvVCC7Q8xv4E+ignaky LF3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Aw5WXq5wBceHp2TEFV1G5r+xP2Xi/95Oor9t7natYrU=; b=AEpVw7HrOJNfiO8MExSY+SyG9+HxKokQB9o2D8+dzVcp9e4p0PwrE39FARDDvoV6hX XOrX/COgpXh6XiGePkoztZTK6rdgmFcOBp9yVLcVbiHOHJADAxl+pHI9CoMoZtfahVns Z7O+ki3YvJOoMLhdXVby3t9y3M1/f+72RuiGQvnAxO8HyJblVxkQncdLSW20giG3KZJc V9Lq7Xqp7hp8GlCFx28KKa5+v2jdYzjAGISWBxvTqJsmi6MJpBSDn70iJJWa0HgbmY7A VQz8Vct/BXiXMyJhxZ4DDulr5cVU9G/FXBF7qkBhgppOAKXqMNlGqiTnZCEAkKjo6TaE 7RYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TRNBEliC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/21] linux-user/aarch64: Implement PROT_MTE Date: Fri, 15 Jan 2021 12:46:38 -1000 Message-Id: <20210115224645.1196742-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2. Otherwise this does not yet have effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Do not overlap PAGE_TARGET_2 with PAGE_RESERVED. --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + target/arm/cpu.h | 1 + linux-user/mmap.c | 22 ++++++++++++++-------- 4 files changed, 17 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c52180e8e6..b2a72f70ec 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -284,6 +284,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0200 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index a00bfc2647..0d6bb1ff8b 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1311,6 +1311,7 @@ struct target_winsize { #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif /* Common */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6ddfd9ebe6..e14c9a6277 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3559,6 +3559,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ #define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 7fb4c628e1..34bd114f97 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,24 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) | (prot & PROT_EXEC ? PROT_READ : 0); #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu = ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |= TARGET_PROT_BTI; page_flags |= PAGE_BTI; } + /* Similarly for the PROT_MTE bit. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |= TARGET_PROT_MTE; + page_flags |= PAGE_MTE; + } } #endif From patchwork Fri Jan 15 22:46:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363806 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp280431jap; Fri, 15 Jan 2021 15:06:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxaPb8LexrRHAYVQBXQPBUyPRMzNfbw31/axuyVaF2Nii8Dw1jpFobg9WFWy8QC0++PLlJb X-Received: by 2002:a25:2f91:: with SMTP id v139mr22342227ybv.491.1610752016441; Fri, 15 Jan 2021 15:06:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610752016; cv=none; d=google.com; s=arc-20160816; b=e+qFB6ARrG+my5/q3rg5Wk6Y6QMsjRm9fnPhjJeTOlVoNxxTfbcw49EM7Zql3aw7up ka7RMxORYtJ2mlqBaRNzeAku29RU31olj9obpV4TDkpiOHfKi8g95pQfvYwkg7QFfpgO w+wpOpVT60MTqq12SHYqTxNmDI3JZ6/AtDAOony0H6vlYO9tywucZREGL5rDyTLiPo0i Uvz1qd+P3mGIJE9mgcG2BTZBU4HvmId/6sVLeJ8JqGgeG1S6RCPrbzNTEZGPwPvtaHeg XshONpdaTbOdvwnF0eumUH1oKkLlrleM5ntGEMzVX5e4udO4ybqak1lT03sFr6/TiwtP 2Auw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0M+ib82Q9NUsY8Zir/mvOr8pifWIKMIlNlMsQviVw94=; b=vvx2b9BLy04qYKzITfsNV+fgSe9Bxe1yBdvsQxPQzVjCXTf7KJSb4FToON2lY7MXqy +D8/7CGmfINZCsc3EqpnWL4nEEIBZB4CUlO2YOrFu///v4liDbjHswIikSmyYVfnHur8 Vi2j/6F3gJl0WkopQfw/ufg3lfYhqAS6DGBEMkM8EeNo6D3kaxRKnqBkJPYoAL3L8TRC o0Q5LS9m/b6Z3gOVYOG16ylw/usQpJU2mVnfZulpTiRYan/jvK2ChD+5PjZdIuxzRk8h AkTKBs8LuHk8BmU12Gl1jS+BsJDFdxcD3A/OCTI45isUlicrN3bjCs78I5HQ1hhnpI0y N8Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bvYoZzrU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/21] target/arm: Split out syndrome.h from internals.h Date: Fri, 15 Jan 2021 12:46:39 -1000 Message-Id: <20210115224645.1196742-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move everything related to syndromes to a new file, which can be shared with linux-user. Signed-off-by: Richard Henderson --- target/arm/internals.h | 245 +----------------------------------- target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 244 deletions(-) create mode 100644 target/arm/syndrome.h -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..1e60c0e0e8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H #include "hw/registerfields.h" +#include "syndrome.h" /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -256,250 +257,6 @@ static inline bool extended_addresses_enabled(CPUARMState *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); } -/* Valid Syndrome Register EC field values */ -enum arm_exception_class { - EC_UNCATEGORIZED = 0x00, - EC_WFX_TRAP = 0x01, - EC_CP15RTTRAP = 0x03, - EC_CP15RRTTRAP = 0x04, - EC_CP14RTTRAP = 0x05, - EC_CP14DTTRAP = 0x06, - EC_ADVSIMDFPACCESSTRAP = 0x07, - EC_FPIDTRAP = 0x08, - EC_PACTRAP = 0x09, - EC_CP14RRTTRAP = 0x0c, - EC_BTITRAP = 0x0d, - EC_ILLEGALSTATE = 0x0e, - EC_AA32_SVC = 0x11, - EC_AA32_HVC = 0x12, - EC_AA32_SMC = 0x13, - EC_AA64_SVC = 0x15, - EC_AA64_HVC = 0x16, - EC_AA64_SMC = 0x17, - EC_SYSTEMREGISTERTRAP = 0x18, - EC_SVEACCESSTRAP = 0x19, - EC_INSNABORT = 0x20, - EC_INSNABORT_SAME_EL = 0x21, - EC_PCALIGNMENT = 0x22, - EC_DATAABORT = 0x24, - EC_DATAABORT_SAME_EL = 0x25, - EC_SPALIGNMENT = 0x26, - EC_AA32_FPTRAP = 0x28, - EC_AA64_FPTRAP = 0x2c, - EC_SERROR = 0x2f, - EC_BREAKPOINT = 0x30, - EC_BREAKPOINT_SAME_EL = 0x31, - EC_SOFTWARESTEP = 0x32, - EC_SOFTWARESTEP_SAME_EL = 0x33, - EC_WATCHPOINT = 0x34, - EC_WATCHPOINT_SAME_EL = 0x35, - EC_AA32_BKPT = 0x38, - EC_VECTORCATCH = 0x3a, - EC_AA64_BKPT = 0x3c, -}; - -#define ARM_EL_EC_SHIFT 26 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -static inline uint32_t syn_get_ec(uint32_t syn) -{ - return syn >> ARM_EL_EC_SHIFT; -} - -/* Utility functions for constructing various kinds of syndrome value. - * Note that in general we follow the AArch64 syndrome values; in a - * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, and we fix this up when populating HSR in - * arm_cpu_do_interrupt_aarch32_hyp(). - * The exception is FP/SIMD access traps -- these report extra information - * when taking an exception to AArch32. For those we include the extra coproc - * and TA fields, and mask them out when taking the exception to AArch64. - */ -static inline uint32_t syn_uncategorized(void) -{ - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_svc(uint32_t imm16) -{ - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_hvc(uint32_t imm16) -{ - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_smc(uint32_t imm16) -{ - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa32_hvc(uint32_t imm16) -{ - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_smc(void) -{ - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) -{ - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, - int crn, int crm, int rt, - int isread) -{ - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; -} - -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 SIMD trap: TA == 1 coproc == 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); -} - -static inline uint32_t syn_sve_access_trap(void) -{ - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_pactrap(void) -{ - return EC_PACTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_btitrap(int btype) -{ - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; -} - -static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) -{ - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; -} - -static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, - int ea, int cm, int s1ptw, - int wnr, int fsc) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; -} - -static inline uint32_t syn_data_abort_with_iss(int same_el, - int sas, int sse, int srt, - int sf, int ar, - int ea, int cm, int s1ptw, - int wnr, int fsc, - bool is_16bit) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; -} - -static inline uint32_t syn_swstep(int same_el, int isv, int ex) -{ - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; -} - -static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) -{ - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; -} - -static inline uint32_t syn_breakpoint(int same_el) -{ - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | 0x22; -} - -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) -{ - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; -} - /* Update a QEMU watchpoint based on the information the guest has set in the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h new file mode 100644 index 0000000000..39a31260f2 --- /dev/null +++ b/target/arm/syndrome.h @@ -0,0 +1,273 @@ +/* + * QEMU ARM CPU -- syndrome functions and types + * + * Copyright (c) 2014 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + * + * This header defines functions, types, etc which need to be shared + * between different source files within target/arm/ but which are + * private to it and not required by the rest of QEMU. + */ + +#ifndef TARGET_ARM_SYNDROME_H +#define TARGET_ARM_SYNDROME_H + +/* Valid Syndrome Register EC field values */ +enum arm_exception_class { + EC_UNCATEGORIZED = 0x00, + EC_WFX_TRAP = 0x01, + EC_CP15RTTRAP = 0x03, + EC_CP15RRTTRAP = 0x04, + EC_CP14RTTRAP = 0x05, + EC_CP14DTTRAP = 0x06, + EC_ADVSIMDFPACCESSTRAP = 0x07, + EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, + EC_CP14RRTTRAP = 0x0c, + EC_BTITRAP = 0x0d, + EC_ILLEGALSTATE = 0x0e, + EC_AA32_SVC = 0x11, + EC_AA32_HVC = 0x12, + EC_AA32_SMC = 0x13, + EC_AA64_SVC = 0x15, + EC_AA64_HVC = 0x16, + EC_AA64_SMC = 0x17, + EC_SYSTEMREGISTERTRAP = 0x18, + EC_SVEACCESSTRAP = 0x19, + EC_INSNABORT = 0x20, + EC_INSNABORT_SAME_EL = 0x21, + EC_PCALIGNMENT = 0x22, + EC_DATAABORT = 0x24, + EC_DATAABORT_SAME_EL = 0x25, + EC_SPALIGNMENT = 0x26, + EC_AA32_FPTRAP = 0x28, + EC_AA64_FPTRAP = 0x2c, + EC_SERROR = 0x2f, + EC_BREAKPOINT = 0x30, + EC_BREAKPOINT_SAME_EL = 0x31, + EC_SOFTWARESTEP = 0x32, + EC_SOFTWARESTEP_SAME_EL = 0x33, + EC_WATCHPOINT = 0x34, + EC_WATCHPOINT_SAME_EL = 0x35, + EC_AA32_BKPT = 0x38, + EC_VECTORCATCH = 0x3a, + EC_AA64_BKPT = 0x3c, +}; + +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + +/* + * Utility functions for constructing various kinds of syndrome value. + * Note that in general we follow the AArch64 syndrome values; in a + * few cases the value in HSR for exceptions taken to AArch32 Hyp + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra coproc + * and TA fields, and mask them out when taking the exception to AArch64. + */ +static inline uint32_t syn_uncategorized(void) +{ + return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_svc(uint32_t imm16) +{ + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa32_hvc(uint32_t imm16) +{ + return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_smc(void) +{ + return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +{ + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, + int crn, int crm, int rt, + int isread) +{ + return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL + | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) + | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 SIMD trap: TA == 1 coproc == 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); +} + +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + +static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, + int ea, int cm, int s1ptw, + int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + +static inline uint32_t syn_data_abort_with_iss(int same_el, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, + int wnr, int fsc, + bool is_16bit) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14) + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + +static inline uint32_t syn_swstep(int same_el, int isv, int ex) +{ + return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; +} + +static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) +{ + return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; +} + +static inline uint32_t syn_breakpoint(int same_el) +{ + return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | 0x22; +} + +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +{ + return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | + (cv << 24) | (cond << 20) | ti; +} + +#endif /* TARGET_ARM_SYNDROME_H */ From patchwork Fri Jan 15 22:46:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363803 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp278284jap; Fri, 15 Jan 2021 15:03:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJyXlEeVdtX+KxNSQaAWB8OFjuC8JAGXN1nEsQU6C5mAtGqBSu+7vc4fe0Sfld1C6Bv/DYFY X-Received: by 2002:a25:dbc4:: with SMTP id g187mr22742012ybf.489.1610751810702; Fri, 15 Jan 2021 15:03:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751810; cv=none; d=google.com; s=arc-20160816; b=oM3R0AEFDYbvibwSifGO3gUYaJcNPxJUdxc6L5JccZafMGyGNkvtNBpxbsVoSgwQJ9 cQARtuIWP/u5xqaTIrhQ3eyaXPeh+FYWQ1mEiKNwATwEuNDF53HuMpW2PO/LYYWMZSGX mjLkOkuJ21JS9wchtgGafsUJBt6LHlulQS5xE1B2E80LKGVqi3bBBQA8YTzhHZ3iyQfH U2ZVy+YIavRE5sHvYCu7BnpFI5xrLYuhCqIepURI9GrcOvE0RS1WOCfbVvy9sHFd5JAD /AUKv0DG58X1X94teTc1OhqpgZb1zVF5zCWi4Ob2txEH71ffIwxgJHEXZimtMDh7f0fo 9U/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ag2kKkF2C6qi/FIsLVctK/0CDxQoX8dZZ8rQ2H49Ggg=; b=XJLyu2cyK825vo1m/SzRx1mI4lLFT8La4SAbYTduo5uGmhX6c7VBKyna/WcY+ot+KU evz+BJv2s3WwxFoHUYpkPWXEriWVE9A92Fy9i4EwwW+bSJ8+/Grq9BlDvrHnc9jI83oH tX097Q5F3G04vKM7hs1wXQ+ohBkwPaoKxbKbbdSEdVhtPXRw4smFJLZysRGmBUc6n1fH Vw4gh4I8qArWJ5kvFbN4vAGE1h0dWUV8iM64geX+dK3da68ouiwtxerf14HjL7NWQ1nY NA0+bFMMecgknrhQjiQl5zrUYv2PxQJ0OO5kdHjUvTeNu8YhADWGdbgN1tQ3ezfeK4m8 YyeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RMZ8WirJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/21] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Fri, 15 Jan 2021 12:46:40 -1000 Message-Id: <20210115224645.1196742-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Signed-off-by: Richard Henderson --- v3: Use syndrome.h, arm_deliver_fault. --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..7811440c68 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -75,7 +76,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; @@ -116,9 +117,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ + ec = syn_get_ec(env->exception.syndrome); + assert(ec == EC_DATAABORT || ec == EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code = TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b35dc8a011..31015749fd 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -151,21 +151,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress = address; - if (access_type == MMU_INST_FETCH) { - cs->exception_index = EXCP_PREFETCH_ABORT; + int flags = page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type = ARMFault_Permission; } else { - cs->exception_index = EXCP_DATA_ABORT; + fi.type = ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs = {}; - ARMMMUFaultInfo fi = {}; ARMCacheAttrs cacheattrs = {}; /* From patchwork Fri Jan 15 22:46:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363796 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp273549jap; Fri, 15 Jan 2021 14:55:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkkOqYlVI8k5VIOxhAkRwKwy9AVmsgSkW5KoAqwWDMkYqgqweEnslvv6xBCZ/ZgsFr04lL X-Received: by 2002:a25:678a:: with SMTP id b132mr22094539ybc.516.1610751313950; Fri, 15 Jan 2021 14:55:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751313; cv=none; d=google.com; s=arc-20160816; b=tVpP+4rgehYdUUlRt3RxFEeYTj4keZ6/+IY7oThopRH+2Twe7yknmn0piIzyjIAsQt 2Wc0xuG31S34C3BGWLs+t5W4JDWfELPc5JtDcjVnXHEwiO7MAWaUIG5ccT7Ssr2R6ZQN dUABmT6GB8Udoz4/3gNNQyZyjJgKhHl/L3BvoZsvOI2OterCZwKPQer+YLZHwhHjNx8a NJE9N5A4UAEukPi6MA7ZKk1QmDW3NTvKLZWc27eKM0hsTxHMIJSZAKP4VgeqRe0fOEv8 pNjZiNbdbdWSL1vcffN8sbq7U5okxc3wIuSx23scBnwwyDOiWuuLN8oHS4cudyY4jI7j yPuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6xhR+Wss/1TBEEfYwI3TvMrUfFA269smX1ho0M9IxOI=; b=Re4NnJIpyPncD64RebbHBjXQprIR1pOZEvMQ/taV/n3ug0tMk6k9qFQ0+N5tOXEHoe u+nvDF+OVyjg5WW2fcfKtf9Lw61xUKQUjNoSgICnNLIJYKnRbmoFmP+Uy2zIAB8+QjTF LTa4vqtK2jwQ8Zq3kBSK91aAnowApfEkc2arfgWC/KMlgJPYR3ql8Yv5MXqlGXDp2cvz uAhkMGTiFka/PLIK98FTT4sHkxFhqlwRYcfCFFX9B0etna13gzyqvTN6nx49//ZuMpcV jOaGVzzdhSAji/NL4JziF0ZL1pScTF0y0jT9RcOKxt8t0e+FBgRXH0IjDzXdbdTeR/QO muLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JnQ8QGg4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/21] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault Date: Fri, 15 Jan 2021 12:46:41 -1000 Message-Id: <20210115224645.1196742-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index ddd73169f0..777fb667fe 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 7811440c68..6867f0db2b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -133,6 +133,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code = TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code = TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } From patchwork Fri Jan 15 22:46:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363810 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp284193jap; Fri, 15 Jan 2021 15:13:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJxtfhS62O+ro5KGBWkdHsEsktzqeyW/2i154Ac8xIR9CPxaw+3DltDqEY6aw2+pQCmughEq X-Received: by 2002:a05:6902:703:: with SMTP id k3mr21863068ybt.88.1610752395077; Fri, 15 Jan 2021 15:13:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610752395; cv=none; d=google.com; s=arc-20160816; b=qOoYD6m+iOfKD1OVy1JSQGZ1ATndQ4oLtKWutyzJQaYN6twt1cBnbkZT7P4qlbORgJ OAnWPtJXA5zTCaWxgr31EWNuiqPJZWUK8/S+1kZjprz7wwG1sGxcTHF544+bXhTNBjd4 pAzbb+ERUJB/3anMrGwkrvzvVLaC8qTVrPcOuBARx6cOf8bdlAMguklO4Jqo7zKX9kCe c0HvGFDs4VOTW0CmTtdCwtJonnNzDRNhb2A29Yo54VtsAXtBveJFvlOXfVOEJj9DVKqY jR3iFSdsVgUHhgessbOidYs7dgvf9i1DpZKpE9FgJ5IF2ZkrGavs6rliDcFHaggnPitP xgPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d+pOvzjLdVYp+MmYo9tDbbGKAe+YDrG7n/EDarHxK9g=; b=VlCLLjWNXWJfpQvYXMIZuFs9CAt8hRQXPidTB0lQaKXoljUnqZcKUFKNnuLn3ZHHlw 1WugluxTJfS20eK/a2M2JAXhaz2WAEOGE8resbxBc3VpVK7IInW/u0gbRZaWM2EO/bvW /49kYEVH8ZRICW8EnBP/1C5ooHDWNiDOS6AaumV4AHjd82mkhJJ5fxphIgbe5x7+SrK0 nW5xiTx+lItCbGCg4Qnx6F0BbLutESqyAFcXubXPCVZpPigf3eIyRR1uJGrTvipC+Trt AyrkpHnnzH68vTX5yyzgIf+PhHJT9RFDSubTSB2Ki1Vpk7Y29DRsZDZ7uP2kjTF2nj0G ndDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x0XQUAUs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Fri, 15 Jan 2021 12:46:42 -1000 Message-Id: <20210115224645.1196742-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 34 +++++++++++++++++++++--------- target/arm/mte_helper.c | 10 +++++++++ 3 files changed, 35 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index 777fb667fe..18013e1b23 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 6867f0db2b..6160a401bd 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -72,6 +72,21 @@ put_user_u16(__x, (gaddr)); \ }) +static bool check_mte_async_fault(CPUARMState *env, target_siginfo_t *info) +{ + if (likely(env->cp15.tfsr_el[0] == 0)) { + return false; + } + + env->cp15.tfsr_el[0] = 0; + info->si_signo = TARGET_SIGSEGV; + info->si_errno = 0; + info->_sifields._sigfault._addr = 0; + info->si_code = TARGET_SEGV_MTEAERR; + queue_signal(env, info->si_signo, QEMU_SI_FAULT, info); + return true; +} + /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { @@ -88,15 +103,13 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: - ret = do_syscall(env, - env->xregs[8], - env->xregs[0], - env->xregs[1], - env->xregs[2], - env->xregs[3], - env->xregs[4], - env->xregs[5], - 0, 0); + if (check_mte_async_fault(env, &info)) { + ret = -TARGET_ERESTARTSYS; + } else { + ret = do_syscall(env, env->xregs[8], env->xregs[0], + env->xregs[1], env->xregs[2], env->xregs[3], + env->xregs[4], env->xregs[5], 0, 0); + } if (ret == -TARGET_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { @@ -104,7 +117,8 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ + /* Just indicate that signals should be handled asap. */ + check_mte_async_fault(env, &info); break; case EXCP_UDEF: info.si_signo = TARGET_SIGILL; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df..d55f8d1e1e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, select = 0; } env->cp15.tfsr_el[el] |= 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; default: From patchwork Fri Jan 15 22:46:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363805 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp279575jap; Fri, 15 Jan 2021 15:05:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwS9fVsj9IykXNHU7chJo5XhmttTC9mp+asgQYAiD3mawaK45wM541187A+jAcwb8HEA3q X-Received: by 2002:a5b:101:: with SMTP id 1mr21550344ybx.507.1610751935325; Fri, 15 Jan 2021 15:05:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610751935; cv=none; d=google.com; s=arc-20160816; b=j+C1dx+3LYxGb/MC5oJTAszLwontYWt/6YHb+d+mAS5Y6ETkChDl/wzdoobGVm8Nqf ecKgZhKqdkKeFxCwM6MrrsKdjsAOKXxLaP37SuIDW7C20jIfN8TPqmBN7CWBrVot/SSB mbvjc8X6GL0IVSuQx7MjcSWTPnM7krRyM/71T43z50rx8w9b0z4dCVrRDNJUp2wvKBcP ZCvTePpt+1fdmKuwEWH2hbg8HTrvJz3imWcuErvlmgqiplahx5j++spsAt/SZIzA45Cw 9hFUxZdo+XmqBWa0wwJjlOUE99N7zA8Ud4wlj+yVmQLaRQcIyda8CqQV0xNRH9u/qjlP 7cDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e1dRDYwqVg1e/BMj2WtrxEnKh4CuzKOtBUsWpusVo1U=; b=py2WWvNLvMNlLCNfn47QvvgwQ7Ge9IofF/cKNHUc3drl+frps3dzSXR3Yfr0fUrgh+ /CsGArNf3FVCjMtZIgKvnGr9JqfzOQsYpencn05AbQ8VjWF8OyBCN4ZV5UgaizIU6JhH iF9o0fUraAyVxwoFePaDyhqg78yTl1O/SWIri3RCRi0RO2gA/6XsyXTBSuZ8WXO3qzv6 bt4g4ZvZqbBgKKh9uy8YSPLuC7OG3mQoEDdS2WHjo3rdaOoDnt7syAyTvO3oEpzryAHj XwKc3nAhPwGRqecaWQLG+ru3Bfo3SgvWXC6kxm6gLgzfHtPIUCl/697pewq9UbSJyn6o sNXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rIS9TFyK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/21] target/arm: Add allocation tag storage for user mode Date: Fri, 15 Jan 2021 12:46:43 -1000 Message-Id: <20210115224645.1196742-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the now-saved PAGE_ANON and PAGE_MTE bits, and the per-page saved data. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d55f8d1e1e..1c569336ea 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr = useronly_clean_ptr(ptr); + int flags = page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; From patchwork Fri Jan 15 22:46:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363808 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp281547jap; Fri, 15 Jan 2021 15:08:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJwJh25/SXUZgeo3ZXlBq+ifHqoSEX70792C16PWTdgo7Cu2Gc+puGk2V5pp/XAUfZ4cCCxt X-Received: by 2002:a25:2407:: with SMTP id k7mr22671953ybk.282.1610752134656; Fri, 15 Jan 2021 15:08:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610752134; cv=none; d=google.com; s=arc-20160816; b=u63d2y8NUIKJ3YTMVsfaoFR8g1lPkYXVYJ4YVJf08Czb5aLfCEo4rFSUkV/3V+SXGb jpIg3P8K2BfAxWvcnm1P7Cacy6QUb6ZvqYzWC6xgF6/yN/toitmfJE76kBvrGWU/FXKR aGNqvjnRNh4BUkLeKwaQDO+nFv1K24CsB+4HS34gYBYLFNx2GxFQUB6QNsojpNU5uHQN jM4GFd/K0vIBdsBH+UvNQMIO+gC4MfYDBT1zfObVfVGhOBBPvOQwZETIjQTOZPc77hLh HOQuyrP+08kuvDSHys4I5E8zNmzSRK/Tn64fnPz9I72636EWbvjph8q96oUECNQGfUZQ J7eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NVTYVf4zlgciMSRy3E1kBUuwxIM3r8rkk5rLkXytMCY=; b=UaDi4swVLYO0MUwxMLmT8rOWvgM/D6QRPQzweyZIoxxD3cj0uY6jyG+pT3khr/RfIq G28qSNcMobVhXuudCKbNBX1LjHXty9ViXsX9NwUSNnh4EeGgkpqpmIbG5gQAQNyumQhb e7D7gTtAhimzX3sxzh7W/UYyWAgFim3LYoc6SE6kuKKl0TyWt6VeDsPtYigkMXSENf3O nOUsd8nx3SM0PJ+hauWLyWOUETnldqOkg/K//kd9tjYL6WTwNW4hdVy8cE6GRIgh20Ea bdiSHc6nTFAXvUh+jmUJTiRYZidM/9rfE0t8U7g2a2cIAuiu8jiS50gfsNAi5fffq0aq F9Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OLeFUxgq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 20/21] target/arm: Enable MTE for user-only Date: Fri, 15 Jan 2021 12:46:44 -1000 Message-Id: <20210115224645.1196742-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index abc0affd00..5e613a747a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,6 +208,22 @@ static void arm_cpu_reset(DeviceState *dev) * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl = 0. + * + * Set RRND, so that helper_irg() will generate a seed later. + * Here in cpu_reset(), the crypto subsystem has not yet been + * initialized. + */ + env->cp15.gcr_el1 = 0x1ffff; + } + # ifdef TARGET_TAGGED_ADDRESSES env->untagged_addr_mask = -1; # endif From patchwork Fri Jan 15 22:46:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 363809 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp282156jap; Fri, 15 Jan 2021 15:09:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOtLY8dSIaU0/PdgSxAfnYXGUhYDHhE2Lkl2RpT+JBlgggVmsPTnjzsU4BwNbXkHupzwiN X-Received: by 2002:a25:6ec3:: with SMTP id j186mr21699564ybc.335.1610752196899; Fri, 15 Jan 2021 15:09:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610752196; cv=none; d=google.com; s=arc-20160816; b=rS18JCRNiDGzUTUGj2KsPqEGLAxV4MahbXbB5JiDwdjLqs2mZ08jGiGM3VwR1gZHBO RxwUqV2Y1m9XzTuvnh7+ndFhdU2X5gN4wk152KIEj9uF0UfKhBoUpywmMlcAZtD4ZeWl 8hJtCVm3djRBK78GmYlobraNKVSFMpXA45xSNEB6p9cwWN3CQ0Abb+DNm2VaDPIql0Po HSJFEX03XwR7bGdS+3tNXUo5nkcxQOsH6LfMtdsIon+gkbneeyixMwAMxs8vPmRtArP7 qR//EYPDIfrd6g3pp6/8aPNieCno9XtyIdilT7/nVeLcmaP/gyUnbyBssKNtw68vPhwQ 6OrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ed3dMxH1EDG+4PBQ/N+mQ4V0QrBrfta+sRgZmd+re9s=; b=d6ZbKsZdXBJuvP6ZD76Y/7+d57QV7XizUxaasn7Xy3cOJE7iB/NGxwzp+iOfkA9aPb ZtGV3WS46cBZ390YAYh1auOdqG1k0I/Ax8o+M1DgdkdUIhPlPhkNEvAVBC8Jh/+77FXM w6l82qUZRVWDzt+ZIkV33zZ3nBmpvU8LzaRx7hMQkbc/9E9oBjkVFvKGewpOmaCuS4kq BG4SH3JOTTDWuE5FFZ6FyAR+36hTxL1vAa3DVL1kka5MmnweEHAjoD7NBXDk5w8As7iQ nojQfxuLvodx5WZb6MUkkJ3y81TsTLs17e3XyI4ehRgSNWVzDfzjJAm2U1DikyuiR+p2 3s/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NWG1XoMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/21] tests/tcg/aarch64: Add mte smoke tests Date: Fri, 15 Jan 2021 12:46:45 -1000 Message-Id: <20210115224645.1196742-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 53 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 25 +++++++++++++++ tests/tcg/aarch64/mte-2.c | 42 ++++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 47 +++++++++++++++++++++++++++ tests/tcg/aarch64/mte-4.c | 42 ++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++++ tests/tcg/configure.sh | 4 +++ 7 files changed, 219 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c -- 2.25.1 diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 0000000000..038d33ab6c --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,53 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r = prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_mem(size_t size) +{ + void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p == MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..02bc978482 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,25 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 = alloc_mte_mem(sizeof(*p0)); + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..a05f5183cb --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,42 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 = 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 0000000000..0d08b477cc --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,47 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + */ + *p2 = 0; + while (1); +} diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c new file mode 100644 index 0000000000..52aa6fae65 --- /dev/null +++ b/tests/tcg/aarch64/mte-4.c @@ -0,0 +1,42 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void __attribute__((noinline)) tagset(void *p, size_t size) +{ + size_t i; + for (i = 0; i < size; i += 16) { + asm("stg %0, [%0]" : : "r"(p + i)); + } +} + +void __attribute__((noinline)) tagcheck(void *p, size_t size) +{ + size_t i; + void *c; + + for (i = 0; i < size; i += 16) { + asm("ldg %0, [%1]" : "=r"(c) : "r"(p + i), "0"(p)); + assert(c == p); + } +} + +int main(int ac, char **av) +{ + size_t size = getpagesize() * 4; + long excl = 1; + int *p0, *p1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(size); + + /* Tag the pointer. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + + tagset(p1, size); + tagcheck(p1, size); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index d7d33e293c..bf53ad0087 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -35,6 +35,12 @@ endif # bti-2 tests PROT_BTI, so no special compiler support required. AARCH64_TESTS += bti-2 +# MTE Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 +mte-%: CFLAGS += -march=armv8.5-a+memtag +endif + # Semihosting smoke test for linux-user AARCH64_TESTS += semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f2..ba8ac9a93e 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -244,6 +244,10 @@ for target in $target_list; do -mbranch-protection=standard -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=armv8.5-a+memtag -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak + fi ;; esac