From patchwork Fri Feb 23 16:05:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129378 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp749464edc; Fri, 23 Feb 2018 07:16:18 -0800 (PST) X-Google-Smtp-Source: AH8x225FG0dUNqrMJ/hJ65sMViFXgJfCScXNkwRh/avwem6OBMmlvUiUxVsXLSVqrR5nQbcfRHJl X-Received: by 10.99.97.9 with SMTP id v9mr1678680pgb.373.1519398978364; Fri, 23 Feb 2018 07:16:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398978; cv=none; d=google.com; s=arc-20160816; b=VlEDhuPrtdpQ//PBDp7kGBr+RB9UxhhQONirRd6xI+YZk/3pG3B86+Nj6ee4BL8/eL 87jcFbKxQyzdGd2BVqY4bpD/gOZSOsk+Qvyjd6UPQV6MCa5nEAijavc8XurU73hYZDn6 wa5O6fhUoujE0gtwZFlQR6fFxN/6FW3RFOJGWYL0NUGrzJ9jML4SGgOsIArA18f61HNR jALyolxodIhheJ0RU9SFqZ+sFEfPzoUB3zECJteEYCFk9lx5AFJqkurO05sXHAWQC9Nm i461ftNm6F0Wr9X4nKLEbNRzfrZwsQRt0/PuxOL98s9gdSWcV2jIP3lity/1aVOhBnMy rZkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=vyBbUkFPS348DmzbElxi0P5dt0F+La3szKjnLjX3h/8=; b=WblmiK1gXF3GdmErk5eXWadahnpjsqc+d/OoRSGLgGJ/fB2PrFn49zH1I8om9z2w0T FesV5iQN6tAl0pNaNYNVRwn7Ce4Z68HkwwLp1NgyeA7Hjg7h5mr4zBEvv2cIEnKaMQtA 4s4xHlVFrjsCsaPlJVx62LMJcqFOgENwVT5E/MmoBpfpDxpiKcGKZ1+8iCfluUtb+mRJ zaJrdYcAx8XyP78Xnk/ZScp9T1cncVuSkIuOH3iP/kIo8FDbpitnK3U4Ur8/sz9UIXOr zLj5PEXWhPQzjQtYpmuWOC91VeVl/y2vmS5uJ2aU+JfoPd5t7xL/pyqIzbyR3xs/QLf0 AbOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 73si1033911pfu.71.2018.02.23.07.16.18; Fri, 23 Feb 2018 07:16:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751928AbeBWPQC (ORCPT + 28 others); Fri, 23 Feb 2018 10:16:02 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39956 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751912AbeBWPO1 (ORCPT ); Fri, 23 Feb 2018 10:14:27 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C73075E693F33; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:11 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 01/11] perf vendor events: drop incomplete multiple mapfile support Date: Sat, 24 Feb 2018 00:05:22 +0800 Message-ID: <1519401932-205051-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently jevents supports multiple mapfiles, but this is only in the form where mapfile basename starts with 'mapfile.csv' At the moment, no architectures actually use multiple mapfiles, so drop the support for now. This patch also solves a nuisance where, when the mapfile is edited and the text editor may create a backup, jevents may use the backup, as shown: jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv Signed-off-by: John Garry Acked-by: Jiri Olsa --- tools/perf/pmu-events/README | 5 ++--- tools/perf/pmu-events/jevents.c | 10 ++-------- 2 files changed, 4 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index c2ee3e4..2407abc 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - - Regular files with basename starting with 'mapfile.csv' are assumed - to be a CSV file that maps a specific CPU to its set of PMU events. - (see below for mapfile format) + - The CSV file that maps a specific CPU to its set of PMU events is to + be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored. diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index b578aa2..9e0a21e 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb, * after processing all JSON files (so we can write out the * mapping table after all PMU events tables). * - * TODO: Allow for multiple mapfiles? Punt for now. */ if (level == 1 && is_file) { - if (!strncmp(bname, "mapfile.csv", 11)) { - if (mapfile) { - pr_info("%s: Many mapfiles? Using %s, ignoring %s\n", - prog, mapfile, fpath); - } else { - mapfile = strdup(fpath); - } + if (!strcmp(bname, "mapfile.csv")) { + mapfile = strdup(fpath); return 0; } From patchwork Fri Feb 23 16:05:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129372 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp747552edc; Fri, 23 Feb 2018 07:14:38 -0800 (PST) X-Google-Smtp-Source: AH8x2270vwpftuK6KxwzkZz4WO3pfr2+d/bKUAtcg7lctuwfuPSC2/1MQDprBFR8igz6lKl/qf9f X-Received: by 2002:a17:902:5a1:: with SMTP id f30-v6mr2036599plf.124.1519398878078; Fri, 23 Feb 2018 07:14:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398878; cv=none; d=google.com; s=arc-20160816; b=PBvP5eY+qPEvCpT+yMC6NMTln19JPWWWcTr3nyjG6IkN30LehBY/nlroMrT6OKUx7S k8LfVzI6HsmFvQ2DY2jHjOLxsNfHyqIIX42Y9sWVOF6CCkZgIyw9309JbatbayPi7htC m6KEzusmaI0nYibeauN0/hnbi7Ne9Z4ZfVX7V5rHC0NG2wu2a8VJpodscyloK4SgvGdH I0mDgVWbA508/Qzd1gwHWVudj4zX2K0Ivco68Hh1JXGAKhtR6zwVvuPXTT0Z7/q5CTXM cqXDQ2amzgviZFuhnRrh0FGeUqgMuApV+ozlBqk8uGhgGcszB55pU7aI5cHf8MsO9U9V LH4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=RdmFWCIV0qjnvw+QUKUTVKtpBwBuptEeOKXdf30MCno=; b=F7gvODhWZGVfWSTTxgsw5pV9NyqrKWxSnZ8c8piC83ClYG93SpszVO1PivSmsdLPue KyOJC1gNrgiYVU+/H1Z5XfSBE8HUg1cgUDGqP1ytx3f8Y+QG9UZc1zHpwsnOHaueVcz5 06/paUnA8CPEuJ776rxgt/4W5I/+PEpjI5yWGf/iei/r4Bf8bEqO5pP+dtAxLi2Hs4Uu MqvRvD9J+xQgx940xgh2fscqsXOozOjdAn5ljE5HIwSfDxP5RLR5+uO5fNIjkDfUI4Pq dNov00hW98Fegrl8Z95YOyQYZvBiFJVJ7fUFigzeXFxrvDLllUfm8yN5jPfTiJLT5aRW so2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6-v6si1962814plo.525.2018.02.23.07.14.37; Fri, 23 Feb 2018 07:14:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752049AbeBWPOd (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:33 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39962 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751913AbeBWPO1 (ORCPT ); Fri, 23 Feb 2018 10:14:27 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id D873E84174D2B; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:11 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 02/11] perf vendor events: fix error code in json_events() Date: Sat, 24 Feb 2018 00:05:23 +0800 Message-ID: <1519401932-205051-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When EXPECT macro fails an assertion, the error code is not properly set after the first loop of tokens in function json_events(). This is because err is set to the return value from func function pointer call, which must be 0 to continue to loop, yet it is not reset for for each loop. I assume that this was not the intention, so change the code so err is set appropriately in EXPECT macro itself. In addition to this, the indention in EXPECT macro is tidied. The current indention alludes that the 2 statements following the if statement are in the body, which is not true. Signed-off-by: John Garry --- tools/perf/pmu-events/jevents.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 9e0a21e..edff989 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) jsmntok_t *loc = (t); \ if (!(t)->start && (t) > tokens) \ loc = (t) - 1; \ - pr_err("%s:%d: " m ", got %s\n", fn, \ - json_line(map, loc), \ - json_name(t)); \ + pr_err("%s:%d: " m ", got %s\n", fn, \ + json_line(map, loc), \ + json_name(t)); \ + err = -EIO; \ goto out_free; \ } } while (0) @@ -416,7 +417,7 @@ int json_events(const char *fn, char *metric_name, char *metric_group), void *data) { - int err = -EIO; + int err; size_t size; jsmntok_t *tokens, *tok; int i, j, len; From patchwork Fri Feb 23 16:05:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129374 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp748202edc; Fri, 23 Feb 2018 07:15:12 -0800 (PST) X-Google-Smtp-Source: AH8x225PzD1H2cA0hjx+3SuYqwKhR2rxm/7Z5rDR44F7eaYhHtQaKbfnP1+jsn4OI7kwDe+ZoLKr X-Received: by 2002:a17:902:b904:: with SMTP id bf4-v6mr1995782plb.195.1519398911922; Fri, 23 Feb 2018 07:15:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398911; cv=none; d=google.com; s=arc-20160816; b=bcBXRQCqjNTCnVTTI60EBiXricR4eho3pS+0RHWbjCfNYomVUwa9D+iMA4JYuHBeXp kyd7tW+SgLzWzfCtlKE8JhTxktz6awDGuE0rb88O0bp/8WkhrLNYSrCqI3okEales1p9 US02+RwLOduIXTQp7Jcb6l0EzZxrXZk6Znfr36aWhBNxriu9v2obTv2hPRw3oiUuGA15 qmfcB9kHsKhAGW9w/5BVyHDK9oiROlzK6cT5cclsy6S5RwqrEalvLZ3HnLjEwR1PYmTw 1rECeZ/Fzs8G2HeIujeKY3CdzFwcTSXduQfUK0KeT6ZWkFrMHCbGIjWKIZ7A8tOAcTIs r6EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=G2nU+dKi/TApBx3Q8w2Q5fXzW7lasbyCM6H9nNFWvz0=; b=e6PonZlCg5Et6gpHH3RoE1tm+/iUVgqSM4i/mqj4NW0ZcF8S/5hOJeV1oSEhP6HqL1 AsJWvJNHxV/ZVWyoM4yeg3eTO6vUpLRMmb1uveQrPFSC3c4lhbLSJU+JzlJhc3hFEQq7 Lq8AkZ8EAXVjA/xFsWJqWcEPvtCBCmhtCSCHMRbbTUFpJOdnz0tobfsSWH1zcl/glkPd 5tZ/3VAPg446r7KZihvUPrcaClt//fdrZexpbB6Kmb7NQJgChrHiXv4PBqPzP4zKZB2a xVNaeQ1NWO347Bh1+B6dCjY5L69aEJBuJNzGRM9aTptmVfWdUSyfFhMt1gxZXQMwvoIk Q2Ww== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a190si1627611pge.436.2018.02.23.07.15.11; Fri, 23 Feb 2018 07:15:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752011AbeBWPOb (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:31 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39963 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751904AbeBWPO1 (ORCPT ); Fri, 23 Feb 2018 10:14:27 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E993A91A9A3D5; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:12 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 03/11] perf vendor events: drop support for unused topic directories Date: Sat, 24 Feb 2018 00:05:24 +0800 Message-ID: <1519401932-205051-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently a topic subdirectory is supported in the pmu-events dir, in the following sample structure: /arch/platform/subtopic/mysubtopic.json Upto 256 levels of topic subdirectories are supported. So this means that JSONs may be located in a topic dir as well as the platform dir. This topic subdirectory causes problems if we want to add support for a vendor dir in the pmu-events structure (in the form arch/platform/vendor), in that we cannot differentiate between a vendor dir and a topic dir. Since the topic dir feature is not used, drop it so it does not block adding vendor subdirectory support. Signed-off-by: John Garry --- NOTE: There was a bug in this code with how add_topic() sets topic_level. Also a delimiter could be added in printing the "topic" in get_topic(). tools/perf/pmu-events/jevents.c | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index edff989..1d02faf 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) goto out_free; \ } } while (0) -#define TOPIC_DEPTH 256 -static char *topic_array[TOPIC_DEPTH]; -static int topic_level; +static char *topic; static char *get_topic(void) { - char *tp_old, *tp = NULL; + char *tp; int i; - for (i = 0; i < topic_level + 1; i++) { - int n; - - tp_old = tp; - n = asprintf(&tp, "%s%s", tp ?: "", topic_array[i]); - if (n < 0) { - pr_info("%s: asprintf() error %s\n", prog); - return NULL; - } - free(tp_old); + /* tp is free'd in process_one_file() */ + i = asprintf(&tp, "%s", topic); + if (i < 0) { + pr_info("%s: asprintf() error %s\n", prog); + return NULL; } for (i = 0; i < (int) strlen(tp); i++) { @@ -291,25 +284,15 @@ static char *get_topic(void) return tp; } -static int add_topic(int level, char *bname) +static int add_topic(char *bname) { - char *topic; - - level -= 2; - - if (level >= TOPIC_DEPTH) - return -EINVAL; - + free(topic); topic = strdup(bname); if (!topic) { pr_info("%s: strdup() error %s for file %s\n", prog, strerror(errno), bname); return -ENOMEM; } - - free(topic_array[topic_level]); - topic_array[topic_level] = topic; - topic_level = level; return 0; } @@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, } } - if (level > 1 && add_topic(level, bname)) + if (level > 1 && add_topic(bname)) return -ENOMEM; /* From patchwork Fri Feb 23 16:05:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129375 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp748732edc; Fri, 23 Feb 2018 07:15:40 -0800 (PST) X-Google-Smtp-Source: AH8x224nhGSHvUBAwkLHAisSk+IgUUVvWnTNVF+ke1zseqZChHubszlD653OxUxnM230ZfOI/Cg1 X-Received: by 10.98.105.9 with SMTP id e9mr2104262pfc.226.1519398940662; Fri, 23 Feb 2018 07:15:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398940; cv=none; d=google.com; s=arc-20160816; b=FnSktp2XTUC7BH2j4fltKAyJqeOd5x0da61wYwJS6U1j1sCmnj79DDyPeq6t7NJ+fd oD4LNpDXvKS3AQ1ZZ3/HyHBESvP+XfRwGbNEyjhk9vZa9QvCsunnhRHAP6ZIr671/SiQ nvJ7s7ewo688D+OPyEd6CrZUklA3JoumFOgMmXu+u2wSQxUHxVb74GGhqSgysyHdTLkg ivcMQLZj+Su7Zwl1bUZSAGrdH/uN2pR/oabGegeQX6qDbyUEluVwf4KHDzsSIZHU3RqE Nx802R8mgdAgspSVOGkhU03ODnoj7zEE/cd8UdaC+2S0MQsf90fi0YoW1tQteUoEJQTt TZQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=AvCYBm8GxSXk+cmu9prxNw3JgKFZSFox9BfHGmoU+no=; b=XouIGbhGoZjlNWkZ9FyDj5M1/ojro6sjj3EqHhghL6IXu2XR3ijApGUToNxprJ3WuT zRRpkBJVcxB4AL0KSGct6m3yIEU54ICarzSRO4W6oD3h2JpYEq08dSX6XviJXxXLWbrK hV/nEDja5TwSqXx8SRrYPugyP3+ikXgI0oVNYJLA1/SXGh+vyu/00AAKd8GsiTLxnvor 3OJvCgbvEfhT8kbGNXB4swVHczphUraOvMhBZ66QHsd9P1tF/EAvocrbBXsEgJPrA46+ ut3lOzVUk3L4uILMZUQZtpSSq81DrKWSZUYwXq0shl9atGgHUrqYhQNK34Eij2pFJZP+ ZmIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j84si1973913pfj.177.2018.02.23.07.15.40; Fri, 23 Feb 2018 07:15:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751991AbeBWPOa (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:30 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39954 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751785AbeBWPO0 (ORCPT ); Fri, 23 Feb 2018 10:14:26 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B56741F6BBA73; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:12 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 04/11] perf vendor events: add support for pmu events vendor subdirectory Date: Sat, 24 Feb 2018 00:05:25 +0800 Message-ID: <1519401932-205051-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some architectures (like arm), it is required to support a vendor subdirectory and not locate all the JSONs for a specific vendor in the same folder. This is because all the events for the same vendor will be placed in the same pmu events table, which may cause conflict. This conflict would be in the instance that a vendor's custom implemented events do have the same meaning on different platforms, so events in the pmu table would conflict. In addition, per list command may show events which are not even supported for a given platform. This patch adds support for a arch/vendor/platform directory hierarchy, while maintaining backwards-compatibility for existing arch/platform structure. In this, each platform would always have its own pmu events table. In generated file pmu_events.c, each platform table name is in the format pme{_vendor}_platform, like this: struct pmu_events_map pmu_events_map[] = { { .cpuid = "0x00000000420f5160", .version = "v1", .type = "core", .table = pme_cavium_thunderx2 }, { .cpuid = 0, .version = 0, .type = 0, .table = 0, }, }; Signed-off-by: John Garry Acked-by: Jiri Olsa --- tools/perf/pmu-events/README | 4 +++ tools/perf/pmu-events/jevents.c | 64 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 62 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 2407abc..655286f 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU: Cache.json Memory.json Virtual-Memory.json Frontend.json Pipeline.json +The JSONs folder for a CPU model/family may be placed in the root arch +folder, or may be placed in a vendor sub-folder under the arch folder +for instances where the arch and vendor are not the same. + Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 1d02faf..7b9e210 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -572,7 +572,7 @@ static char *file_name_to_table_name(char *fname) * Derive rest of table name from basename of the JSON file, * replacing hyphens and stripping out .json suffix. */ - n = asprintf(&tblname, "pme_%s", basename(fname)); + n = asprintf(&tblname, "pme_%s", fname); if (n < 0) { pr_info("%s: asprintf() error %s for file %s\n", prog, strerror(errno), fname); @@ -582,7 +582,7 @@ static char *file_name_to_table_name(char *fname) for (i = 0; i < strlen(tblname); i++) { c = tblname[i]; - if (c == '-') + if (c == '-' || c == '/') tblname[i] = '_'; else if (c == '.') { tblname[i] = '\0'; @@ -739,25 +739,77 @@ static int get_maxfds(void) static FILE *eventsfp; static char *mapfile; +static int is_leaf_dir(const char *fpath) +{ + DIR *d; + struct dirent *dir; + int res = 1; + + d = opendir(fpath); + if (!d) + return 0; + + while ((dir = readdir(d)) != NULL) { + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') { + res = 0; + break; + } else if (dir->d_type == DT_UNKNOWN) { + char path[PATH_MAX]; + struct stat st; + + sprintf(path, "%s/%s", fpath, dir->d_name); + if (stat(path, &st)) + break; + + if (S_ISDIR(st.st_mode)) { + res = 0; + break; + } + } + } + + closedir(d); + + return res; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { - char *tblname, *bname = (char *) fpath + ftwbuf->base; + char *tblname, *bname; int is_dir = typeflag == FTW_D; int is_file = typeflag == FTW_F; int level = ftwbuf->level; int err = 0; + if (level == 2 && is_dir) { + /* + * For level 2 directory, bname will include parent name, + * like vendor/platform. So search back from platform dir + * to find this. + */ + bname = (char *) fpath + ftwbuf->base - 2; + for (;;) { + if (*bname == '/') + break; + bname--; + } + bname++; + } else + bname = (char *) fpath + ftwbuf->base; + pr_debug("%s %d %7jd %-20s %s\n", is_file ? "f" : is_dir ? "d" : "x", level, sb->st_size, bname, fpath); - /* base dir */ - if (level == 0) + /* base dir or too deep */ + if (level == 0 || level > 3) return 0; + /* model directory, reset topic */ - if (level == 1 && is_dir) { + if ((level == 1 && is_dir && is_leaf_dir(fpath)) || + (level == 2 && is_dir)) { if (close_table) print_events_table_suffix(eventsfp); From patchwork Fri Feb 23 16:05:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129380 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp750404edc; Fri, 23 Feb 2018 07:17:04 -0800 (PST) X-Google-Smtp-Source: AH8x224SPpLTp0xqMax58VxyCVQRGQrC2k+6eCyJAeG3BlPvbdQIEcQAvbDDXtPC0gJQrJxyK8wJ X-Received: by 10.99.145.194 with SMTP id l185mr1663675pge.394.1519399024049; Fri, 23 Feb 2018 07:17:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519399024; cv=none; d=google.com; s=arc-20160816; b=fB1sGVaTJR9vthDnqO4i2EZMacSaqK0B89srY3rHGkf4i5XWh/4RizcXw+WbnyeoEX ci2FNm8Gd5PnLq52Ahy0jKzT8g+w8SL1DJ9dSuQZqPNHh97056JtyCpg1C073AtQtyIE Qp5Y9SUX5YcznoXL65M82X5CkC9rpsa7sCGWPjhIAiyMKTwWlA3awV/JQujo0PDMD9Da gTegSxaRXU0eR9IDCMv7Td53KiyXB3Rg/Qi68wclkKzDne1Pzgk4PcTEl3YZpddWJTO+ nOR/Bj80ATkT+zoJXjlWOEgVnL3Az+bNnkCr7+m0UZS23L23O8/mdTQnl8Xz9OWY1621 dRdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zM+abxZaUaF+2Wlc+oiaxEwW3YU+2kRCh2Uxf42Lses=; b=ambSANbV7k6nGfHWg/oCXTDVM1kVaua7SjC2Obv6IaubQU/lxnUF2vbZwwqLXsvW6d ffP00JwHyEq6SIZAQThxPLWp6IDZhqqqSqUkilaS+PoMkOAbcL3sbmQA8neR1sVNC5Am BNB+PC9DvUa4GyuGL//6wnARe2SsVDn7sVPuKS9kERAMDMZffP+L1ENBOa8XZFkbi69N V7ocP4Ngs9sRwL56f9Y9jJ7GprOh1wTcBXOI89PDsBp5qzPiAqNNyvJ1QOVBDpcmIVLW 0jwwkopE/FzxkZ/N2AG0zvzNrv+E+x9S7KdrFw7GN+QnU0PVDHaLyNuflXtZ2WVjaHz5 JTYw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z2si1618035pgn.768.2018.02.23.07.17.03; Fri, 23 Feb 2018 07:17:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752071AbeBWPRA (ORCPT + 28 others); Fri, 23 Feb 2018 10:17:00 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39912 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751815AbeBWPOY (ORCPT ); Fri, 23 Feb 2018 10:14:24 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7E08ECFAF12E; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:12 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 05/11] perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory Date: Sat, 24 Feb 2018 00:05:26 +0800 Message-ID: <1519401932-205051-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since jevents now supports vendor subdirectory, relocate the ThunderX2 JSON to Cavium subdirectory. Cc: Ganapatrao Kulkarni Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---------------------- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 3 files changed, 63 insertions(+), 63 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json deleted file mode 100644 index 2db45c4..0000000 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json +++ /dev/null @@ -1,62 +0,0 @@ -[ - { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", - }, - { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", - }, - { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", - }, - { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json new file mode 100644 index 0000000..2db45c4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "l1d_cache_rd", + "BriefDescription": "L1D cache read", + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write ", + "EventCode": "0x41", + "EventName": "l1d_cache_wr", + "BriefDescription": "L1D cache write", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "l1d_cache_refill_rd", + "BriefDescription": "L1D cache refill read", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "l1d_cache_refill_wr", + "BriefDescription": "L1D refill write", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "l1d_tlb_refill_rd", + "BriefDescription": "L1D tlb refill read", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "l1d_tlb_refill_wr", + "BriefDescription": "L1D tlb refill write", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "l1d_tlb_rd", + "BriefDescription": "L1D tlb read", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "l1d_tlb_wr", + "BriefDescription": "L1D tlb write", + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "bus_access_rd", + "BriefDescription": "Bus access read", + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "bus_access_wr", + "BriefDescription": "Bus access write", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index e61c9ca..952a05c 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Fri Feb 23 16:05:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129376 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp748934edc; Fri, 23 Feb 2018 07:15:52 -0800 (PST) X-Google-Smtp-Source: AH8x227Mbd6c2d1RNSa/KqoYBBMrYZ3YmVHW8vMaIZmHBSi4H65sgHrbqpOjEWcUfP2GzeNGvw9e X-Received: by 2002:a17:902:a981:: with SMTP id bh1-v6mr1961429plb.298.1519398952752; Fri, 23 Feb 2018 07:15:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398952; cv=none; d=google.com; s=arc-20160816; b=f/F13I593IdjD210ib5AD2ClPW/Yp0u9GPI2GL0ktvEtf+F6sL5A4ZAzIzv+qJIV9K OQUVFy//9mVzO9L66GsngVmQIDUT6MTLBmNTM/SBSn2DkFtj7clesD8Kh33k9MfQrZeu 1s2/TPmM9orHW67eUsWehdtTUBnZ76XZRNj9+i6IaGx8iXm1eZrv/D+LlNvxl4XOmerT NskwdzXDgpOE9FNd9RjeQ9wpYPjULpSACwbIJtp6oHLTYzGWonCLt89hRbS5qctJWuqb qjsFSFHYPM1o4veqSbyPU11kVZqEs4UepKYLboknxR+b2erVUKF64tYB4vCY/cCaR2vK Mhww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=IwaiI92RaPUKav4RdbGuH6I4mNSQdAMtQ2MH0OiJS+A=; b=Lw8doZaNn/wVxe5FMVtOJFcbx8P4LbdzdyddwRygRoDv27uJz0GR+YMIAV1U2v5KjU gWpxNlLg2+xndtFPwetTqlmL5JTD7hYkLxu5Wi7WUJAYbSEkmJlvQkaCb0fofAq4IhoQ yYPWNlyYhjV+gIvKLG0tbWU8mAQUfztgsJMPbkpM+2670IxKcoIVAe01nDidnVLqJjMo AeMoGB6Pv8nhck2Egv6pewoss16QV7f5QfdlzXOhRjh878YjgiAoUAF4ZNPIwnJNUN/Q 2kiW8mdvJ2ivvamrFTpHWBAJLRFs6SVAcn3Kb9z4nPoZ/IWL3oHfxxZ7AOTRZrPa9tSZ Zb9w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j184si1646548pgc.142.2018.02.23.07.15.52; Fri, 23 Feb 2018 07:15:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751952AbeBWPO2 (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:28 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39925 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751841AbeBWPOZ (ORCPT ); Fri, 23 Feb 2018 10:14:25 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id A1EE1978D4806; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:13 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 06/11] perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory Date: Sat, 24 Feb 2018 00:05:27 +0800 Message-ID: <1519401932-205051-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm subdirectory. Cc: William Cohen Signed-off-by: John Garry --- .../arch/arm64/arm/cortex-a53/branch.json | 27 +++++++++++ .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/cache.json | 27 +++++++++++ .../arch/arm64/arm/cortex-a53/memory.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/other.json | 32 +++++++++++++ .../arch/arm64/arm/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++ .../pmu-events/arch/arm64/cortex-a53/branch.json | 27 ----------- .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/cache.json | 27 ----------- .../pmu-events/arch/arm64/cortex-a53/memory.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/other.json | 32 ------------- .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ---------------------- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 13 files changed, 183 insertions(+), 183 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json new file mode 100644 index 0000000..3b62087 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0x7A", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed - Indirect branch" + }, + {, + "EventCode": "0xC9", + "EventName": "BR_COND", + "BriefDescription": "Conditional branch executed" + }, + {, + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MISPRED", + "BriefDescription": "Indirect branch mispredicted" + }, + {, + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_MISPRED_ADDR", + "BriefDescription": "Indirect branch mispredicted because of address miscompare" + }, + {, + "EventCode": "0xCC", + "EventName": "BR_COND_MISPRED", + "BriefDescription": "Conditional branch mispredicted" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json new file mode 100644 index 0000000..11baad6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" + }, + {, + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" + }, + {, + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" + }, + {, + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" + }, + {, + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json new file mode 100644 index 0000000..73a2240 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -0,0 +1,32 @@ +[ + {, + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + }, + {, + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + }, + {, + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" + }, + {, + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + }, + {, + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + }, + {, + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json new file mode 100644 index 0000000..3149fb9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -0,0 +1,52 @@ +[ + {, + "EventCode": "0xC7", + "EventName": "STALL_SB_FULL", + "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" + }, + {, + "EventCode": "0xE0", + "EventName": "OTHER_IQ_DEP_STALL", + "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" + }, + {, + "EventCode": "0xE1", + "EventName": "IC_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" + }, + {, + "EventCode": "0xE2", + "EventName": "IUTLB_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" + }, + {, + "EventCode": "0xE3", + "EventName": "DECODE_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" + }, + {, + "EventCode": "0xE4", + "EventName": "OTHER_INTERLOCK_STALL", + "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" + }, + {, + "EventCode": "0xE5", + "EventName": "AGU_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" + }, + {, + "EventCode": "0xE6", + "EventName": "SIMD_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." + }, + {, + "EventCode": "0xE7", + "EventName": "LD_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" + }, + {, + "EventCode": "0xE8", + "EventName": "ST_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json deleted file mode 100644 index 3b62087..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" - }, - {, - "EventCode": "0xC9", - "EventName": "BR_COND", - "BriefDescription": "Conditional branch executed" - }, - {, - "EventCode": "0xCA", - "EventName": "BR_INDIRECT_MISPRED", - "BriefDescription": "Indirect branch mispredicted" - }, - {, - "EventCode": "0xCB", - "EventName": "BR_INDIRECT_MISPRED_ADDR", - "BriefDescription": "Indirect branch mispredicted because of address miscompare" - }, - {, - "EventCode": "0xCC", - "EventName": "BR_COND_MISPRED", - "BriefDescription": "Conditional branch mispredicted" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json deleted file mode 100644 index 11baad6..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" - }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" - }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" - }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" - }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json deleted file mode 100644 index 73a2240..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json +++ /dev/null @@ -1,32 +0,0 @@ -[ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" - }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" - }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" - }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" - }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" - }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json deleted file mode 100644 index 3149fb9..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json +++ /dev/null @@ -1,52 +0,0 @@ -[ - {, - "EventCode": "0xC7", - "EventName": "STALL_SB_FULL", - "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" - }, - {, - "EventCode": "0xE0", - "EventName": "OTHER_IQ_DEP_STALL", - "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" - }, - {, - "EventCode": "0xE1", - "EventName": "IC_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" - }, - {, - "EventCode": "0xE2", - "EventName": "IUTLB_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" - }, - {, - "EventCode": "0xE3", - "EventName": "DECODE_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" - }, - {, - "EventCode": "0xE4", - "EventName": "OTHER_INTERLOCK_STALL", - "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" - }, - {, - "EventCode": "0xE5", - "EventName": "AGU_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" - }, - {, - "EventCode": "0xE6", - "EventName": "SIMD_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." - }, - {, - "EventCode": "0xE7", - "EventName": "LD_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" - }, - {, - "EventCode": "0xE8", - "EventName": "ST_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 952a05c..cf14e23 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core -0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Fri Feb 23 16:05:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129381 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp750777edc; Fri, 23 Feb 2018 07:17:22 -0800 (PST) X-Google-Smtp-Source: AH8x224niFSA/+ixAeuBzs0JW3NnSMTPH+66xi6j1G+djxT9W8o4TDW/pZ37Cwyflc7XnHE07DYz X-Received: by 10.99.109.77 with SMTP id i74mr1672185pgc.73.1519399041897; Fri, 23 Feb 2018 07:17:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519399041; cv=none; d=google.com; s=arc-20160816; b=mFe6CjHjLK4aMSpC0lFnrwAzd3se2yyuc8lAQDqWzCtURze+3apLJM1INgKDFy0a6A LvJYX+AI+ayFgErOrfdv0JsgmY/A953+hoZDEs3xXnQX/kwslV6M+O7siFGfAOieQJvS pTtBR1WMSOqoIWAASWcgKABwR/GNwoFiR/+qBLM4sG5yLV1MtTaJYp2sRgL7n6C/Gkkw BYEvQNmssX5q0+bjxx7GqoR39m1EOjoGNhc1E0R5SMnV7Nf7QTQW55Lbhs1tx0sx/y4k Vkc6W2QiRPWqqE94vgNxERmQ3kgDtX1YMdID+QSegh6cs2IzB1BkgLLfZIcD6edirk14 I5Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=dvFZL1LneQs8kO7sSAz2gbLy54QgSlA0qHlSDSNloEs=; b=u8mLLJcsnIelqKP4UH6v9yOCEFUm+mATXEnwmXrFfff4DZB/3+0AEWRoKjVQK6UK0N mAhPh0peTA6Kay6uedYXGfKfpuwrV5GVMdMrOofsqwgZN//cPPho4+zCuOJibrqrXkPt Yy83nAQBxaFeF19NaIR+FqdE8Q6w1Y/astjDWfDf7czOCxYTEoC8+0k1MyJOlp7dExM8 VOkR8kW6UJ+3JS/IWBnCstIgj4GVxs4i6zsLHhsuTR0CCNGK9HUwUI5iSqEbtO1MDWVc fVZutQzmIjV5DzM6j7dKsOnuokiGMTt8hchhmdtMR9UfAbyNNkPqTh5Eh5LpXpx+lCqV VsVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l6si1631267pgq.562.2018.02.23.07.17.21; Fri, 23 Feb 2018 07:17:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752081AbeBWPRT (ORCPT + 28 others); Fri, 23 Feb 2018 10:17:19 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39796 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751782AbeBWPOX (ORCPT ); Fri, 23 Feb 2018 10:14:23 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 341AC758775DD; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:13 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 07/11] perf vendor events: add support for arch standard events Date: Sat, 24 Feb 2018 00:05:28 +0800 Message-ID: <1519401932-205051-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some architectures (like arm), there are architecture- defined events. Sometimes these events may be "recommended" according to the architecture standard, in that the implementer is free ignore the "recommendation" and create its custom event. This patch adds support for parsing standard events from arch-defined JSONs, and fixing up vendor events when they have implemented these events as standard. Support is also ensured that the vendor may implement their own custom events. A new step is added to the pmu events parsing to fix up the vendor events with the arch-standard events. The arch-defined JSONs must be placed in the arch root folder for preprocessing prior to tree JSON processing. In the vendor JSON, to specify that the arch event is supported, the keyword "ArchStdEvent" should be used, like this: [ { "ArchStdEvent": "0x41", "BriefDescription": "L1D cache access, write" }, ] No other JSON objects are strictly required. However, for other objects added, these take precedence over architecture defined standard events, thus supporting separate events which have the same event code. Signed-off-by: John Garry --- tools/perf/pmu-events/Build | 2 + tools/perf/pmu-events/README | 6 ++ tools/perf/pmu-events/jevents.c | 166 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 170 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 999a4e8..1778391 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -1,10 +1,12 @@ hostprogs := jevents jevents-y += json.o jsmn.o jevents.o +CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include pmu-events-y += pmu-events.o JDIR = pmu-events/arch/$(SRCARCH) JSON = $(shell [ -d $(JDIR) ] && \ find $(JDIR) -name '*.json' -o -name 'mapfile.csv') + # # Locate/process JSON files in pmu-events/arch/ # directory and create tables in pmu-events.c. diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 655286f..cff4c91 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo. - Directories are traversed, but all other files are ignored. + - To reduce JSON event duplication per architecture, platform JSONs may + use "ArchStdEvent" keyword to dereference an "Architecture standard + events", defined in architecture standard JSONs. + Architecture standard JSONs must be located in the architecture root + folder. + The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 7b9e210..3886c6b 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -44,6 +44,7 @@ #include /* getrlimit */ #include #include +#include #include "jsmn.h" #include "json.h" #include "jevents.h" @@ -350,6 +351,83 @@ static int print_events_table_entry(void *data, char *name, char *event, return 0; } +struct event_struct { + struct list_head list; + char *name; + char *event; + char *desc; + char *long_desc; + char *pmu; + char *unit; + char *perpkg; + char *metric_expr; + char *metric_name; + char *metric_group; +}; + +#define ADD_EVENT_FIELD(field) do { if (field) { \ + es->field = strdup(field); \ + if (!es->field) \ + goto out_free; \ +} } while (0) + +#define FREE_EVENT_FIELD(field) free(es->field) + +#define EVENT_PREFIX "event" + +#define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\ + *field = strdup(es->field); \ + if (!*field) \ + return -ENOMEM; \ +} } while (0) + +#define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \ + op(name); \ + op(event); \ + op(desc); \ + op(long_desc); \ + op(pmu); \ + op(unit); \ + op(perpkg); \ + op(metric_expr); \ + op(metric_name); \ + op(metric_group); \ +} while (0) + +static LIST_HEAD(arch_std_events); + +static void free_arch_std_events(void) +{ + struct event_struct *es, *next; + + list_for_each_entry_safe(es, next, &arch_std_events, list) { + FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); + list_del(&es->list); + free(es); + } +} + +static int save_arch_std_events(void *data, char *name, char *event, + char *desc, char *long_desc, char *pmu, + char *unit, char *perpkg, char *metric_expr, + char *metric_name, char *metric_group) +{ + struct event_struct *es; + struct stat *sb = data; + + es = malloc(sizeof(*es)); + if (!es) + return -ENOMEM; + memset(es, 0, sizeof(*es)); + FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD); + list_add_tail(&es->list, &arch_std_events); + return 0; +out_free: + FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); + free(es); + return -ENOMEM; +} + static void print_events_table_suffix(FILE *outfp) { fprintf(outfp, "{\n"); @@ -391,6 +469,27 @@ static char *real_event(const char *name, char *event) return event; } +static int +try_fixup(const char *fn, char *arch_std, char **event, char **desc, + char **name, char **long_desc, char **pmu, char **filter, + char **perpkg, char **unit, char **metric_expr, char **metric_name, + char **metric_group) +{ + /* try to find matching event from arch standard values */ + struct event_struct *es; + + list_for_each_entry(es, &arch_std_events, list) { + if (!strcmp(arch_std, es->event+sizeof(EVENT_PREFIX))) { + FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD); + return 0; + } + } + + pr_err("%s: could not find matching %s for %s\n", + prog, arch_std, fn); + return -1; +} + /* Call func with each event in the json file */ int json_events(const char *fn, int (*func)(void *data, char *name, char *event, char *desc, @@ -426,6 +525,7 @@ int json_events(const char *fn, char *metric_expr = NULL; char *metric_name = NULL; char *metric_group = NULL; + char *arch_std = NULL; unsigned long long eventcode = 0; struct msrmap *msr = NULL; jsmntok_t *msrval = NULL; @@ -511,6 +611,10 @@ int json_events(const char *fn, addfield(map, &metric_expr, "", "", val); for (s = metric_expr; *s; s++) *s = tolower(*s); + } else if (json_streq(map, field, "ArchStdEvent")) { + addfield(map, &arch_std, "", "", val); + for (s = arch_std; *s; s++) + *s = tolower(*s); } /* ignore unknown fields */ } @@ -522,7 +626,7 @@ int json_events(const char *fn, addfield(map, &extra_desc, " ", "(Precise event)", NULL); } - snprintf(buf, sizeof buf, "event=%#llx", eventcode); + snprintf(buf, sizeof(buf), "%s=%#llx", EVENT_PREFIX, eventcode); addfield(map, &event, ",", buf, NULL); if (desc && extra_desc) addfield(map, &desc, " ", extra_desc, NULL); @@ -535,8 +639,21 @@ int json_events(const char *fn, if (name) fixname(name); + if (arch_std) { + /* + * An arch standard event is referenced, so try to + * fixup any unassigned values. + */ + err = try_fixup(fn, arch_std, &event, &desc, &name, + &long_desc, &pmu, &filter, &perpkg, + &unit, &metric_expr, &metric_name, + &metric_group); + if (err) + goto free_strings; + } err = func(data, name, real_event(name, event), desc, long_desc, pmu, unit, perpkg, metric_expr, metric_name, metric_group); +free_strings: free(event); free(desc); free(name); @@ -549,6 +666,8 @@ int json_events(const char *fn, free(metric_expr); free(metric_name); free(metric_group); + free(arch_std); + if (err) break; tok += j; @@ -773,6 +892,32 @@ static int is_leaf_dir(const char *fpath) return res; } +static int is_json_file(const char *name) +{ + const char *suffix; + + if (strlen(name) < 5) + return 0; + + suffix = name + strlen(name) - 5; + + if (strncmp(suffix, ".json", 5) == 0) + return 1; + return 0; +} + +static int preprocess_arch_std_files(const char *fpath, const struct stat *sb, + int typeflag, struct FTW *ftwbuf) +{ + int level = ftwbuf->level; + int is_file = typeflag == FTW_F; + + if (level == 1 && is_file && is_json_file(fpath)) + return json_events(fpath, save_arch_std_events, (void *)sb); + + return 0; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { @@ -850,9 +995,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, * ignore it. It could be a readme.txt for instance. */ if (is_file) { - char *suffix = bname + strlen(bname) - 5; - - if (strncmp(suffix, ".json", 5)) { + if (!is_json_file(bname)) { pr_info("%s: Ignoring file without .json suffix %s\n", prog, fpath); return 0; @@ -958,12 +1101,26 @@ int main(int argc, char *argv[]) maxfds = get_maxfds(); mapfile = NULL; + rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0); + if (rc && verbose) { + pr_info("%s: Error preprocessing arch standard files %s\n", + prog, ldirname); + goto empty_map; + } else if (rc < 0) { + /* Make build fail */ + free_arch_std_events(); + return 1; + } else if (rc) { + goto empty_map; + } + rc = nftw(ldirname, process_one_file, maxfds, 0); if (rc && verbose) { pr_info("%s: Error walking file tree %s\n", prog, ldirname); goto empty_map; } else if (rc < 0) { /* Make build fail */ + free_arch_std_events(); return 1; } else if (rc) { goto empty_map; @@ -988,5 +1145,6 @@ int main(int argc, char *argv[]) empty_map: fclose(eventsfp); create_empty_mapping(output_file); + free_arch_std_events(); return 0; } From patchwork Fri Feb 23 16:05:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129377 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp749222edc; Fri, 23 Feb 2018 07:16:06 -0800 (PST) X-Google-Smtp-Source: AG47ELuEXLYNGb7VI2r8aVfJluF7gbYnSdoKM0/lwTzAwsOX1dANsFxVgn8ulWzcjcAvNqX5WO7o X-Received: by 2002:a17:902:7290:: with SMTP id d16-v6mr48830pll.31.1519398966434; Fri, 23 Feb 2018 07:16:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398966; cv=none; d=google.com; s=arc-20160816; b=jeAuI3msPGrt/ymL+TqNiImX9IvITXtoEbyL8kPYkWAYWJYHWGzR66b02cpuB91APX zvYYT6WnT1N9pkhiA5LSOzxYhAtplnfa6723ge2QfkSmKYtQ1bxdF5+d2HOC3Bb5AKr1 eDgFigt6TnzYOxM8WZRc4HgjYmniVpt8qQ8knslsy4M+nhGTywXQb4XERsW/mEgxl9yu J4xc8ZAFJtgo/we63gfyK7xIvRt7IpJCpSpfHJKrTrYZyVNivJg1AoqqSRHRUtq66sA0 dPuBmJj0RK58ud3JDSOWipsOKVbf9oVSkyWD8raiFfJqFjRYdqD6yQ5VKUigtlm4IgWE 1dTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=VIZjMVfclJRYeGMpuI3aPi9PrGNWBIgFil9HAwLKamY=; b=saZDyVusLq4EOk58a2bbhAuXKHuw/86TGhW2xC1GBksiXk5a1ulNe/xt/31COyMKx5 lkpq3BrqQ/5JuwEQHwxzTGa/+1Ut56hvy/rvNyctH/YwlGrNFFsqX3Qo2IkNOn8sElN5 K534OJoYf8ggxU8oBnFmXL+s03H0AcPyDOiO6DvbcYWb71tkeaR53ZYhiBhI/ePWY9Ee 9NXSzZNrX0bj1n1xyej6YCms9QKB9zyXoAGQomTZbK9Eq/RmZazyJZACaQIY6lTCixCN r07PA/Ioit4BTsywtAILc5/WixZBK/deJB/sBIV7KEcHtgWTcWux4x4/NTFAePOCm1G0 tlbw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 73si1033911pfu.71.2018.02.23.07.16.06; Fri, 23 Feb 2018 07:16:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752037AbeBWPQD (ORCPT + 28 others); Fri, 23 Feb 2018 10:16:03 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39924 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751834AbeBWPO1 (ORCPT ); Fri, 23 Feb 2018 10:14:27 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 8F6B1418E356E; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:13 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 08/11] perf vendor events arm64: add armv8-recommended.json Date: Sat, 24 Feb 2018 00:05:29 +0800 Message-ID: <1519401932-205051-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events. The JSON is copied from ARMv8 architecture reference manual, available here: https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf Signed-off-by: John Garry Signed-off-by: Shaokun Zhang --- .../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json new file mode 100644 index 0000000..6328828 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -0,0 +1,452 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "L1D_CACHE_RD", + "BriefDescription": "L1D cache access, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write", + "EventCode": "0x41", + "EventName": "L1D_CACHE_WR", + "BriefDescription": "L1D cache access, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "L1D_CACHE_REFILL_RD", + "BriefDescription": "L1D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "L1D_CACHE_REFILL_WR", + "BriefDescription": "L1D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, inner", + "EventCode": "0x44", + "EventName": "L1D_CACHE_REFILL_INNER", + "BriefDescription": "L1D cache refill, inner" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, outer", + "EventCode": "0x45", + "EventName": "L1D_CACHE_REFILL_OUTER", + "BriefDescription": "L1D cache refill, outer" + }, + { + "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", + "EventCode": "0x46", + "EventName": "L1D_CACHE_WB_VICTIM", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", + "EventCode": "0x47", + "EventName": "L1D_CACHE_WB_CLEAN", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 1 data cache invalidate", + "EventCode": "0x48", + "EventName": "L1D_CACHE_INVAL", + "BriefDescription": "L1D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "L1D_TLB_REFILL_RD", + "BriefDescription": "L1D tlb refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "L1D_TLB_REFILL_WR", + "BriefDescription": "L1D tlb refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "L1D_TLB_RD", + "BriefDescription": "L1D tlb access, read" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "L1D_TLB_WR", + "BriefDescription": "L1D tlb access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, read", + "EventCode": "0x50", + "EventName": "L2D_CACHE_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, write", + "EventCode": "0x51", + "EventName": "L2D_CACHE_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, read", + "EventCode": "0x52", + "EventName": "L2D_CACHE_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, write", + "EventCode": "0x53", + "EventName": "L2D_CACHE_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache Write-Back, victim", + "EventCode": "0x56", + "EventName": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency", + "EventCode": "0x57", + "EventName": "L2D_CACHE_WB_CLEAN", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 2 data cache invalidate", + "EventCode": "0x58", + "EventName": "L2D_CACHE_INVAL", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", + "EventCode": "0x5c", + "EventName": "L2D_TLB_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, write", + "EventCode": "0x5d", + "EventName": "L2D_TLB_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, read", + "EventCode": "0x5e", + "EventName": "L2D_TLB_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, write", + "EventCode": "0x5f", + "EventName": "L2D_TLB_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "BUS_ACCESS_RD", + "BriefDescription": "Bus access read" + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "BUS_ACCESS_WR", + "BriefDescription": "Bus access write" + } + { + "PublicDescription": "Bus access, Normal, Cacheable, Shareable", + "EventCode": "0x62", + "EventName": "BUS_ACCESS_SHARED", + "BriefDescription": "Bus access, Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", + "EventCode": "0x63", + "EventName": "BUS_ACCESS_NOT_SHARED", + "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, Normal", + "EventCode": "0x64", + "EventName": "BUS_ACCESS_NORMAL", + "BriefDescription": "Bus access, Normal" + } + { + "PublicDescription": "Bus access, peripheral", + "EventCode": "0x65", + "EventName": "BUS_ACCESS_PERIPH", + "BriefDescription": "Bus access, peripheral" + } + { + "PublicDescription": "Data memory access, read", + "EventCode": "0x66", + "EventName": "MEM_ACCESS_RD", + "BriefDescription": "Data memory access, read" + } + { + "PublicDescription": "Data memory access, write", + "EventCode": "0x67", + "EventName": "MEM_ACCESS_WR", + "BriefDescription": "Data memory access, write" + } + { + "PublicDescription": "Unaligned access, read", + "EventCode": "0x68", + "EventName": "UNALIGNED_LD_SPEC", + "BriefDescription": "Unaligned access, read" + } + { + "PublicDescription": "Unaligned access, write", + "EventCode": "0x69", + "EventName": "UNALIGNED_ST_SPEC", + "BriefDescription": "Unaligned access, write" + } + { + "PublicDescription": "Unaligned access", + "EventCode": "0x6a", + "EventName": "UNALIGNED_LDST_SPEC", + "BriefDescription": "Unaligned access" + } + { + "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", + "EventCode": "0x6c", + "EventName": "LDREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", + "EventCode": "0x6d", + "EventName": "STREX_PASS_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", + "EventCode": "0x6e", + "EventName": "STREX_FAIL_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", + "EventCode": "0x6f", + "EventName": "STREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" + } + { + "PublicDescription": "Operation speculatively executed, load", + "EventCode": "0x70", + "EventName": "LD_SPEC", + "BriefDescription": "Operation speculatively executed, load" + } + { + "PublicDescription": "Operation speculatively executed, store" + "EventCode": "0x71", + "EventName": "ST_SPEC", + "BriefDescription": "Operation speculatively executed, store" + } + { + "PublicDescription": "Operation speculatively executed, load or store", + "EventCode": "0x72", + "EventName": "LDST_SPEC", + "BriefDescription": "Operation speculatively executed, load or store" + } + { + "PublicDescription": "Operation speculatively executed, integer data processing", + "EventCode": "0x73", + "EventName": "DP_SPEC", + "BriefDescription": "Operation speculatively executed, integer data processing" + } + { + "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", + "EventCode": "0x74", + "EventName": "ASE_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", + } + { + "PublicDescription": "Operation speculatively executed, floating-point instruction", + "EventCode": "0x75", + "EventName": "VFP_SPEC", + "BriefDescription": "Operation speculatively executed, floating-point instruction" + } + { + "PublicDescription": "Operation speculatively executed, software change of the PC", + "EventCode": "0x76", + "EventName": "PC_WRITE_SPEC", + "BriefDescription": "Operation speculatively executed, software change of the PC" + } + { + "PublicDescription": "Operation speculatively executed, Cryptographic instruction", + "EventCode": "0x77", + "EventName": "CRYPTO_SPEC", + "BriefDescription": "Operation speculatively executed, Cryptographic instruction" + } + { + "PublicDescription": "Branch speculatively executed, immediate branch" + "EventCode": "0x78", + "EventName": "BR_IMMED_SPEC", + "BriefDescription": "Branch speculatively executed, immediate branch" + } + { + "PublicDescription": "Branch speculatively executed, procedure return" + "EventCode": "0x79", + "EventName": "BR_RETURN_SPEC", + "BriefDescription": "Branch speculatively executed, procedure return" + } + { + "PublicDescription": "Branch speculatively executed, indirect branch" + "EventCode": "0x7a", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed, indirect branch" + } + { + "PublicDescription": "Barrier speculatively executed, ISB" + "EventCode": "0x7c", + "EventName": "ISB_SPEC", + "BriefDescription": "Barrier speculatively executed, ISB" + } + { + "PublicDescription": "Barrier speculatively executed, DSB" + "EventCode": "0x7d", + "EventName": "DSB_SPEC", + "BriefDescription": "Barrier speculatively executed, DSB" + } + { + "PublicDescription": "Barrier speculatively executed, DMB" + "EventCode": "0x7e", + "EventName": "DMB_SPEC", + "BriefDescription": "Barrier speculatively executed, DMB" + } + { + "PublicDescription": "Exception taken, Other synchronous" + "EventCode": "0x81", + "EventName": "EXC_UNDEF", + "BriefDescription": "Exception taken, Other synchronous" + } + { + "PublicDescription": "Exception taken, Supervisor Call" + "EventCode": "0x82", + "EventName": "EXC_SVC", + "BriefDescription": "Exception taken, Supervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort" + "EventCode": "0x83", + "EventName": "EXC_PABORT", + "BriefDescription": "Exception taken, Instruction Abort" + } + { + "PublicDescription": "Exception taken, Data Abort and SError" + "EventCode": "0x84", + "EventName": "EXC_DABORT", + "BriefDescription": "Exception taken, Data Abort and SError" + } + { + "PublicDescription": "Exception taken, IRQ" + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + } + { + "PublicDescription": "Exception taken, FIQ" + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + } + { + "PublicDescription": "Exception taken, Secure Monitor Call" + "EventCode": "0x88", + "EventName": "EXC_SMC", + "BriefDescription": "Exception taken, Secure Monitor Call" + } + { + "PublicDescription": "Exception taken, Hypervisor Call" + "EventCode": "0x8a", + "EventName": "EXC_HVC", + "BriefDescription": "Exception taken, Hypervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "EventCode": "0x8b", + "EventName": "EXC_TRAP_PABORT", + "BriefDescription": "Exception taken, Instruction Abort not taken locally" + } + { + "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "EventCode": "0x8c", + "EventName": "EXC_TRAP_DABORT", + "BriefDescription": "Exception taken, Data Abort or SError not taken locally" + } + { + "PublicDescription": "Exception taken, Other traps not taken locally" + "EventCode": "0x8d", + "EventName": "EXC_TRAP_OTHER", + "BriefDescription": "Exception taken, Other traps not taken locally" + } + { + "PublicDescription": "Exception taken, IRQ not taken locally" + "EventCode": "0x8e", + "EventName": "EXC_TRAP_IRQ", + "BriefDescription": "Exception taken, IRQ not taken locally" + } + { + "PublicDescription": "Exception taken, FIQ not taken locally" + "EventCode": "0x8f", + "EventName": "EXC_TRAP_FIQ", + "BriefDescription": "Exception taken, FIQ not taken locally" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire" + "EventCode": "0x90", + "EventName": "RC_LD_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Store-Release" + "EventCode": "0x91", + "EventName": "RC_ST_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Store-Release" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, read" + "EventCode": "0xa0", + "EventName": "L3D_CACHE_RD", + "BriefDescription": "Attributable Level 3 data or unified cache access, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, write" + "EventCode": "0xa1", + "EventName": "L3D_CACHE_WR", + "BriefDescription": "Attributable Level 3 data or unified cache access, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, read" + "EventCode": "0xa2", + "EventName": "L3D_CACHE_REFILL_RD", + "BriefDescription": "Attributable Level 3 data or unified cache refill, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, write" + "EventCode": "0xa3", + "EventName": "L3D_CACHE_REFILL_WR", + "BriefDescription": "Attributable Level 3 data or unified cache refill, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + "EventCode": "0xa6", + "EventName": "L3D_CACHE_WB_VICTIM", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + "EventCode": "0xa7", + "EventName": "L3D_CACHE_WB_CLEAN", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate" + "EventCode": "0xa8", + "EventName": "L3D_CACHE_INVAL", + "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate" + } +] From patchwork Fri Feb 23 16:05:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129370 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp747375edc; Fri, 23 Feb 2018 07:14:28 -0800 (PST) X-Google-Smtp-Source: AH8x226FsMAQ7yYG0xL10Sx/BU72BGuJPrcu6xRm5ynzSEm3sd6GZSkRZC6R7ASOGjtjFrdur2/U X-Received: by 10.98.22.65 with SMTP id 62mr2077052pfw.211.1519398868376; Fri, 23 Feb 2018 07:14:28 -0800 (PST) ARC-Seal: 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[209.132.180.67]) by mx.google.com with ESMTP id e6-v6si1962814plo.525.2018.02.23.07.14.28; Fri, 23 Feb 2018 07:14:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751895AbeBWPOY (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:24 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39890 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751785AbeBWPOX (ORCPT ); Fri, 23 Feb 2018 10:14:23 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 59FFB6AB46FA1; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:14 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events Date: Sat, 24 Feb 2018 00:05:30 +0800 Message-ID: <1519401932-205051-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. The brief description is kept for readability, but is not strictly required. Cc: Ganapatrao Kulkarni Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 60 ++++++++-------------- 1 file changed, 20 insertions(+), 40 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c4..f47bf0f 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,42 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D cache refill, inner" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "0x60", + "BriefDescription": "Bus access read" }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "0x61", + "BriefDescription": "Bus access write" } ] From patchwork Fri Feb 23 16:05:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129371 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp747487edc; Fri, 23 Feb 2018 07:14:35 -0800 (PST) X-Google-Smtp-Source: AH8x2267MdWtVYasGHLMu90wa+s8GElQ0rmjJYA27r4sETNvEjp56lIBBxkgNEsSvwnZRkq8J28K X-Received: by 2002:a17:902:f44:: with SMTP id 62-v6mr1997052ply.27.1519398875037; Fri, 23 Feb 2018 07:14:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398875; cv=none; d=google.com; s=arc-20160816; b=csDtAPaJnCO4xmIinALFy2gwAefnKceVSjFXNxdO8jsRv6Z237/F7hw14qkKZa5sSJ VMuD4CrpuB9Or4VEyZXaackfm4vKIQo5SHhGk5B+XxcwZX3X683oLTcCmYmkLfCypPxp 0ge8JKXkALkPdZaN3dkaoBNdqJ0F8IrDDTTxptQF6yqZEGQf+uCW6GquEjCzKgtpQs/i j5jTKLS+uZlVfYdvsZQx3Ed6t1+MPreo3nk96vJYp+iqh+afCQNkXMnyaXfoJkDp78kZ q+aWg3flJxvloJS31By3fi0n5lDpplyAcnGqK6Iz1qU1k8OTGNVBegOV63ZIR3q/P9TH 56Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=PAypKjg3CI82ewkp0yIuUJM0vbQyAj8XuumkPw2VYUc=; b=yXtS1VKse0yidwyfqfHKwWhfF0zTZrLlQ6UQjnsN4t4QYd6LcStEaxmX+0ihQrdI0h v/FUQCYMEebUCx9kSZ1XkGnuMCUUJeZ8VB2Dae6RuOgNkdB9aZ1IB1SY+53zVC140+06 ydaAFQbTlCKY3+4nBbL6zB0FRL/A4qgc7iLCpFY+9DYtQJ5Izgn8KCtw+Qe+w2lopwoc ckNelW6DavWfEzvtrgVEpkdZTnPFmAKaq4pgypNZpax34pwOyOdggS7Hf0bNo3ws+Nhh iZYy4C/X4qN1izklaml1p7VdEFg2Lk+7W5daYQy+aFkwKo/OmzDv1ApnLv0UVdDbC3NE fWhQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6-v6si1962814plo.525.2018.02.23.07.14.34; Fri, 23 Feb 2018 07:14:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752031AbeBWPOc (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:32 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:39896 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751799AbeBWPO0 (ORCPT ); Fri, 23 Feb 2018 10:14:26 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6AA6A5B75517F; Fri, 23 Feb 2018 23:14:19 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:14 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 10/11] perf vendor events arm64: fixup A53 to use recommended events Date: Sat, 24 Feb 2018 00:05:31 +0800 Message-ID: <1519401932-205051-11-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes the ARM Cortex-A53 json to use event definition from the ARMv8 recommended events. The brief description is kept for readability, but is not strictly required. In addition to this change, other changes were made: - remove stray ',' - remove mirrored events in memory.json and bus.json - fixed indentation to be consistent with other ARM JSONs Cc: William Cohen Signed-off-by: John Garry --- .../arch/arm64/arm/cortex-a53/branch.json | 15 ++++--- .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 24 +++-------- .../arch/arm64/arm/cortex-a53/cache.json | 40 +++++++++---------- .../arch/arm64/arm/cortex-a53/memory.json | 14 +------ .../arch/arm64/arm/cortex-a53/other.json | 46 +++++++++++----------- .../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++----- 6 files changed, 67 insertions(+), 92 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json index 3b62087..efcebaa 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -1,25 +1,24 @@ [ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" + { + "ArchStdEvent": "0x7A", + "BriefDescription": "Branch speculatively executed, indirect branch" }, - {, + { "EventCode": "0xC9", "EventName": "BR_COND", "BriefDescription": "Conditional branch executed" }, - {, + { "EventCode": "0xCA", "EventName": "BR_INDIRECT_MISPRED", "BriefDescription": "Indirect branch mispredicted" }, - {, + { "EventCode": "0xCB", "EventName": "BR_INDIRECT_MISPRED_ADDR", "BriefDescription": "Indirect branch mispredicted because of address miscompare" }, - {, + { "EventCode": "0xCC", "EventName": "BR_COND_MISPRED", "BriefDescription": "Conditional branch mispredicted" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json index 480d9f7..bbbc930 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -1,22 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" + { + "ArchStdEvent": "0x60", + "BriefDescription": "Bus access read" }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" + { + "ArchStdEvent": "0x61", + "BriefDescription": "Bus access write" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json index 11baad6..5dfbec4 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -1,27 +1,27 @@ [ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" + { + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" + { + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" + { + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" + { + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" + { + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json index 480d9f7..25ae642 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -1,20 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, + { "EventCode": "0xC0", "EventName": "EXT_MEM_REQ", "BriefDescription": "External memory request" }, - {, + { "EventCode": "0xC1", "EventName": "EXT_MEM_REQ_NC", "BriefDescription": "Non-cacheable external memory request" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json index 73a2240..4eb17a8 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -1,32 +1,30 @@ [ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" + { + "ArchStdEvent": "0x86", + "BriefDescription": "Exception taken, IRQ" }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" + { + "ArchStdEvent": "0x87", + "BriefDescription": "Exception taken, FIQ" }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" + { + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + { + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + { + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" + { + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json index 3149fb9..f45a6b5 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -1,50 +1,50 @@ [ - {, + { "EventCode": "0xC7", "EventName": "STALL_SB_FULL", "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" }, - {, + { "EventCode": "0xE0", "EventName": "OTHER_IQ_DEP_STALL", "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" }, - {, + { "EventCode": "0xE1", "EventName": "IC_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" }, - {, + { "EventCode": "0xE2", "EventName": "IUTLB_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" }, - {, + { "EventCode": "0xE3", "EventName": "DECODE_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" }, - {, + { "EventCode": "0xE4", "EventName": "OTHER_INTERLOCK_STALL", "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" }, - {, + { "EventCode": "0xE5", "EventName": "AGU_DEP_STALL", "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" }, - {, + { "EventCode": "0xE6", "EventName": "SIMD_DEP_STALL", "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." }, - {, + { "EventCode": "0xE7", "EventName": "LD_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" }, - {, + { "EventCode": "0xE8", "EventName": "ST_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" From patchwork Fri Feb 23 16:05:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 129373 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp747686edc; Fri, 23 Feb 2018 07:14:44 -0800 (PST) X-Google-Smtp-Source: AH8x225Pjg+FC1Nrve+Wt7F8L1vGCgAPqIiYzS03lUfR4NPKie6fPVbjF1pf0GEkSEF2H1r+WX35 X-Received: by 2002:a17:902:684:: with SMTP id 4-v6mr1995639plh.262.1519398884290; Fri, 23 Feb 2018 07:14:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519398884; cv=none; d=google.com; s=arc-20160816; b=q78siRx5/BwJbdkAl8LZOlqY/Uv1JJxqMHdkfqC/XrdY6yGgSu8zL9soBRClD/RaZc MWS4rlRoCw/xQdYAfRn/i3D3pM5lBm6IM+dI2SqAn4Is0th1lS2efHMWlY/FViPWD2Yz CFtJPhXyFeWHYcMqTTV4R1EobYNJhd3z/51RPP0jGYTtPN/SMSE65+tfenJyLlWKv8mG ud/P5nROacQEengmYVJi7rORcbsX0/kVYGBYbIsJ1uKHFmOSMvXmfgk3572Q+2pxd6UW dcxkFWqJ4O7FUrfoioM9HpqF1Js4VbuIbO+/kQzsWgIy8FtTOQyK04co8azunEMR7Nlr C6DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=AVTyrTOlJiUvCv/JQhFfqx/tSYgQINBzwgRknjL03Is=; b=wXde/cc/TAVzfshVcVFDfeLl4qiJeShsKrnB40N+sFYlRqrr0YRmo3cQBG8hOPimOU n6y6nAnokOhwrRb7lNHG0onv4pH2vH4EGIwwM4Up+NaqYvqHW6MftRElDir2HiwmVCgC 6QIQFN4r9rl3dCwMYPq6rG3vMD0ih2jqGS9Ie30peP1qrgNmRkX+12MCKi+CWNpLM4wT Qv0c83kcbg3Xq+T9UzMekMIYay0fQVAgR93P4II7oFmakBIxBLAKyI/W5k24h7v3xAjy IPjEkZicDkzpTnzCaUaoedJhcVVivO3di+LmaFAFJSQ+QUtl8OwVdOkDGzCS8H2rnLt3 NjGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a190si1627611pge.436.2018.02.23.07.14.44; Fri, 23 Feb 2018 07:14:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751965AbeBWPOk (ORCPT + 28 others); Fri, 23 Feb 2018 10:14:40 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:56530 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751472AbeBWPOi (ORCPT ); Fri, 23 Feb 2018 10:14:38 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B5DDD1BFBA8FF; Fri, 23 Feb 2018 23:14:24 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Fri, 23 Feb 2018 23:14:14 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH v2 11/11] perf vendor events arm64: add HiSilicon hip08 JSON file Date: Sat, 24 Feb 2018 00:05:32 +0800 Message-ID: <1519401932-205051-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519401932-205051-1-git-send-email-john.garry@huawei.com> References: <1519401932-205051-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. The brief description is kept for readability, but is not strictly required. Signed-off-by: John Garry --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 140 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 141 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 0000000..ca0be5e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,140 @@ +[ + { + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" + }, + { + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" + }, + { + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" + }, + { + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" + }, + { + "ArchStdEvent": "0x46", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x47", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x48", + "BriefDescription": "L1D cache invalidate" + }, + { + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D tlb refill, read" + }, + { + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" + }, + { + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" + }, + { + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" + }, + { + "ArchStdEvent": "0x50", + "BriefDescription": "L2D cache access, read" + }, + { + "ArchStdEvent": "0x51", + "BriefDescription": "L2D cache access, write" + }, + { + "ArchStdEvent": "0x52", + "BriefDescription": "L2D cache refill, read" + }, + { + "ArchStdEvent": "0x53", + "BriefDescription": "L2D cache refill, write" + }, + { + "ArchStdEvent": "0x56", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x57", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x58", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index cf14e23..8f11aeb 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,3 +14,4 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core