From patchwork Wed Feb 21 10:15:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129008 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451198ljc; Wed, 21 Feb 2018 02:15:41 -0800 (PST) X-Google-Smtp-Source: AH8x227gVvMgaRMGGglVRpnotOQq9SAOIWLCureFkiL7voWdmaLig+ftSKP8HMk2oqIfLBv260Dk X-Received: by 10.99.111.137 with SMTP id k131mr2331318pgc.11.1519208141845; Wed, 21 Feb 2018 02:15:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519208141; cv=none; d=google.com; s=arc-20160816; b=rzGzv7lMRWzEaFpe7u1tpOXJPe3O9Y2H43qFUYHiYzvL7gW8slZjSSQgVOqcEDgLt5 8a9fcwfhD51/mdo9Hwe92op+qFMjlVE8kamLnsd06KJjGPsrAnS67S5kKR3CJ0bfrxuK jkW7rO33UGJGkH8kmCUM+pgsJF0wYZRFVaG679GiHR8VngGyQ2eysVWmBCtSFBmGwQZW 2jixBg4vc+GN8G35OjDCprcFhdnULvvkwaB26b3vv/KA3YjNLLC7mQX9/9fi+mhRS3lR aoIwWFO8uW1UYCBvaOViT85FpXjlnI3pSYZjUlIuh4iwlEVFXkuReonbL952iZo2HweG aEkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=twXUCVmE+TRy5raSbpAu2AHq8M0nmDoxkdU+OV6X6As=; b=1Lq6EkeYsI548D54y7dvM577HpqeTzvNFV2D6N0QQMhp4qveSNpfiLOsLpSf8+AjJI reJ3Lmm6DBIco0E0O4R1FbSf4M/w3Uk/BO9dPRw1ud9heUgzWZa0cKhVs35tHi4+H26Q Uvw5HscKuijC4qPjZId3LFt8TwyBdoqzYJ523wLZGnmhR48O46M/brKqbLubgiKkX4xf U+IC8RibTvthY56puj3qd2Y3Q/xVxrumrCPlXwTozhbJEDeCZtzkziUd8TF5KLc0W/QY okOI1OcqT/fanPEDdptnrLV30hd0UGetlpNJ3oV/E54ae9DHv5CPa/JmF6557cXCdmJu TTfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=I7nosfjH; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 21 Feb 2018 10:15:34 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 5C.81.17380.5C64D8A5; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180221101533eucas1p234b1801844ce8fac633377d129323422~VT798w9j_1442414424eucas1p2f; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) X-AuditID: cbfec7f4-713ff700000043e4-13-5a8d46c56ad8 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id CD.E2.04178.5C64D8A5; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P4H005K9WHT4SB0@eusync3.samsung.com>; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 1/6] soc: samsung: pm_domains: Add blacklisting clock handling Date: Wed, 21 Feb 2018 11:15:22 +0100 Message-id: <20180221101527.25554-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180221101527.25554-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsWy7djP87pH3XqjDHbf0LbYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6M7c9vsxWc4aqY//00cwPjY44uRk4OCQETiS1LzzF3MXJxCAmsYJTY2tHF BOF8ZpSYfamHFabqzIyTrBCJZYwSD1feYoNwGpgkfnQ3MoNUsQkYSnS97WIDsUUEHCQ+f3rN CFLELNDGJHH2wH4mkISwQIBE6/ftYDaLgKpE48cL7F2MHBy8ArYSD6YYQ2yTl1j8fScbSJhT wE5i50sOkDESAn9ZJQ729jGCxCUEXCQuHeOBKBeWeHV8CzuELSPR2XGQCaK+n1Hi3/+XUM4M Ron1H1uhqqwlDh+/CPYaswCfxKRt05khhvJKdLQJQZR4SKxb9ooNIuwosXWFJMS/Exkl7vWf YpvAKLWAkWEVo3hqaXFuemqxUV5quV5xYm5xaV66XnJ+7iZGYDSe/nf8yw7GXX+SDjEKcDAq 8fC+MOiJEmJNLCuuzD3EKMHBrCTCWynUGyXEm5JYWZValB9fVJqTWnyIUZqDRUmcN06jLkpI ID2xJDU7NbUgtQgmy8TBKdXAuLGuTutSi8TLZ1ttVHLZFdzjwg/+nun45LdU89vY3B2Pbjb4 rcpRvMvwdlObkMr2K0E7RaQ0zfYKRy5tbInYybJOyil3c+QlN3+OBqnljsdbWOfca2T6WtKY 9yJ30e8yqysGW06+WFXw1Ivj4JK/XDw3yo8luqbySmst7WX0uViweArXdJVoJZbijERDLeai 4kQAiy+Rd8ICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkluLIzCtJLcpLzFFi42I5/e/4Vd2jbr1RBnsPs1psnLGe1eL6l+es FpPuT2CxOH9+A7vFx557rBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfG9ue32QrOcFXM/36auYHxMUcXIyeHhICJxJkZJ1m7GLk4hASWMEr8PdYC 5TQxSbR1L2cDqWITMJToetsFZosIOEh8/vSaEaSIWaCDSWLP3odgCWEBP4kdk7sZQWwWAVWJ xo8X2LsYOTh4BWwlHkwxhtgmL7H4+042kDCngJ3EzpdgRwgBVUxb+5Z9AiPPAkaGVYwiqaXF uem5xYZ6xYm5xaV56XrJ+bmbGIEBs+3Yz807GC9tDD7EKMDBqMTDa6HTEyXEmlhWXJl7iFGC g1lJhLdSqDdKiDclsbIqtSg/vqg0J7X4EKM0B4uSOO95g8ooIYH0xJLU7NTUgtQimCwTB6dU A+PC6pigRul9986/57s4+eLjgsX3H6pOsjw2a6WEXtbBh5HycddXffN29FvjwXvAsjVIr0xl 7ts/m5b0/f/x8A+PvM3umbevmHM1zpv0Laxzas7v109S9adeKLK4YXfDbx27qXuLsGqf2tpP n/TVsmeFzXzBNzvpwgeDlf2Tfm+TnxAorvy+nXGOEktxRqKhFnNRcSIAualOABQCAAA= X-CMS-MailID: 20180221101533eucas1p234b1801844ce8fac633377d129323422 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180221101533eucas1p234b1801844ce8fac633377d129323422 X-RootMTR: 20180221101533eucas1p234b1801844ce8fac633377d129323422 References: <20180221101527.25554-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Handling of clock reparenting will be move to clock controller driver, so add possibility to blacklist clock handling on systems, where the clock controller already does all needed operations. This is needed to avoid potential deadlock on clock reparenting during power domain on/off procedure. Signed-off-by: Marek Szyprowski --- drivers/soc/samsung/pm_domains.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Krzysztof Kozlowski diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index b6a436594a19..cef30bdf19b1 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -147,6 +147,9 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } +static const char *soc_force_no_clk[] = { +}; + static __init int exynos4_pm_init_power_domain(void) { struct device_node *np; @@ -183,6 +186,11 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_on = exynos_pd_power_on; pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; + for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++) + if (of_find_compatible_node(NULL, NULL, + soc_force_no_clk[i])) + goto no_clk; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { char clk_name[8]; From patchwork Wed Feb 21 10:15:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129009 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451223ljc; Wed, 21 Feb 2018 02:15:43 -0800 (PST) X-Google-Smtp-Source: AH8x2247a5S+W42jyB0iwAmz0bkpIg6L3nOdGMre7/m7pZ0k62gVrhDZx4/FzBSGZeX2y7FMY5J5 X-Received: by 10.99.120.205 with SMTP id t196mr2244729pgc.392.1519208143148; Wed, 21 Feb 2018 02:15:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519208143; cv=none; d=google.com; s=arc-20160816; b=C6uN2I/XzNKKlOXSzMzQ1PQ9YBvuLe0zPb7CAvqn41aEfmRXcslKGTPQcJNll/wpb+ yPdm8NW3BreD1jG9GqyFn5V9SpSAHQrCxqLOuBV5CsPIxo6YTb1OeJTLC9nY/gLh6RAe CosRQ1UJ3qA+KE3AeonJKLwsDxd69+2ANra04i+SaK8C1HK33XeUm31Zo84l6t+TIX9Q 13botcZyQ62QtoWenNET0DUMU/A0Ute4UaBOUTItPXAWnjnmQHxWIQ4Gq8lZLJW5vvU6 darHFASlkZ49wnTxeZSOSoxSdqbE1MhQgDiVlBm9W7cyOHUlaiFTsKc2aluQmzPpNLaS lhrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=VS7K9uGmzJPkk92sUuX9MmV2bPQY32jU3xixG1aQjcg=; b=SWgLp1DT5rBk5A5ZpqOImh0MaWMqICcbDQxIKEt0p1UezcX8w71b+Ml2I0gd5ErNia IDcfLnEaAYvW9tVc+5fMGrplWKXY7lshqJ0V+Jvd2UTTBdX++vMeuckr68zdBxUCRToV eOn1LfbIfSnelzKyU2NDoSX/ZXT65cDb3b+sk5V/RPj7XoIJI3RxgICaSNgKm0WR/vW3 2jedkxxGO3KcVglemwcHnzJABjDpTHKrW9koUde1a/YvbLIBm6gaMtwf+STazZt3LOyC 6DzG478TU3DuiPaDo3zJx/1rCKRw5PnHMJBrIsa/PICxZIR2bp/rGcFOHpzYHuchDdEu xw9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=P07KePiB; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Handling integration of clock controller and power domain can be done using runtime PM feature of CCF framework. This however needs a separate struct device for each power domain. This patch adds such separate driver for group such clocks, which can be instantiated more than once, each time for a different power domain. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5x-subcmu.c | 180 ++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5x-subcmu.h | 30 +++++ 2 files changed, 210 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5x-subcmu.c create mode 100644 drivers/clk/samsung/clk-exynos5x-subcmu.h -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos5x-subcmu.c b/drivers/clk/samsung/clk-exynos5x-subcmu.c new file mode 100644 index 000000000000..9ff6d5d17f57 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5x-subcmu.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * Author: Marek Szyprowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5x power-domain dependent + * sub-CMUs + */ + +#include +#include +#include +#include + +#include "clk.h" +#include "clk-exynos5x-subcmu.h" + +static struct samsung_clk_provider *ctx; +static const struct samsung_5x_subcmu_info *cmu; +static int nr_cmus; + +static void samsung_ext_clk_save(void __iomem *base, + struct samsung_clk_ext_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) { + rd->save = readl(base + rd->offset); + writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); + rd->save &= rd->mask; + } +}; + +static void samsung_ext_clk_restore(void __iomem *base, + struct samsung_clk_ext_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + writel((readl(base + rd->offset) & ~rd->mask) | rd->save, + base + rd->offset); +} + +static int __maybe_unused exynos5x_clk_subcmu_suspend(struct device *dev) +{ + struct samsung_5x_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + samsung_ext_clk_save(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static int __maybe_unused exynos5x_clk_subcmu_resume(struct device *dev) +{ + struct samsung_5x_subcmu_info *info = dev_get_drvdata(dev); + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + samsung_ext_clk_restore(ctx->reg_base, info->suspend_regs, + info->nr_suspend_regs); + spin_unlock_irqrestore(&ctx->lock, flags); + + return 0; +} + +static void samsung_clk_defer_gate(struct samsung_clk_provider *ctx, + const struct samsung_gate_clock *list, int nr_clk) +{ + while (nr_clk--) + samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id); +} + +void samsung_clk_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus, + const struct samsung_5x_subcmu_info *_cmu) +{ + ctx = _ctx; + cmu = _cmu; + nr_cmus = _nr_cmus; + + for (; _nr_cmus--; _cmu++) { + samsung_clk_defer_gate(ctx, _cmu->gate_clks, _cmu->nr_gate_clks); + samsung_ext_clk_save(ctx->reg_base, _cmu->suspend_regs, + _cmu->nr_suspend_regs); + } +} + +static int __init exynos5x_clk_subcmu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct samsung_5x_subcmu_info *info = dev_get_drvdata(dev); + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + pm_runtime_get(dev); + + ctx->dev = dev; + samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks); + samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks); + ctx->dev = NULL; + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops exynos5x_disp_pm_ops = { + SET_RUNTIME_PM_OPS(exynos5x_clk_subcmu_suspend, + exynos5x_clk_subcmu_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver exynos5x_clk_subcmu_driver __refdata = { + .driver = { + .name = "exynos5x-clock-subcmu", + .suppress_bind_attrs = true, + .pm = &exynos5x_disp_pm_ops, + }, + .probe = exynos5x_clk_subcmu_probe, +}; + +static int __init exynos_5x_clk_register_subcmu(struct device *parent, + const struct samsung_5x_subcmu_info *info, + struct device_node *pd_node) +{ + struct of_phandle_args genpdspec = { .np = pd_node }; + struct platform_device *pdev; + + pdev = platform_device_alloc(info->pd_name, -1); + pdev->dev.parent = parent; + pdev->driver_override = "exynos5x-clock-subcmu"; + platform_set_drvdata(pdev, (void *)info); + of_genpd_add_device(&genpdspec, &pdev->dev); + platform_device_add(pdev); + + return 0; +} + +static int __init exynos5x_clk_probe(struct platform_device *pdev) +{ + struct device_node *np; + const char *name; + int i; + + for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { + if (of_property_read_string(np, "label", &name) < 0) + continue; + for (i = 0; i < nr_cmus; i++) + if (strcmp(cmu[i].pd_name, name) == 0) + exynos_5x_clk_register_subcmu(&pdev->dev, + &cmu[i], np); + } + return 0; +} + +static const struct of_device_id exynos5x_clk_of_match[] = { + { }, +}; + +static struct platform_driver exynos5x_clk_driver __refdata = { + .driver = { + .name = "exynos5x-clock", + .of_match_table = exynos5x_clk_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos5x_clk_probe, +}; + +static int __init exynos5x_clk_drv_init(void) +{ + platform_driver_register(&exynos5x_clk_driver); + platform_driver_register(&exynos5x_clk_subcmu_driver); + return 0; +} +core_initcall(exynos5x_clk_drv_init); diff --git a/drivers/clk/samsung/clk-exynos5x-subcmu.h b/drivers/clk/samsung/clk-exynos5x-subcmu.h new file mode 100644 index 000000000000..b44c238e54fa --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5x-subcmu.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5x power-domain dependent + * sub-CMUs +*/ + +struct samsung_clk_ext_reg_dump { + u32 offset; + u32 value; + u32 mask; + u32 save; +}; + +struct samsung_5x_subcmu_info { + const struct samsung_div_clock *div_clks; + unsigned int nr_div_clks; + const struct samsung_gate_clock *gate_clks; + unsigned int nr_gate_clks; + struct samsung_clk_ext_reg_dump *suspend_regs; + unsigned int nr_suspend_regs; + const char *pd_name; +}; + +void samsung_clk_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus, + const struct samsung_5x_subcmu_info *cmu); From patchwork Wed Feb 21 10:15:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129010 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451241ljc; Wed, 21 Feb 2018 02:15:44 -0800 (PST) X-Google-Smtp-Source: AH8x224QTSniPx801eVWiehyQ/P3SDjMQuPZ0ag96ziLJEAzUUanuqrKTpUyLDQCEJtkcSfl8V+v X-Received: by 2002:a17:902:9693:: with SMTP id n19-v6mr2656205plp.69.1519208144483; Wed, 21 Feb 2018 02:15:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519208144; cv=none; d=google.com; s=arc-20160816; b=0lsn4Qo58tjrOW9GN556tMEZj2lV2UQIbO68El1hKn/7CT98zDW+OJ+o0N1TkY/lGz VoLkaMwJ/BMeUJeSC8nD+ozcMwPAdyzjm2JD73opPzjPJvnX/muv6rk2/xAuuRuW3Uhv 4TWMaGecYmo6Hk83De8RvV1uc5rvlH9tth9CoSvlpVqCNMZZXUk8VkBERKDEteI7Mv8x 5SPykKD4caoLIz37w4eTiiu8l8igBVYfgk3eR4ba/D6se5jmGu9GKSg5HEQ1Ce608vl/ vEhqsr0bOkLVSZ19HeIBNpxuyIBVwysPAYNRgSl0Vyl+1qa1R8zZpFEh+RreV1KdciuF mUAA== ARC-Message-Signature: i=1; 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Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5x sub-CMU driver instantiated from Exynos5420 driver. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5420.c | 121 +++++++++++++++++++++++------- drivers/clk/samsung/clk-exynos5x-subcmu.c | 2 + drivers/soc/samsung/pm_domains.c | 2 + 4 files changed, 100 insertions(+), 26 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ef8900bc077f..f70b3f66be89 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5x-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 45d34f601e9e..dbf4b5243987 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -19,6 +19,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5x-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -863,7 +864,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), - DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), @@ -912,8 +912,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), - /* Mfc Block */ - DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), /* PCM */ DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), @@ -932,8 +930,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), /* GSCL Block */ - DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", - DIV2_RATIO0, 4, 2), DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), /* MSCL Block */ @@ -1190,8 +1186,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", GATE_TOP_SCLK_GSCL, 7, 0, 0), - GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), - GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", GATE_IP_GSCL0, 4, 0, 0), GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", @@ -1205,10 +1199,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_IP_GSCL1, 3, 0, 0), GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", GATE_IP_GSCL1, 4, 0, 0), - GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", - GATE_IP_GSCL1, 6, 0, 0), - GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", - GATE_IP_GSCL1, 7, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", @@ -1227,18 +1217,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", GATE_IP_MSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), - GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), - GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), - GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), - GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", - GATE_IP_DISP1, 7, 0, 0), - GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", - GATE_IP_DISP1, 8, 0, 0), - GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", - GATE_IP_DISP1, 9, 0, 0), - /* ISP */ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), @@ -1255,11 +1233,98 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +}; + +static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { + DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), +}; + +static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), + GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), + GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), + GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), + GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", + GATE_IP_DISP1, 7, 0, 0), + GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", + GATE_IP_DISP1, 8, 0, 0), + GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", + GATE_IP_DISP1, 9, 0, 0), +}; + +static struct samsung_clk_ext_reg_dump exynos_5x_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ + { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ + { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ + { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ +}; + +static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { + DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", + DIV2_RATIO0, 4, 2), +}; + +static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { + GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), + GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), + GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", + GATE_IP_GSCL1, 6, 0, 0), + GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", + GATE_IP_GSCL1, 7, 0, 0), +}; + +static struct samsung_clk_ext_reg_dump exynos_5x_gsc_suspend_regs[] = { + { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ + { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ + { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ + { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ +}; + +static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), +}; + +static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), +}; - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +static struct samsung_clk_ext_reg_dump exynos_5x_mfc_suspend_regs[] = { + { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ + { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ + { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ +}; + +static const struct samsung_5x_subcmu_info exynos_5x_subcmus[] = { + { + .div_clks = exynos5x_disp_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), + .gate_clks = exynos5x_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), + .suspend_regs = exynos_5x_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_disp_suspend_regs), + .pd_name = "DISP", + }, { + .div_clks = exynos5x_gsc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), + .gate_clks = exynos5x_gsc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), + .suspend_regs = exynos_5x_gsc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_gsc_suspend_regs), + .pd_name = "GSC", + }, { + .div_clks = exynos5x_mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), + .gate_clks = exynos5x_mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), + .suspend_regs = exynos_5x_mfc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_mfc_suspend_regs), + .pd_name = "MFC", + }, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { @@ -1472,6 +1537,8 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); exynos5420_clk_sleep_init(); + samsung_clk_subcmus_init(ctx, ARRAY_SIZE(exynos_5x_subcmus), + exynos_5x_subcmus); samsung_clk_of_add_provider(np, ctx); } @@ -1480,10 +1547,12 @@ static void __init exynos5420_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5420); } -CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", + exynos5420_clk_init); static void __init exynos5800_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5800); } -CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", + exynos5800_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5x-subcmu.c b/drivers/clk/samsung/clk-exynos5x-subcmu.c index 9ff6d5d17f57..256473b83264 100644 --- a/drivers/clk/samsung/clk-exynos5x-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5x-subcmu.c @@ -159,6 +159,8 @@ static int __init exynos5x_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5x_clk_of_match[] = { + { .compatible = "samsung,exynos5420-clock", }, + { .compatible = "samsung,exynos5800-clock", }, { }, }; diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index cef30bdf19b1..f2d6d7a09c16 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -148,6 +148,8 @@ static __init const char *exynos_get_domain_name(struct device_node *node) } static const char *soc_force_no_clk[] = { + "samsung,exynos5420-clock", + "samsung,exynos5800-clock", }; static __init int exynos4_pm_init_power_domain(void) From patchwork Wed Feb 21 10:15:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129011 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451259ljc; Wed, 21 Feb 2018 02:15:45 -0800 (PST) X-Google-Smtp-Source: AH8x225/kRy7fZiqyHJcngX0ScfoMrrGId+ZdLWa0UYiM6rAkx5ZxIsYUIoZcbHDDJfW+gZGN619 X-Received: by 2002:a17:902:59d3:: with SMTP id d19-v6mr2662584plj.394.1519208145225; Wed, 21 Feb 2018 02:15:45 -0800 (PST) ARC-Seal: i=1; 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Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5x sub-CMU driver instantiated from Exynos5250 driver. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5250.c | 51 +++++++++++++++++++++---------- drivers/clk/samsung/clk-exynos5x-subcmu.c | 1 + drivers/soc/samsung/pm_domains.c | 1 + 4 files changed, 38 insertions(+), 16 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index f70b3f66be89..d265f4babfb0 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5x-subcmu.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 9b073c98a891..876fa4c122ca 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -18,6 +18,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5x-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -571,17 +572,6 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, - 0), - GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, - 0), - GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, - 0), - GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, - 0), - GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, - 0), GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, @@ -671,10 +661,6 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), - GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 9, 0, 0), - GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", - GATE_IP_DISP1, 8, 0, 0), GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", GATE_IP_ISP0, 8, 0, 0), @@ -698,6 +684,38 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE_IP_ISP1, 7, 0, 0), }; +static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, + 0), + GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, + 0), + GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, + 0), + GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, + 0), + GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, + 0), + GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 9, 0, 0), + GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", + GATE_IP_DISP1, 8, 0, 0), +}; + +static struct samsung_clk_ext_reg_dump exynos_5250_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */ + { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */ +}; + +static const struct samsung_5x_subcmu_info exynos_5250_disp_subcmu = { + .gate_clks = exynos5250_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks), + .suspend_regs = exynos_5250_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5250_disp_suspend_regs), + .pd_name = "DISP1", +}; + static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -859,10 +877,11 @@ static void __init exynos5250_clk_init(struct device_node *np) __raw_writel(tmp, reg_base + PWR_CTRL2); exynos5250_clk_sleep_init(); + samsung_clk_subcmus_init(ctx, 1, &exynos_5250_disp_subcmu); samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", _get_rate("div_arm2")); } -CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5x-subcmu.c b/drivers/clk/samsung/clk-exynos5x-subcmu.c index 256473b83264..483f70c2dd40 100644 --- a/drivers/clk/samsung/clk-exynos5x-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5x-subcmu.c @@ -159,6 +159,7 @@ static int __init exynos5x_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5x_clk_of_match[] = { + { .compatible = "samsung,exynos5250-clock", }, { .compatible = "samsung,exynos5420-clock", }, { .compatible = "samsung,exynos5800-clock", }, { }, diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index f2d6d7a09c16..caf45cf7aa8e 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -148,6 +148,7 @@ static __init const char *exynos_get_domain_name(struct device_node *node) } static const char *soc_force_no_clk[] = { + "samsung,exynos5250-clock", "samsung,exynos5420-clock", "samsung,exynos5800-clock", }; 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Mark clock related properties in Exynos power domain bindings as deprecated. This change has no inpact on backwards-compatibility, as the new drivers properly work with old DTBs (deprecated properties are ignored). Signed-off-by: Marek Szyprowski --- .../devicetree/bindings/power/pd-samsung.txt | 20 +---- drivers/soc/samsung/pm_domains.c | 90 +--------------------- 2 files changed, 5 insertions(+), 105 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt index 549f7dee9b9d..92ef355e8f64 100644 --- a/Documentation/devicetree/bindings/power/pd-samsung.txt +++ b/Documentation/devicetree/bindings/power/pd-samsung.txt @@ -15,23 +15,13 @@ Required Properties: Optional Properties: - label: Human readable string with domain name. Will be visible in userspace to let user to distinguish between multiple domains in SoC. -- clocks: List of clock handles. The parent clocks of the input clocks to the - devices in this power domain are set to oscclk before power gating - and restored back after powering on a domain. This is required for - all domains which are powered on and off and not required for unused - domains. -- clock-names: The following clocks can be specified: - - oscclk: Oscillator clock. - - clkN: Input clocks to the devices in this power domain. These clocks - will be reparented to oscclk before switching power domain off. - Their original parent will be brought back after turning on - the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - - asbN: Clocks required by asynchronous bridges (ASB) present in - the power domain. These clock should be enabled during power - domain on/off operations. - power-domains: phandle pointing to the parent power domain, for more details see Documentation/devicetree/bindings/power/power_domain.txt +Deprecated Properties: +- clocks +- clock-names + Node of a device using power domains must have a power-domains property defined with a phandle to respective power domain. @@ -47,8 +37,6 @@ Example: mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "clk0"; #power-domain-cells = <0>; label = "MFC"; }; diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index caf45cf7aa8e..ab8582971bfc 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -13,14 +13,11 @@ #include #include #include -#include #include #include #include #include -#define MAX_CLK_PER_DOMAIN 4 - struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; @@ -33,10 +30,6 @@ struct exynos_pm_domain { void __iomem *base; bool is_off; struct generic_pm_domain pd; - struct clk *oscclk; - struct clk *clk[MAX_CLK_PER_DOMAIN]; - struct clk *pclk[MAX_CLK_PER_DOMAIN]; - struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; u32 local_pwr_cfg; }; @@ -46,29 +39,10 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) void __iomem *base; u32 timeout, pwr; char *op; - int i; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_prepare_enable(pd->asb_clk[i]); - } - - /* Set oscclk before powering off a domain*/ - if (!power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - pd->pclk[i] = clk_get_parent(pd->clk[i]); - if (clk_set_parent(pd->clk[i], pd->oscclk)) - pr_err("%s: error setting oscclk as parent to clock %d\n", - domain->name, i); - } - } - pwr = power_on ? pd->local_pwr_cfg : 0; writel_relaxed(pwr, base); @@ -86,26 +60,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) usleep_range(80, 100); } - /* Restore clocks after powering on a domain*/ - if (power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - - if (IS_ERR(pd->pclk[i])) - continue; /* Skip on first power up */ - if (clk_set_parent(pd->clk[i], pd->pclk[i])) - pr_err("%s: error setting parent to clock%d\n", - domain->name, i); - } - } - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_disable_unprepare(pd->asb_clk[i]); - } - return 0; } @@ -147,12 +101,6 @@ static __init const char *exynos_get_domain_name(struct device_node *node) return kstrdup_const(name, GFP_KERNEL); } -static const char *soc_force_no_clk[] = { - "samsung,exynos5250-clock", - "samsung,exynos5420-clock", - "samsung,exynos5800-clock", -}; - static __init int exynos4_pm_init_power_domain(void) { struct device_node *np; @@ -161,7 +109,7 @@ static __init int exynos4_pm_init_power_domain(void) for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) { const struct exynos_pm_domain_config *pm_domain_cfg; struct exynos_pm_domain *pd; - int on, i; + int on; pm_domain_cfg = match->data; @@ -189,42 +137,6 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_on = exynos_pd_power_on; pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg; - for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++) - if (of_find_compatible_node(NULL, NULL, - soc_force_no_clk[i])) - goto no_clk; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "asb%d", i); - pd->asb_clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->asb_clk[i])) - break; - } - - pd->oscclk = of_clk_get_by_name(np, "oscclk"); - if (IS_ERR(pd->oscclk)) - goto no_clk; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "clk%d", i); - pd->clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->clk[i])) - break; - /* - * Skip setting parent on first power up. - * The parent at this time may not be useful at all. - */ - pd->pclk[i] = ERR_PTR(-EINVAL); - } - - if (IS_ERR(pd->clk[0])) - clk_put(pd->oscclk); - -no_clk: on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; pm_genpd_init(&pd->pd, NULL, !on); From patchwork Wed Feb 21 10:15:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129013 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451297ljc; Wed, 21 Feb 2018 02:15:47 -0800 (PST) X-Google-Smtp-Source: AH8x225i432Bx8ObUsXwnZz/BbxhlDf/9Ci36f419uRN7NfB1zj9NU3glM6PEuWHcisVLOD0piF1 X-Received: by 10.98.86.15 with SMTP id k15mr2817601pfb.187.1519208147380; Wed, 21 Feb 2018 02:15:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519208147; cv=none; d=google.com; s=arc-20160816; b=WWb8OvBQKsN6vZAVzTIr/l2pNhMoP5TmydrMW8ZBCnuoVUAR5VLhgp0KTd2/NY/OGR HwkGLDWQumsav+VJm8jJPOiwej+JFUNU9P26ZqEsY5BE3mHVt6YbJl581BWzGiCaRmeG LdsRJ1oSrRboIE5uYo8yRSoXZOPBjOFB0bc5Je0B7cpbjqscBVN8ldTMi0hpn/MuyL45 hEYLuE8N2ATHsKrwN7jrBT6pMK9VZokXSfbMIsqPNbUcu6GNVkLqacUmvwowPCgK5svI sDuIWoI11nTJRE1TYUMeMNvdwphu3ExS7LA6F8thchxGrpXD0dt+KTX4nta5I64ywVxj igYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=kVk7ucLLwszMb1Bch+QecGIWcpCAn9S7UeKPOe0MklQ=; b=MVLcBZPOeH1mHfMPffMS7/yo3bQJ/3xdmuiyG419KZPDpqsIkbvFF49U+O8TbGcdjz HCNy8Mag2Am3FZECk3WpJdV84ESyuaXnqwCBBAs+RbsaMPKdRGdFWg18C4p7klIE4tcW LaWmHT5+sKWmh8GZPfLXf9RFRe9vk8uiJ7xq1XwrCN1yfW1RZZmM37caDQVtNPHrgcIf ALhVkfZLyRENCQ4TGD3GdNqdIBIAjlEpmI6ATpj1HkS3esdqltimemjXWGIPWQS4yzGP ZlSR/aGVzZykuUzY5ikCDRZmUki9t7v3VlRWH6FUt4CtROGLuoyKxwnVEggseQRjZsML bpZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=GNeLJDB9; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Remove all clock properties from existing Exynos power domain nodes, as they are no longer used. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5250.dtsi | 4 ---- arch/arm/boot/dts/exynos5420.dtsi | 14 -------------- 2 files changed, 18 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index bb4180ef7885..54b0ecd2c4fd 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -132,10 +132,6 @@ reg = <0x100440A0 0x20>; #power-domain-cells = <0>; label = "DISP1"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_ACLK200_DISP1_SUB>, - <&clock CLK_MOUT_ACLK300_DISP1_SUB>; - clock-names = "oscclk", "clk0", "clk1"; }; pd_mau: power-domain@100440c0 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2f3cb2a97f71..9672d0e51f69 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -276,10 +276,6 @@ reg = <0x10044000 0x20>; #power-domain-cells = <0>; label = "GSC"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 { @@ -292,10 +288,6 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; - clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; label = "MFC"; }; @@ -312,12 +304,6 @@ reg = <0x100440C0 0x20>; #power-domain-cells = <0>; label = "DISP"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; mau_pd: power-domain@100440e0 {