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[23.128.96.18]) by mx.google.com with ESMTP id ay21si3437544edb.575.2021.01.08.03.34.47; Fri, 08 Jan 2021 03:34:47 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ywk/gPaj"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725965AbhAHLda (ORCPT + 6 others); Fri, 8 Jan 2021 06:33:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725828AbhAHLda (ORCPT ); Fri, 8 Jan 2021 06:33:30 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B490FC0612F9 for ; Fri, 8 Jan 2021 03:32:49 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id p18so7479368pgm.11 for ; Fri, 08 Jan 2021 03:32:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CxihuApHeST5FtR1ic0MIOxlrYHGlIn3irwCDLvd5sM=; b=Ywk/gPajX5//7GQMshPjTj9MnHRxcL6KC4lwq7LbB2IP01fdFz7eo80k75h3ei71+s dAkWsmc4L5j3huT/PsV7RHFzZKPjvYb7LNrXHsjC488Cj2v8PIh2zkodRZsCbPYYxL2T nOmK50mMGEJc1MFKxTCdeboNZSWUmOxgQjzLmy4pwOwxlRky/a45VFJB5Y5eInlZwvNG ymEn5H52fFqqORtirxz7wT1cdg6AneznFMAAXXzYcfhpfqvvrS/xbXKgnzwzExtj/Kff oqOyygJIK8VkBuQy5Qu/cu87dTXNFcNEcHx6qSd+MM5Z40dedsrAfWREb8hs0HOIQjRP vYIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CxihuApHeST5FtR1ic0MIOxlrYHGlIn3irwCDLvd5sM=; b=l87pjLk78098Z4/rfW+CB5ReevNm6pBeUfXi/TFoWB5AH4fTiCZ0W+tTt0DNJd6Sw0 9Dvs9ugY/NcrDWQgEKz5RsTLVGoT/QU47iJddwUbMgfATmctLGf3TuJPnkW4ODRoqEC7 UnY7bH5akxMW6QytmQFpEiKIQ75huVY23jDf4X/pDG36PiYXS9+5x2UDLtEkYpB8wg1y ArDE0XPy2fgpf/tzzRgkcR6NkGr1nB3wP9cuVeeRGRxkxbKWO2usZMebZt3d1ij9rR/i 6La7DvDgzliUi37KWMUw/jhhVcW8EoSGYJQTIztzxHC176DbOJP5hiYrSdxeiNDgwF0W /l/g== X-Gm-Message-State: AOAM530hGmn/01DHYZ1me9U3/NQjdO5BZ0MffGlTCvgLxy21s4WZuiLO ATxfQKNFQTBxnNiy2hqEl65i X-Received: by 2002:a62:d142:0:b029:19e:62a0:ca16 with SMTP id t2-20020a62d1420000b029019e62a0ca16mr3243147pfl.46.1610105569213; Fri, 08 Jan 2021 03:32:49 -0800 (PST) Received: from localhost.localdomain ([103.77.37.188]) by smtp.gmail.com with ESMTPSA id i25sm9261573pgb.33.2021.01.08.03.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 03:32:48 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 1/5] dt-bindings: mailbox: Add binding for SDX55 APCS Date: Fri, 8 Jan 2021 17:02:29 +0530 Message-Id: <20210108113233.75418-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> References: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree YAML binding for SDX55 APCS GCC block. The APCS block acts as the mailbox controller and also provides a clock output and takes 3 clock sources (pll, aux, ref) as input. Signed-off-by: Manivannan Sadhasivam --- .../mailbox/qcom,apcs-kpss-global.yaml | 59 ++++++++++++++++--- 1 file changed, 50 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index ffd09b664ff5..3c75ea0b6040 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -27,26 +27,24 @@ properties: - qcom,sdm660-apcs-hmss-global - qcom,sdm845-apss-shared - qcom,sm8150-apss-shared + - qcom,sdx55-apcs-gcc reg: maxItems: 1 - clocks: - description: phandles to the parent clocks of the clock driver - items: - - description: primary pll parent of the clock driver - - description: auxiliary parent - '#mbox-cells': const: 1 '#clock-cells': const: 0 + clocks: + minItems: 2 + maxItems: 3 + clock-names: - items: - - const: pll - - const: aux + minItems: 2 + maxItems: 3 required: - compatible @@ -55,6 +53,49 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + - qcom,msm8916-apcs-kpss-global + - qcom,msm8994-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcs404-apcs-apps-global + - qcom,sc7180-apss-shared + - qcom,sdm660-apcs-hmss-global + - qcom,sdm845-apss-shared + - qcom,sm8150-apss-shared + then: + properties: + clocks: + items: + - description: Primary PLL parent of the clock driver + - description: Auxiliary parent + clock-names: + items: + - const: pll + - const: aux + - if: + properties: + compatible: + enum: + - qcom,sdx55-apcs-gcc + then: + properties: + clocks: + items: + - description: Primary PLL parent of the clock driver + - description: Auxiliary parent + - description: Reference clock + clock-names: + items: + - const: pll + - const: aux + - const: ref examples: # Example apcs with msm8996 From patchwork Fri Jan 8 11:32:30 2021 Content-Type: text/plain; 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Fri, 08 Jan 2021 03:32:53 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/5] mailbox: qcom: Add support for SDX55 APCS IPC Date: Fri, 8 Jan 2021 17:02:30 +0530 Message-Id: <20210108113233.75418-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> References: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 077e5c6a9ef7..1c205832a1cc 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -61,11 +61,15 @@ static const struct qcom_apcs_ipc_data apps_shared_apcs_data = { .offset = 12, .clk_name = NULL }; +static const struct qcom_apcs_ipc_data sdx55_apcs_data = { + .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk" +}; + static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0xFFC, + .max_register = 0x1008, .fast_io = true, }; @@ -162,6 +166,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data }, { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, + { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); From patchwork Fri Jan 8 11:32:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 358931 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp459446jai; Fri, 8 Jan 2021 03:34:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJwR1tGm82o9KyE4+DoqUCnwxhyNNfb7PqfuxNhVgo63aPJAkmnS2f8fQic2dZYSVLVCEWt4 X-Received: by 2002:a17:906:d19b:: with SMTP id c27mr2436248ejz.234.1610105691185; Fri, 08 Jan 2021 03:34:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610105691; cv=none; d=google.com; s=arc-20160816; b=QJ4jp3MMrSsgypr3ncIVuaPCVb3i6yTtthSpJ8R7Z3mnb3bCp+vELqICHZOprMVAmB gTbX4dVb76jYbj30FjejZLUVSz3qAzTbQbHyW4cSXmq8xOozJYy17eRTnUWiuNeec2Hg Rxo4cDXoJ0pmFydzTG9ZGTXsQvTEDcGLgi0s1dOOsRdCWYisFqxR0WjGI0ErGNGInx2c z3fDi3pwql5DEJWrnXHQlXx445rH4ppCYYe04wEkPZqBpxQ+eLWlu0/ZmWMmt45MwDYt /VH5xq80toEz7418/2ZikgDm8vuZtCGtTGjk5CS8/ht00ofaIAeiCctXqI6ZQRxw+2GG vDrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SajeAnD/bM3T+Qtfi1lyQyoeSgIHCjSTfGa4G04tdEU=; b=ed/nDbA5ghSgGF2XgTqWniSDYKtdIzAnoWRlS0Zonygy6r1rERxMAaJaozgFr7rfm1 74SOIuaj1FuP90Ttz6OtCJ8pEDqrwKKDtHqZkmBQicrPwJUxxSxUo7YPaRk7fGqjJ5Rn e5z/g23KLAy+lfDeZFAaU0J7NOLxT6MJE/2gqL6MluZlbKhDeTICkbJVX4r00imxsOMm MgKvxvNiBvgp0m5jiUBkqEP9M06mVfpWcEHtRnXJsOEvZzlRyfS1+xNviqxcUJpGBTm5 6FDrDpemcIx/Kwcx/V110a2OPwbL2nkaPm9sTAjM00Ee12qaFVC42pS6g/2mNIC3GO0p I3/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fJy7+QGB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/clock/qcom,a7pll.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml -- 2.25.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml new file mode 100644 index 000000000000..8666e995725f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm A7 PLL Binding + +maintainers: + - Manivannan Sadhasivam + +description: + The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high + frequency clock to the CPU. + +properties: + compatible: + enum: + - qcom,sdx55-a7pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + clocks: + items: + - description: board XO clock + + clock-names: + items: + - const: bi_tcxo + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; From patchwork Fri Jan 8 11:32:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 358932 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp459470jai; Fri, 8 Jan 2021 03:34:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJz7lhwP8832PYkwLwvu+PQ1uYtxlPqMnh6ET0zaNXg7qRNSRfN5XADbV/INdmTUXBC1gPLC X-Received: by 2002:a17:906:178d:: with SMTP id t13mr2280035eje.455.1610105692991; Fri, 08 Jan 2021 03:34:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610105692; cv=none; d=google.com; s=arc-20160816; b=XckFaMjLQdi4Q/PYE2dKeI21lSTr5Lqk6Xtw1PjfrwjJHn/DqoEbEPF/ZUX31hi4QL zH52+oLFiSfc8Dqb4PH3Td6XKn2k6g5f9Yu4KkU5v4NYCA2Zc4XFLpMXhK1oYgRnGOhT KVPLDrKznBIWwZADjUVkoQEW34QDX7RzlrLJ3ZL97m+3P7kKeKcEHd5rfOe1oOX2ibL1 EOuDy37sZnarxquhM3JZepNPBtPMFCQS3WupzEHySAgtZ4yQqdn6xjr9ahYVFCvNqXLu +uDuo6V0Wf2oa4vbXf1VEOuJzY/LOMKpGEggEmEvavHUwCYTCAcxchF3Gg3YcjhnI1oe gqFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9oCBXEeItNyLdmXrVsfC7b3QROxgUzyHxaMFoVN3rtU=; b=dCnALJJNufPOMdlCx5tR8xi9BsMlpVKCbwiEeHB0quVGpTDXECeLwm9s06D6OlYwIF WQJrmwYGqiiYU0XNKw3ukg+zcqZfhmm+cpk5bXrgZcCk4YzvzZHQFqE3LP8Tg/w2j7TQ VR652SV6369XEAVbhRrTgcolgj7ln7qRm4QsP7cD2NypdmRXApytJVENuvNhz21BNZQm Prnm3Bz7j6d8Mp67CcdQzl5cPDKJPTCsaFjub53qhuF0oZz0fAVryw0OTbEiCAR+1Rlu f3rSNV4x9PsnBAf3h9sL9Hpq4h4GHP6JQQ/vlNt4H3QGmkMNG9znkaeUSTBkdRZfiKmV xKxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ua2XMhpo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ay21si3437544edb.575.2021.01.08.03.34.52; Fri, 08 Jan 2021 03:34:52 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ua2XMhpo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727045AbhAHLeX (ORCPT + 6 others); Fri, 8 Jan 2021 06:34:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726607AbhAHLeW (ORCPT ); Fri, 8 Jan 2021 06:34:22 -0500 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BE2FC0612A5 for ; Fri, 8 Jan 2021 03:33:05 -0800 (PST) Received: by mail-pg1-x534.google.com with SMTP id z21so7500156pgj.4 for ; Fri, 08 Jan 2021 03:33:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9oCBXEeItNyLdmXrVsfC7b3QROxgUzyHxaMFoVN3rtU=; b=Ua2XMhposk+JG9VoblsJbkOh1sUkeL9uznRFpJ4/+COC813mK6EaW8ZLPQ6mB1Tvb/ hr0cBmNLrAPLd+g3Mt+VxWKST4zrbh+A+5YBDfa3UFQeqA/SVjSmEx5BcELP8HkgftJK 82xPA722BwKwn/FprMSr5KyUh+ZLtqpgd5dKMl8bxXX4gFvGrwp82G789X6f+y3w3z2z nLOsKEEnLWlHGMrnEgUJvJhW+VIgJ+dCQwaIvf1Z6VOTSopD4KCxIccOkCQ4E6hxDI7f fOdzgUqxvC0JjsmdamsNuBH30SNlfluAyfMIcxsyAAKfFjMvehMcWNg1e+MvLTdXyC63 fYsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9oCBXEeItNyLdmXrVsfC7b3QROxgUzyHxaMFoVN3rtU=; b=JsNv9WCgXYX9Q1irczVcfUtJ2W7F62PbfL3xj/qQp86FX6jZGh7Vsq2BoqotM64dIm jAMXK8E0EfwzBpOuAZaY48B9GIQIuQWnrvVIONc8AigwonUQ2k/2z5Zq+FHgWI2vUWoO xSO78I87bP/UMNmUroveCl/3g6Z3AbD8YcqTaJC7TH4tFRj/ELwTYipn2QJtS9XH9b8B GESAReEQce8Vdz8OoI07M5YOB1Vs/iqYqpkMvNewqYVGd0atE8Y6Guii4/29oNuDNrUZ C/qPNbc/r2r4LaG8Jh0Gs3I5zkekIe2S6d2jZ7ilMokECHWBA9Hy1GtL0yO7Ub1u2drZ M79A== X-Gm-Message-State: AOAM532wO365b2dH5NRRlhZ/cWpAHThLwzw+XT/svOFI6QGR17OgsCo9 etRrwa+duIlqdWVjeXlMSUDD X-Received: by 2002:aa7:9afb:0:b029:19e:45d8:b102 with SMTP id y27-20020aa79afb0000b029019e45d8b102mr3237525pfp.48.1610105584922; Fri, 08 Jan 2021 03:33:04 -0800 (PST) Received: from localhost.localdomain ([103.77.37.188]) by smtp.gmail.com with ESMTPSA id i25sm9261573pgb.33.2021.01.08.03.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 03:33:04 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 4/5] clk: qcom: Add A7 PLL support Date: Fri, 8 Jan 2021 17:02:32 +0530 Message-Id: <20210108113233.75418-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> References: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for PLL found in Qualcomm SDX55 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 8 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a7-pll.c | 100 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 drivers/clk/qcom/a7-pll.c -- 2.25.1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d32bb12cd8d0..d6f4aee4427a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -28,6 +28,14 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_A7PLL + tristate "SDX55 A7 PLL" + help + Support for the A7 PLL on SDX55 devices. It provides the CPU with + frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on SDX55 + devices. + config QCOM_CLK_APCS_MSM8916 tristate "MSM8916 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9e5e0e3cb7b4..e7e0ac382176 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c new file mode 100644 index 000000000000..e171d3caf2cf --- /dev/null +++ b/drivers/clk/qcom/a7-pll.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm A7 PLL driver + * + * Copyright (c) 2020, Linaro Limited + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include + +#include "clk-alpha-pll.h" + +#define LUCID_PLL_OFF_L_VAL 0x04 + +static const struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll a7pll = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "a7pll", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct alpha_pll_config a7pll_config = { + .l = 0x39, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x2261, + .config_ctl_hi1_val = 0x029A699C, + .user_ctl_val = 0x1, + .user_ctl_hi_val = 0x805, +}; + +static const struct regmap_config a7pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true, +}; + +static int qcom_a7pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + void __iomem *base; + u32 l_val; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Configure PLL only if the l_val is zero */ + regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val); + if (!l_val) + clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config); + + ret = devm_clk_register_regmap(dev, &a7pll.clkr); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &a7pll.clkr.hw); +} + +static const struct of_device_id qcom_a7pll_match_table[] = { + { .compatible = "qcom,sdx55-a7pll" }, + { } +}; + +static struct platform_driver qcom_a7pll_driver = { + .probe = qcom_a7pll_probe, + .driver = { + .name = "qcom-a7pll", + .of_match_table = qcom_a7pll_match_table, + }, +}; +module_platform_driver(qcom_a7pll_driver); + +MODULE_DESCRIPTION("Qualcomm A7 PLL Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Jan 8 11:32:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 358933 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp459490jai; 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It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-sdx55.c | 149 ++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clk/qcom/apcs-sdx55.c -- 2.25.1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d6f4aee4427a..2c67fdfae913 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -45,6 +45,15 @@ config QCOM_CLK_APCS_MSM8916 Say Y if you want to support CPU frequency scaling on devices such as msm8916. +config QCOM_CLK_APCS_SDX55 + tristate "SDX55 APCS Clock Controller" + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for the APCS Clock Controller on SDX55 platform. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as SDX55. + config QCOM_CLK_APCC_MSM8996 tristate "MSM8996 CPU Clock Controller" select QCOM_KRYO_L2_ACCESSORS diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e7e0ac382176..a9271f40916c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o +obj-$(CONFIG_QCOM_CLK_APCS_SDX55) += apcs-sdx55.o obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o diff --git a/drivers/clk/qcom/apcs-sdx55.c b/drivers/clk/qcom/apcs-sdx55.c new file mode 100644 index 000000000000..14413c957d83 --- /dev/null +++ b/drivers/clk/qcom/apcs-sdx55.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm SDX55 APCS clock controller driver + * + * Copyright (c) 2020, Linaro Limited + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" +#include "common.h" + +static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 }; + +static const struct clk_parent_data pdata[] = { + { .fw_name = "ref", .name = "bi_tcxo", }, + { .fw_name = "aux", .name = "gpll0", }, + { .fw_name = "pll", .name = "a7pll", }, +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A7 PLL is reconfigured. + */ +static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = mux_div_set_src_div(md, 1, 2); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + struct device *cpu_dev; + struct clk_regmap_mux_div *a7cc; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret = -ENODEV; + + regmap = dev_get_regmap(parent, NULL); + if (!regmap) { + dev_err(dev, "Failed to get parent regmap: %d\n", ret); + return ret; + } + + a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL); + if (!a7cc) + return -ENOMEM; + + init.name = "a7mux"; + init.parent_data = pdata; + init.num_parents = ARRAY_SIZE(pdata); + init.ops = &clk_regmap_mux_div_ops; + + a7cc->clkr.hw.init = &init; + a7cc->clkr.regmap = regmap; + a7cc->reg_offset = 0x8; + a7cc->hid_width = 5; + a7cc->hid_shift = 0; + a7cc->src_width = 3; + a7cc->src_shift = 8; + a7cc->parent_map = apcs_mux_clk_parent_map; + + a7cc->pclk = devm_clk_get(parent, "pll"); + if (IS_ERR(a7cc->pclk)) { + ret = PTR_ERR(a7cc->pclk); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get PLL clk: %d\n", ret); + return ret; + } + + a7cc->clk_nb.notifier_call = a7cc_notifier_cb; + ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb); + if (ret) { + dev_err(dev, "Failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a7cc->clkr); + if (ret) { + dev_err(dev, "Failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &a7cc->clkr.hw); + if (ret) { + dev_err(dev, "Failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a7cc); + + /* + * Attach the power domain to cpudev. There seems to be no better place + * to do this, so do it here. + */ + cpu_dev = get_cpu_device(0); + dev_pm_domain_attach(cpu_dev, true); + + return 0; + +err: + clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb); + return ret; +} + +static int qcom_apcs_sdx55_clk_remove(struct platform_device *pdev) +{ + struct device *cpu_dev = get_cpu_device(0); + struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev); + + clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb); + dev_pm_domain_detach(cpu_dev, true); + + return 0; +} + +static struct platform_driver qcom_apcs_sdx55_clk_driver = { + .probe = qcom_apcs_sdx55_clk_probe, + .remove = qcom_apcs_sdx55_clk_remove, + .driver = { + .name = "qcom-sdx55-acps-clk", + }, +}; +module_platform_driver(qcom_apcs_sdx55_clk_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm SDX55 APCS clock driver");