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[23.128.96.18]) by mx.google.com with ESMTP id t20si33458073edw.31.2021.01.05.07.16.44; Tue, 05 Jan 2021 07:16:44 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dzA2i6Ge; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725917AbhAEPQO (ORCPT + 6 others); Tue, 5 Jan 2021 10:16:14 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40016 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725868AbhAEPQK (ORCPT ); Tue, 5 Jan 2021 10:16:10 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 105FEW8i012808; Tue, 5 Jan 2021 09:14:32 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1609859672; bh=jEkh70lgQQiul1cZEJwraNm1tV2d5H5lh02w9ERRWbs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dzA2i6GeZ16mU/09MxoUx+/L5yqggf+fmCQLAv3gFdCVcn5gOnb5hGzbmNciEAy4S PssAT4o1f121I9DS4U4Uk24tFh0gWPg1LuMKj9uba/XxRd42UVsgTNMZb/T+uIQBUs 56F+hijirZQrfJXLi8ZwUt7w1NHO784ljf2glsM0= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 105FEWal035998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 5 Jan 2021 09:14:32 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 5 Jan 2021 09:14:31 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 5 Jan 2021 09:14:31 -0600 Received: from a0393678-ssd.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 105FEPOD005961; Tue, 5 Jan 2021 09:14:29 -0600 From: Kishon Vijay Abraham I To: Nishanth Menon , Rob Herring , Kishon Vijay Abraham I CC: , , Subject: [PATCH v4 1/6] arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions Date: Tue, 5 Jan 2021 20:44:16 +0530 Message-ID: <20210105151421.23237-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210105151421.23237-1-kishon@ti.com> References: <20210105151421.23237-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence IP in J721E supports a maximum of 32 outbound regions. However commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") incorrectly added this as 16 outbound regions. Now that "cdns,max-outbound-regions" is an optional property with default value as 32, remove "cdns,max-outbound-regions" from endpoint DT node. (Since this doesn't impact existing functionality, it need not be backported to older kernels). Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b32df591c766..1c11da612c67 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -651,7 +651,6 @@ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -700,7 +699,6 @@ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -749,7 +747,6 @@ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 241 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -798,7 +795,6 @@ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 242 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; From patchwork Tue Jan 5 15:14:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356865 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp77112jai; Tue, 5 Jan 2021 07:16:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSDmTd5Cbu5sXMShzUAv20wyb3zggVt+z0IcLoX0+Cnu1ocbDGtCXsCgUbRq0I04PS9dXT X-Received: by 2002:a50:d2c8:: with SMTP id q8mr165394edg.375.1609859799484; Tue, 05 Jan 2021 07:16:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609859799; cv=none; d=google.com; s=arc-20160816; b=u38pv34rN+r4rhcLb/gymXgql2+WqMcARvfTgTc81pvU+hNxmK/v/jzVigrprHc7lZ z70CGJGWW93q2MzKMSreRIYQMZMaAPv5RnRbW7vH0eAKOjabyUBu/V7q+ihHageYviML sfUIT9j2n/VrbS+5dvadfyslaY1LWbUB1V+GVuN2aDCkOq8ZM9/Q/mkUJySluuIaH82j hWdT7FCYp0+PmeuBwTd/dxY/DVWw4ySsDh2UqJSx3Y+ffB4+2FLzNBWO9GzZwbJ08tZx 4QOeBQr3qad6y57tXRIsUgia6D3sdNngvOn2SjaM6PWmdBnpra6Khkk3GsH5nJXNN4aZ au3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uFq9z3ejFp9l0tjXk+DozG6GW6K1mSjTFFPB1zKf5Zc=; b=LlufCk0qQdiuPL7NFQTpeUmAM+2+1R3GHLywUI4HfpkBn6KvOccLgj/Udax5UY9Zwu 7dsb66KhUyJxFF4aGv3JrpCXXSCm+q0GWfAsasgz77/HXmoDXfU/IBwhM09eMfky2lNf 5iN3G/QHudnBmBdSVWZ/9tXWcF2ZLI1COs1CEE3ORzr2ZxBCEut7UIrLJXlDg+mQ9XsV unQBq7LxtMQBwxXA3NWNZDX2s9DrxsJX19Wjg/udGfENsOzzQRGHGZExO1rPASltmucd fKr1wVLiy/wYjGA8At/DKmUdc0REcozZuz7bzRH90qKMPH9G/Ub/LwHkohyzGAv0jE7j +GWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wyFFiJyI; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This change is as discussed in [1]. [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++------------------- 1 file changed, 8 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 1c11da612c67..2d526ea44a85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,38 +28,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_ctrl: syscon@4070 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4070 0x4070 0x4>; - }; - - pcie1_ctrl: syscon@4074 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4074 0x4074 0x4>; - }; - - pcie2_ctrl: syscon@4078 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4078 0x4078 0x4>; - }; - - pcie3_ctrl: syscon@407c { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0000407c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x407c 0x407c 0x4>; - }; - serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; @@ -618,7 +586,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -645,7 +613,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -666,7 +634,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -693,7 +661,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -714,7 +682,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -741,7 +709,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -762,7 +730,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; @@ -789,7 +757,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; From patchwork Tue Jan 5 15:14:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356870 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp77179jai; Tue, 5 Jan 2021 07:16:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJwtLmYuuPcRA6KUQdu6Gi3i2DkhmAjyYOuUPhcFccBAx0defBA1iZ9SJ1dzhPPFS108LLoO X-Received: by 2002:a17:906:1488:: with SMTP id x8mr58373983ejc.124.1609859805907; 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index b0094212aa82..fbe4cd1e6e09 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -5,6 +5,13 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -531,6 +538,62 @@ dma-coherent; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 292 85>; + assigned-clock-parents = <&k3_clks 292 89>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&wiz0_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Tue Jan 5 15:14:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356871 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp77187jai; Tue, 5 Jan 2021 07:16:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJxEsNTZ39xwdLdcdx9rr8ohFc68oVzBvTfBTnYxMdln2b4/CVUpHC0lfXZzGFtto3PCMxNv X-Received: by 2002:a50:8741:: with SMTP id 1mr178743edv.349.1609859806793; Tue, 05 Jan 2021 07:16:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609859806; cv=none; d=google.com; s=arc-20160816; b=y8eEkui/6sBsy/QuikAvlcZH9pEGkzF+zkJOHnBfgF7CdXvPwTsxmvBeJVmvgAKCon FAf8farZYVLm+vvsK5jcCEoeQBxpVlKx5mVUbirFP/3BCc1F484iVzEOlp1Fs1621Ips U7WGCQQzze3ATII8suQXOOe8XdvCgfHo4Y3/j169i2VViDDodRw+iofqdyBDWXrZHkpk uOB8zra3/M7PBbac66t25xe7pJm4jw6BA3wbaDLOvIWIOFnp3NURJ+BetT8RYAygP1bR jxsd2RPbw5gY4R3LZt93VjBhh0vf1w+H9jcaSGaybOhJyHt+kcH2ADBg96zi0JQD7ITP yWVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=a5c+PysASIVxRTBhsge2AmvKiHMXJJVRD93ZeuiTO60=; b=LQ7mb2W+gcMEYqOxVpO5D3BwgYli4afzCgqIOQjcr4MObtNQFGgFsXGdsKSv8i/ZuG XCMfxsJS6UxSOOk3hJRG2BLhyH8FIxyH1m8HMHuRDbBsW422Ur0CrlIqmzEGGauHjY1D Gk/28+rFiJDS85vDfP9W7zXQJu1jzGVzQNUb12tIEdi419ZQ5j0sP0FujwHpG8JG2L6L fHfBLqzkoGGYoacS4i/UGH9AX+dlokvcn0j5nB1oDbL0zN0Pi3Eb6N4pHW5I+9MLpBoj 4ml1mSqwu9wwaLAQA4QUHKMX1MYJw9vryUU8XImNhf6IYQw9bpIKzw7BOKfM/5DejQK8 SDxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BYoCW8cG; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index fbe4cd1e6e09..4e39f0325c03 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -594,6 +594,54 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Tue Jan 5 15:14:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356866 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp77126jai; Tue, 5 Jan 2021 07:16:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJwle34KfX8rzspkkErGUI1cgQGXL86Srdx3opoz3XLOgA1C2Cg3LPs7zkc5SeoRZAXgDCSG X-Received: by 2002:a50:8741:: with SMTP id 1mr178216edv.349.1609859800854; Tue, 05 Jan 2021 07:16:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609859800; cv=none; d=google.com; s=arc-20160816; b=RNwnZVbMvXD9Vj+6w4W+uNoA8LHgzA4pz7DsOkh11JZLuIJ4HDh47rWX99g0CH3G92 ptuBHAokLCkHl0zzN3ikrJwpvF9ys/TsD0Hyab4BX3o+zVZ5DA/WZ0/L8dPvgtZXEbuE xwlUlK7jtZdJ4SbUSbrttdJ+dtXxfILHH5TNP1fplfdpk8zLajuv/PKwDJpSr28KI3+5 y07fQfVvSQYMWOBWG7tYbpyXgqk2sVSGLaVhKrm2FzD/fBVWTISxYe3DQJdVdy+6gG3k 5n4JUYSBwC1DTlwPArbzsube6UGIFHdy6oiS62W+LRv2AD4y2z14okFeisnusyoJChsg RNFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TCT4o2ep6cw3Hu4jevsOOwo8iY51in45dTp+iGuuPKs=; b=V5cxaYzWfiANHA4x/QaDqLhArmqT6PWWH6/WqDyCphaNaXWcHrrTd/X7mP07z0zuvJ Clj5hOz7Vp6GfDPXCNQJNUy3PwOpS/X+U7xhLJHqPJD0PMc3CLjlYKPUelOqtKR4V3g7 LNaVu/Ksx8jxd5GISgR5c73gOg4ve7U1ID2D3srloNBbAzc27MGN5G+miIQ5mTIpG1YC /13ZIjR5euCJz9ylkAuwlfRfSExYniAsLffB0IsZ8p5MyFAv3SR0Y1cj28/FbclnW0n1 S1vasphpKv2NcUE13fJyQcRSb7rBLekGrQJcGVGBWKr+idJ8t3zdWyE4l+0KzmRfTCbL 9cDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=O7tPnp9N; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 331b388e1d1b..def98f563336 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j7200-som-p0.dtsi" #include #include +#include / { chosen { @@ -218,3 +219,25 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_qsgmii_link: phy@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; +}; From patchwork Tue Jan 5 15:14:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356869 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp77174jai; Tue, 5 Jan 2021 07:16:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJwafJelWsnLjL8iERZXD8FPklyLlK//cNhw2dNtPmqsAnxtEobtNfDZGCVdMVolwgXsXJnz X-Received: by 2002:a05:6402:1a52:: with SMTP id bf18mr200206edb.143.1609859805545; Tue, 05 Jan 2021 07:16:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609859805; cv=none; d=google.com; s=arc-20160816; b=GWZz+KzruoV/3dHu6ORr6LqjJQNKKe8fkXKt1VAznlDq6wcrymN+h58C7cEADZ9Khq yzWjK0z/5vbl09xHuwnJxc+eIowUm0JzJIk4kcfavdt70sXI0HJu0/hnsOWXcDVZC15T 1Bmc9vL5fUiDjMbl5TyhEJuzdclP6RMpkWyDdQ/QJH0pSKJX+Xty+NJAU9dta4cs/XeM eB24h1QuYKCXaeEj6dEK5mbS0kaivJvk8Jk56BlL9jzPDgEuDNEE8DBFiAXJmMcyFnvt 9wO9VWBG4/ObWRb+mN3XyQClN5lmsB59fq2Mfea0BxDlRY1I6Jq6AMQyqXDLk8Slghdz zphg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=v8DeDg+aSnj9XDWh6SjoEmvU220d2QLKrD8S48HIXT4=; b=hzPXUhOL9kWiG7L+6A5v2PQeIQ6y6xRJaVhnhBnddEURsWCGBD9u/JlnotrHjYIYxk g/vOxB4G3RD0Oqmn4fNQ7OxUVqXKLc29XWHI0l0XYYRgQPKItz1L9v/mQtZeQ75KKPP3 3ATkd19DY2Sams/zsAtd7olmQooWzSjAqnbfvnIo8bgt7kt3wXn+P/NF+tGGVlvVIYH/ gv5bQ2535p6h/MhCXN6RH1NgKHefqap/oe0lP7pPGZ/F5DQ/v83f7pX1vq9dHsYKJylX m9xr/ZS8pYVSyUAYPTDBTZLs19vzZ+ipY0AKahXuImefCUc08WadizFT6f9jmWHhKnuh 3N6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yj3aKO12; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index def98f563336..4a7182abccf5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include #include #include #include @@ -241,3 +242,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +};