From patchwork Thu Feb 15 15:02:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128468 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847070ljc; Thu, 15 Feb 2018 07:05:52 -0800 (PST) X-Google-Smtp-Source: AH8x225OBpkFmoZslKTdXb1MKOEo1wzGoGwTVkSEsKjRFF71QpLJaLNiQTombyVrG0FG3iKkLhbJ X-Received: by 10.36.39.201 with SMTP id g192mr3791307ita.144.1518707152518; Thu, 15 Feb 2018 07:05:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707152; cv=none; d=google.com; s=arc-20160816; b=CpYYb/fUd4E5BFVE8npvJazUo/NkHUpCBbAZvb3GQ80yGGQgJonidAbB+cl7blfJ3S GMm7h+riB/dozx8X1helWx7V+uyrszvoz5LpQhvki2QftWKpHdeFZBWNZwG/e6mWOXJN Pb4GRlDs4DJCTCZly5exinTekJB8olPcvEVp7s2r+GWyQl72owfkhfO7CB1WZBbkzoxt TYdN+ukWiCJKN6Apxql/K4cGF40lk5VZ4tzYbq3W5ARNSHUdPIdGHUH0zHfn7ARJ6Y0r 8X4YxsSEedUB2UcYqyJehB2V2Xyli1BCmleViAs2r5hxX60XXvqDjyTI8VEvwCXfSwEN rong== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=RNizgi6L5bjdxZc2gWBEGX822ct2C7j3W1tVSPy0Iz8=; b=wpWxgLR8ljnrA/O9MxhQPAvvKkrPKZhEj6rOfmmjQqaDqFjCQSoodULMKJSCzexe7T P11h7NcYK79jhO4pEqmit1IVjctE2IpuSTnHeRu+6WrNiWgnWyHFdhFT5cyKjg99EyjU woz+4hK+ZIhxqRFf2FDcWMZxPw0qh6HEh8lbHGERbHsrtbUt8F1Gt6yvfqaABD+xblZR preZ2p8NiVqxtULuWGjF8h0/3jGBm60xdEdQlwOEIVCkbmF9b5oVOjWk1YVHFG7+QC9G GIiJQU8lBWLw63P/Y2UssRowxeXbfwEtKxU7KI+wpT9PYt6rixDstbp9ysd3jRbKC4Ag ij5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c63si1776210itb.42.2018.02.15.07.05.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3w-0001wf-Na; Thu, 15 Feb 2018 15:03:04 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3v-0001wY-Js for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:03 +0000 X-Inumbo-ID: 3a400b14-1261-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 3a400b14-1261-11e8-ba59-bc764e045a96; Thu, 15 Feb 2018 16:02:23 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE77615AD; Thu, 15 Feb 2018 07:03:00 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 77FD33F41F; Thu, 15 Feb 2018 07:02:59 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:32 +0000 Message-Id: <20180215150248.28922-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Ian Jackson , andre.przywara@linaro.org, Julien Grall , volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com Subject: [Xen-devel] [PATCH v3 01/17] xen/arm: vpsci: Add support for PSCI 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, Xen provides virtual PSCI interface compliant with 0.1 and 0.2. Since them, the specification has been updated and the latest version is 1.1 (see ARM DEN 0022D). >From an implementation point of view, only PSCI_FEATURES is mandatory. The rest is optional and can be left unimplemented for now. At the same time, the compatible for PSCI node have been updated to expose "arm,psci-1.0". Signed-off-by: Julien Grall Acked-by: Wei Liu Reviewed-by: Volodymyr Babchuk Cc: Ian Jackson Cc: mirela.simonovic@aggios.com Acked-by: Stefano Stabellini --- We may want to provide a way for the toolstack to specify a PSCI version. This could be useful if a guest is expecting a given version. Changes in v3: - Add Wei's acked-by - Add Volodymyr's reviewed-by Changes in v2: - Return v1.1 on GET_VERSION call as claimed by this patch - Order by function ID the calls in FEATURES call --- tools/libxl/libxl_arm.c | 3 ++- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/vpsci.c | 39 ++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/psci.h | 1 + xen/include/asm-arm/vpsci.h | 2 +- 6 files changed, 44 insertions(+), 3 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..86f59c0d80 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -410,7 +410,8 @@ static int make_psci_node(libxl__gc *gc, void *fdt) res = fdt_begin_node(fdt, "psci"); if (res) return res; - res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); + res = fdt_property_compat(gc, fdt, 3, "arm,psci-1.0", + "arm,psci-0.2", "arm,psci"); if (res) return res; res = fdt_property_string(fdt, "method", "hvc"); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 155c952349..941688a2ce 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -637,6 +637,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent) { int res; const char compat[] = + "arm,psci-1.0""\0" "arm,psci-0.2""\0" "arm,psci"; diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 6ab8ab64d0..e82b62db1a 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -106,7 +106,11 @@ static int32_t do_psci_cpu_off(uint32_t power_state) static uint32_t do_psci_0_2_version(void) { - return PSCI_VERSION(0, 2); + /* + * PSCI is backward compatible from 0.2. So we can bump the version + * without any issue. + */ + return PSCI_VERSION(1, 1); } static register_t do_psci_0_2_cpu_suspend(uint32_t power_state, @@ -191,6 +195,29 @@ static void do_psci_0_2_system_reset(void) domain_shutdown(d,SHUTDOWN_reboot); } +static int32_t do_psci_1_0_features(uint32_t psci_func_id) +{ + /* /!\ Ordered by function ID and not name */ + switch ( psci_func_id ) + { + case PSCI_0_2_FN32_PSCI_VERSION: + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN32_CPU_OFF: + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN32_SYSTEM_OFF: + case PSCI_0_2_FN32_SYSTEM_RESET: + case PSCI_1_0_FN32_PSCI_FEATURES: + return 0; + default: + return PSCI_NOT_SUPPORTED; + } +} + #define PSCI_SET_RESULT(reg, val) set_user_reg(reg, 0, val) #define PSCI_ARG(reg, n) get_user_reg(reg, n) @@ -304,6 +331,16 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; } + + case PSCI_1_0_FN32_PSCI_FEATURES: + { + uint32_t psci_func_id = PSCI_ARG32(regs, 1); + + perfc_incr(vpsci_features); + PSCI_SET_RESULT(regs, do_psci_1_0_features(psci_func_id)); + return true; + } + default: return false; } diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index a7acb7d21c..87866264ca 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -31,6 +31,7 @@ PERFCOUNTER(vpsci_system_off, "vpsci: system_off") PERFCOUNTER(vpsci_system_reset, "vpsci: system_reset") PERFCOUNTER(vpsci_cpu_suspend, "vpsci: cpu_suspend") PERFCOUNTER(vpsci_cpu_affinity_info, "vpsci: cpu_affinity_info") +PERFCOUNTER(vpsci_features, "vpsci: features") PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index becc9f9ded..e2629eed01 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -40,6 +40,7 @@ void call_psci_system_reset(void); #define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) #define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) #define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) +#define PSCI_1_0_FN32_PSCI_FEATURES PSCI_0_2_FN32(10) #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) diff --git a/xen/include/asm-arm/vpsci.h b/xen/include/asm-arm/vpsci.h index 035a41e812..0cca5e6830 100644 --- a/xen/include/asm-arm/vpsci.h +++ b/xen/include/asm-arm/vpsci.h @@ -23,7 +23,7 @@ #include /* Number of function implemented by virtual PSCI (only 0.2 or later) */ -#define VPSCI_NR_FUNCS 11 +#define VPSCI_NR_FUNCS 12 /* Functions handle PSCI calls from the guests */ bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid); From patchwork Thu Feb 15 15:02:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128469 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847088ljc; Thu, 15 Feb 2018 07:05:53 -0800 (PST) X-Google-Smtp-Source: AH8x2244/tLWHXZiz7xhoi7W/OenQttY9JPgtY0JiNEtgY0M5Cf0F5Z1Yp1aznu1WO/non4PXLcV X-Received: by 10.36.110.4 with SMTP id w4mr3714014itc.103.1518707153115; Thu, 15 Feb 2018 07:05:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707153; cv=none; d=google.com; s=arc-20160816; b=wu9pFIsQN6Bp3GpEoBzc+THh/Qtjy8hEtnNCiRIOmCxP40Spb+02YLMm3M+Hs2Xp4N YCygVuDrPwRFVNA4nwAFjvVyTG+blKUtYxfeE/Ae073RjcIxWjnq3hiJ0FG8qe9KurVV RtlfgBESgYVIx3ArPpKmakbgZ9SEtaDLmzN+oxInT1KXMj23AaSZlOvoNLMw6fKx3kRm 1XzEKMMqR3ovvQTl49scs2ElcZViIw2zY8EAV0jxWztu/7ee1ipnTP6CpylbkgdBWTe0 FYsvZ3W6zFPxyU9oqRVAWwLEiaq+A6/0W+o0Gcm+7+AYoL45chwbsC1VSJCNpi2orEde q+Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=iZznK+ooip6MQHmd5Mi/4p2/f5p5IUbt4M4XQc1fgYE=; b=xWh9h+e5XwKGpyplQ4QmDcp6SjkIt73e+WOKVZzvTW0jmn+xxEJrbtTo5qcbVlRDb8 of7Yru2R8/zly6T2ZuL+29ghIdi9hQIqS9WZzPLni+XWE1H4qsrNCmIZvQjtqeEjK1WF mz/0mZb3g01Crd0Z/tNInUofcmvWAACJO9U4LPVPKMhnRmUvRkZsiZhVRJ7aFcOGcYjr thkmQFpctiR0JJaZ87CF3PR2rkdCLnE0McjrOXokc635UTRVsW2Z7cm4doHrJx9gFBXk pT+4XNSsGoBwj3Lfn6cMVcFO/koaxHxWXyjM50CkBlHACc7vbAO08WkLI3wRb0gOPSvO OAWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b99si8448149ioj.70.2018.02.15.07.05.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL41-0001xU-Bh; Thu, 15 Feb 2018 15:03:09 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL41-0001we-2Y for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:09 +0000 X-Inumbo-ID: 7fa34255-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 7fa34255-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:19 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 289E61435; Thu, 15 Feb 2018 07:03:02 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1928B3F41F; Thu, 15 Feb 2018 07:03:00 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:33 +0000 Message-Id: <20180215150248.28922-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 02/17] xen/arm: vsmc: Implement SMCCC 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. See "Firmware interfaces for mitigating CVE-2017-5715" ARM DEN 00070A. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v3: - Use ARM_SMCCC_NOT_SUPPORTED rather than hardcoded return Changes in v2: - Add a humand readable name for the specification --- xen/arch/arm/vpsci.c | 1 + xen/arch/arm/vsmc.c | 23 +++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 18 +++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index e82b62db1a..19ee7caeb4 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -212,6 +212,7 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) case PSCI_0_2_FN32_SYSTEM_OFF: case PSCI_0_2_FN32_SYSTEM_RESET: case PSCI_1_0_FN32_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FID: return 0; default: return PSCI_NOT_SUPPORTED; diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 3d3bd95fee..7ec492741b 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -81,6 +81,26 @@ static bool fill_function_call_count(struct cpu_user_regs *regs, uint32_t cnt) return true; } +/* SMCCC interface for ARM Architecture */ +static bool handle_arch(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + switch ( fid ) + { + case ARM_SMCCC_VERSION_FID: + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + return true; + + case ARM_SMCCC_ARCH_FEATURES_FID: + /* Nothing supported yet */ + set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + return true; + } + + return false; +} + /* SMCCC interface for hypervisor. Tell about itself. */ static bool handle_hypervisor(struct cpu_user_regs *regs) { @@ -188,6 +208,9 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { switch ( smccc_get_owner(funcid) ) { + case ARM_SMCCC_OWNER_ARCH: + handled = handle_arch(regs); + break; case ARM_SMCCC_OWNER_HYPERVISOR: handled = handle_hypervisor(regs); break; diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 62b3a8cdf5..629cc5150b 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + /* * This file provides common defines for ARM SMC Calling Convention as * specified in @@ -100,8 +103,21 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_##owner, \ 0xFF03) -/* Only one error code defined in SMCCC */ +#define ARM_SMCCC_VERSION_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x0) \ + +#define ARM_SMCCC_ARCH_FEATURES_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x1) + +/* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) +#define ARM_SMCCC_NOT_SUPPORTED (-1) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Thu Feb 15 15:02:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128465 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847024ljc; Thu, 15 Feb 2018 07:05:50 -0800 (PST) X-Google-Smtp-Source: AH8x227IBJz/kY7S2Z1W6dq/QyhpnpQX2aHuIZ+sQzrwROHNaukt4jPT5UcSPlhT/dOaYriasO66 X-Received: by 10.36.46.23 with SMTP id i23mr3775486ita.55.1518707150498; Thu, 15 Feb 2018 07:05:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707150; cv=none; d=google.com; s=arc-20160816; b=G85QnbvF0RpFmqk8HSblplr4zRv3FCjzDMx2P94VQ76/uFGRIgmDji9sXLI24Xtr0d 3USAMJLl/QtkZAq3qvcgUz8dEyWg/Ha6H0vaDOz5D40s0nj+2FaTxFjEIusPUezMcC2O gzQlfozNsyk1OI6vRNq5aQt8F7Ejo2fPsoyMOlA6wL9xRB2I+S3EomoJPDklIkN7J6Dy KgohddHuBshTzJ+kCB5f5T5L4tD74R7MdrSs4YXQn334eA9X3QLyERxNgzNOxTWkQrsK a1oTMusiya1/Fj1J5IfMTgeA7dGrKhxdDd9+Y/R7SHiTzFVEUdtp7S/SdbCqW0TJNfKZ XGQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=PrFouUW6WxyPfPQX1gemJxx+wmbais6t54EO7G2KgwE=; b=kVrQo7srMuDfGKzjBgpBYi5f7IQAB0kuVXkk2WAhUo2zZNYbRfjTcqtTlWOubebhmi Swa3KK0gdOMcV1OrOzcpa9TxgpFzCgVV+OB7/AUbWiDq4PLbx8twg2MV6atmnPlm3jdJ Pyv33tG8XRixWmJx3EageK+3Qq1Ij0ggsP1HJrbi5tHoyq2i2HIqJvbedfM1albeW1VD O/lNhQnJa466xiQkdL7IdNzUrIxn2t/6Hrq7rPpmpBT7Ux0vvllva93X/beVpuwBkloG tn8jPgrlgUHo6uVGFkXBz1xZdrrnGdPLv4hJH3s4SRnofLLWdw0S887IzFbKGQ8ug8qR C92Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c63si1776135itb.42.2018.02.15.07.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3x-0001ww-Ul; Thu, 15 Feb 2018 15:03:05 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3w-0001wi-Ru for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:04 +0000 X-Inumbo-ID: 3bcf66c7-1261-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 3bcf66c7-1261-11e8-ba59-bc764e045a96; Thu, 15 Feb 2018 16:02:26 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77CAD15BF; Thu, 15 Feb 2018 07:03:03 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67D913F41F; Thu, 15 Feb 2018 07:03:02 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:34 +0000 Message-Id: <20180215150248.28922-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 03/17] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v3: - Fix minor conflict during rebase Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7ec492741b..40a80d5760 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = ARM_SMCCC_NOT_SUPPORTED; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 629cc5150b..2951caa49d 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) From patchwork Thu Feb 15 15:02:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128460 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846924ljc; Thu, 15 Feb 2018 07:05:45 -0800 (PST) X-Google-Smtp-Source: AH8x226AnG4F6FpJ8LoFjDywfUoWQAPfNas61n+ntanU8eWmfjWXLWT20ofhhy8gZfly/nL7gSlS X-Received: by 10.202.90.137 with SMTP id o131mr1899591oib.210.1518707145730; Thu, 15 Feb 2018 07:05:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707145; cv=none; d=google.com; s=arc-20160816; b=bZzvFNK+kGmlqiHfxahTheB5MXKdcFR47jZWMhuV3POBnJiB3H71tjftj9u7/1H6Dy 002WWIPxy9jwfOnQbxXMivfZkFNm+vymHwW7PD0MTNd4g1tMJHnC5DgPrhj7zYcU4wIv Szv2wjPEGnKjW+9UiPG/VcBjYrB7zucW7lf3vNyMDqFeACq0HPCdCdz9pogteA7VsfUL i78UHFT33Ynj+LUnsBl9srys3Do5GFUmJcHuvphvYF9fUUXBZoURKL1WwTyk5283tH88 SFgK78O36NIQPRzL3+qrSaPIUOh4ohRlPCiCGeL3oGRiddDJZ3jhVOQSBUOxNQmVw0o7 fQvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ima8HELVD6oCpECxpXHQLSqnkWAMPbKAVNbj6ItWmGw=; b=hA3yeFAy2oVWPW7kdL7PNKgKgfctP/sAO3p9WH92e3LCva3eju+cF4FC5xmAi7nS5U yQ+Ep1SDdakZ5Rw+eCCkV1Y7QRxkZ7ui+fn4tTaCuSNyA/chQFGlgEjRyC+baMuS+koi pQyJf1oA9Nt/VdXD5ZcKNRbRm1WFkmWFevkQKIgydAn2odNEKnRffC+5SpEn8PGx8YKA KAikU6goGJfnAPCar6IlUi6RApdrttQ9s7tu0WMIfJ7qer/q9zyQxkbZm8Z/BYgryFn9 RRMi3I3ufHXvZGKuKWWEdju7srfSvbzh+a+PxAQrGsFAfjJPGK6k324YA3xdJerUIojC q/Aw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f77si1821618itf.51.2018.02.15.07.05.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL43-0001yV-MI; Thu, 15 Feb 2018 15:03:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL43-0001x1-2A for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:11 +0000 X-Inumbo-ID: 8136153c-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 8136153c-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:22 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C52DF1435; Thu, 15 Feb 2018 07:03:04 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B604D3F41F; Thu, 15 Feb 2018 07:03:03 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:35 +0000 Message-Id: <20180215150248.28922-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 04/17] xen/arm: Adapt smccc.h to be able to use it in assembly code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/include/asm-arm/smccc.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 2951caa49d..30208d12ca 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -25,18 +25,20 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0U -#define ARM_SMCCC_FAST_CALL 1U +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 -#define ARM_SMCCC_CONV_32 0U -#define ARM_SMCCC_CONV_64 1U +#define ARM_SMCCC_CONV_32 _AC(0,U) +#define ARM_SMCCC_CONV_64 _AC(1,U) #define ARM_SMCCC_CONV_SHIFT 30 -#define ARM_SMCCC_OWNER_MASK 0x3FU +#define ARM_SMCCC_OWNER_MASK _AC(0x3F,U) #define ARM_SMCCC_OWNER_SHIFT 24 -#define ARM_SMCCC_FUNC_MASK 0xFFFFU +#define ARM_SMCCC_FUNC_MASK _AC(0xFFFF,U) + +#ifndef __ASSEMBLY__ /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) @@ -62,6 +64,8 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +#endif + /* * Construct function identifier from call type (fast or standard), * calling convention (32 or 64 bit), service owner and function number. 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[192.237.175.120]) by mx.google.com with ESMTPS id b5si217232iog.291.2018.02.15.07.05.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL45-0001ze-Ta; Thu, 15 Feb 2018 15:03:13 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL44-0001xD-F9 for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:12 +0000 X-Inumbo-ID: 81ff4cc4-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 81ff4cc4-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:23 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F3A115AD; Thu, 15 Feb 2018 07:03:06 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1001A3F41F; Thu, 15 Feb 2018 07:03:04 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:36 +0000 Message-Id: <20180215150248.28922-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 05/17] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advance. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/arm64/entry.S | 56 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..67f96d518f 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1 (default 1). If 0, + * we rely on the on x0/x1 to have been saved at the correct position on + * the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,45 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, x0 + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03 From patchwork Thu Feb 15 15:02:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128462 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846950ljc; Thu, 15 Feb 2018 07:05:46 -0800 (PST) X-Google-Smtp-Source: AH8x226pPm5s/c/PlYuL6ZwWJuCMoBOyYKkflAGI3Fz6ss7G/Yt+N3+ajc4ioM12UfY2TiggPYVd X-Received: by 10.36.61.142 with SMTP id n136mr3832098itn.6.1518707146550; Thu, 15 Feb 2018 07:05:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707146; cv=none; d=google.com; s=arc-20160816; b=OjLz666AdiX2dif3PnOgv2YwxttqVepWZyL4R/+Vn0PV6Ir4yY1HQeDmxp1KAHN109 Y0lvaCfwivK2Q10iMcEtRaJNlnJPulAcq+JFE1/pJsmA4qo1Z00iyiSRgA7HCFfORUGF rmRplKqOVCiM2tZGddabRrKjqepG8NbWfDpLGACE+ysbwGdweecxQmt8GllEtLgGPT4f OxzP2a+EccxLMUSg7CwurnQTLwO4xzRQCscTbr4BYvKaAex6SviMSPzPbAr9Lnr6dtko 2VZMFm9TWlB+jCUz+2jgJ9IZ8NGfEHVu2pv4OfLC9t8doYNJgMMK0vn1Tec4eIGRZh4S HabA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=SuMOPMQSRPu1B0Ke2ZtElhm/TB/kAemeaIvkat+Gutc=; b=uypfUq0Tg3e6ddBs9SDpKq6j2TBkfjvm+hsULGCW3hBzhrhhK06OjwXBrvXhbVU6cK hmJOuErM6XspbFX57UK2bJdX6TDcYcz8WSG8zbs7jA3TS9YS+a7Lg6oFJgQWHjpTaENK +OuYLzI+tl6kjExA6+7tB1+o2+blBK5QvudKDh0NwBnwm1CAsVVPUbLaVc+sx8cgIHM7 Z6LKfqcIAV2pErKExxHUp6OHu+vpIij2CcqkYy71xq5XJxQDyrjI+qCM/dWKfXJYJeGQ os0MxfgOEp0sXnpOBMa3RbRVajkFWKfCUEkKoNnBhqN+LPQhV+IgvFewE/6NMlQ99X9i 6BEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 42si151295iog.191.2018.02.15.07.05.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4g-0002UY-76; Thu, 15 Feb 2018 15:03:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4f-0002RY-8A for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:49 +0000 X-Inumbo-ID: 82c8e438-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 82c8e438-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:25 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D39C15BF; Thu, 15 Feb 2018 07:03:07 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5E10E3F41F; Thu, 15 Feb 2018 07:03:06 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:37 +0000 Message-Id: <20180215150248.28922-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 06/17] xen/arm64: Print a per-CPU message with the BP hardening method used X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This will make easier to know whether BP hardening has been enabled for a CPU and which method is used. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babcuk Acked-by: Stefano Stabellini --- Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/cpuerrata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index c243521ed4..8d5f8d372a 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start, static bool __maybe_unused install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, const char *hyp_vec_start, - const char *hyp_vec_end) + const char *hyp_vec_end, + const char *desc) { static int last_slot = -1; static DEFINE_SPINLOCK(bp_lock); @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, if ( !entry->matches(entry) ) return true; + printk(XENLOG_INFO "CPU%u will %s on exception entry\n", + smp_processor_id(), desc); + /* * No need to install hardened vector when the processor has * ID_AA64PRF0_EL1.CSV2 set. @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data) */ if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); + __psci_hyp_bp_inval_end, + "call PSCI get version"); else if ( !warned ) { ASSERT(system_state < SYS_STATE_active); From patchwork Thu Feb 15 15:02:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128461 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846947ljc; Thu, 15 Feb 2018 07:05:46 -0800 (PST) X-Google-Smtp-Source: AH8x227ckv0VhXRRxfh53/qv39a5Cyg9MRiHVcfJYRXpN2+B1XDP8OeLHgfdX+SdznsrCD5RgTl7 X-Received: by 10.36.90.147 with SMTP id v141mr3520415ita.64.1518707146423; Thu, 15 Feb 2018 07:05:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707146; cv=none; d=google.com; s=arc-20160816; b=UxrqqngF/XY/TqxFH7Oi/+F7vXkmBY+ixMAPotiwuV7YqJJhMhYlPn/xVtVKdtqFp6 9YWtGQBksrHhL2IcW3Yymn4sqVd1FxGXv2uD1tw5gBlWjuPptct7K76DjMFxHMLgCZrH n7yyBxsI7/2ZXLWBSqM622g6f1qQ19K6rNxPHJ0utzq0GP1uRj7lAiDZ71fZ6aaQ5fAy bZIOqt0rV2g5+6P+tFOJZh8QBrZnwmIsi1XzdqVNuRgh3F2GbptDpvGYMhO+AalkbSRe l5gTKzyXZLxdf6AmwrEblbvaLk8C3FvpcBigmms84XsTGBGVEFMx/bCcMXwa+eC3Gk4B ZOBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=QcBvRqzHWwMglXQBcwVQt119JP33T0BAN6gISsqgXek=; b=DBE/mcDMIEs2ByqpdX9dFZPLkZxBel43+132XrSsVsyQv7osSCFSSXMrSC4EA48oov Cou+d4F6NEcKtctMNkgBNe0nh4qEmz8cjcXPJvVutxmTCHrzHLhGvfibg7kPjVsZi1Uz 0ihTkrAunR434ZB0R8Qb9S7FT7SCGn98kakpkgx7FGgTYfz2Ut9VTuwbGhRrafzqkE2Y XPsgBGDlvNEYNDoaEjq7KolcPcfU2BBlfgd/M8Mw+ZS31fdR9XvGQwhcw5qFBI7k8gEV J3KJ8JTvdp9zmNfC9XzSk1eBvHW9It7MsbWHxZ01wersvbxdkVDfDduRMjHRYwAtHH/f TSfw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b123si2571iti.123.2018.02.15.07.05.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL48-00020O-3u; Thu, 15 Feb 2018 15:03:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL47-0001yB-84 for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:15 +0000 X-Inumbo-ID: 8391f313-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 8391f313-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB31A15AD; Thu, 15 Feb 2018 07:03:08 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ABED23F41F; Thu, 15 Feb 2018 07:03:07 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:38 +0000 Message-Id: <20180215150248.28922-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 07/17] xen/arm: smccc: Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} to easily convert between a 32-bit value and a version number. The encoding is based on 2.2.2 in "Firmware interfaces for mitigation CVE-2017-5715" (ARM DEN 0070A). Also re-use them to define ARM_SMCCC_VERSION_1_0 and ARM_SMCCC_VERSION_1_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 30208d12ca..d0240d64bf 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,8 +16,20 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ -#define ARM_SMCCC_VERSION_1_0 0x10000 -#define ARM_SMCCC_VERSION_1_1 0x10001 +#define SMCCC_VERSION_MAJOR_SHIFT 16 +#define SMCCC_VERSION_MINOR_MASK \ + ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) +#define SMCCC_VERSION_MAJOR_MASK ~SMCCC_VERSION_MINOR_MASK +#define SMCCC_VERSION_MAJOR(ver) \ + (((ver) & SMCCC_VERSION_MAJOR_MASK) >> SMCCC_VERSION_MAJOR_SHIFT) +#define SMCCC_VERSION_MINOR(ver) \ + ((ver) & SMCCC_VERSION_MINOR_MASK) + +#define SMCCC_VERSION(major, minor) \ + (((major) << SMCCC_VERSION_MAJOR_SHIFT) | (minor)) + +#define ARM_SMCCC_VERSION_1_0 SMCCC_VERSION(1, 0) +#define ARM_SMCCC_VERSION_1_1 SMCCC_VERSION(1, 1) /* * This file provides common defines for ARM SMC Calling Convention as From patchwork Thu Feb 15 15:02:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128463 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846974ljc; Thu, 15 Feb 2018 07:05:48 -0800 (PST) X-Google-Smtp-Source: AH8x225bOPzb6ccASl/4CQA3ddVJVCG67yoDk+JEekz1whpMN5tnnhZxxXoot73MTP9semKO57xs X-Received: by 10.36.124.1 with SMTP id a1mr3773891itd.92.1518707148126; Thu, 15 Feb 2018 07:05:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707148; cv=none; d=google.com; s=arc-20160816; b=Fm8HY+9cDkAl38gt3/hTMuxWoiXIPKOeGbqCbnjqaZwAKk4l/G9NM3QL3YHGY+TCat UU/wZcPo1Z4SH1vmhVNU2YVN7d4MAEfSqD46re/6Nl+myTuROyCvW1vCTdnBsVZc0vvm EOiVuaXwcdvZ4L3czkfVxIZiEyWpMgAoDNacs0hoM40MUe1ay2AxSzKNE2NOLUAtAq09 89iA/5jw0wx5JEHagZfuhoQKnLcBPrgRWyAdIYRntXdOstU08R1Ps/IldRr6pWA3VZq9 t9FEr/ZZl9QcdFULuvbR1D0i4Olfu67UY/7PN+OOKSTrWC/4mf/yYtaQVToty4zlWUnx gMqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=Aef7lbEgfyEQoFMfMiLD87dPnfQu5aWm8WnUIgfmxss=; b=i3tU3s6KDqTl8t2EN1nHj77OGAqXRdOuBkRf8IVSNWMkfpJou/ttpeJlfBgTnDtSlB bzOCYj0A6OgI5FuEIHhITvREiVLsUtDYp4OEMgc+w/n/QVBj2M1ljNaUsxgVjRP2HSMd G9T0/zamYPrntDpqUHqVK3/iuTOLNq0+SXsVlXdAsSTmVeYuGVonp7bQsbLi2gKoapHu H97Nq3X9OP+KXpb+Hd04sSzk7w6MxC3b4OZA7+vrGhy4OJEssX/AKOkTvThzBz3J1tYh W4TjitAl1JpPqgcCHJkHqLAxvZK/sk/wrBU2S1y/1Y6rdeOQoJfmglN+zADVL3WOQ5FF doeg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p124si401806ite.0.2018.02.15.07.05.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL49-000213-Ae; Thu, 15 Feb 2018 15:03:17 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL48-0001yQ-7W for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:16 +0000 X-Inumbo-ID: 845b7499-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 845b7499-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1525515BF; Thu, 15 Feb 2018 07:03:10 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 05C673F41F; Thu, 15 Feb 2018 07:03:08 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:39 +0000 Message-Id: <20180215150248.28922-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 08/17] xen/arm: psci: Detect SMCCC version X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or earlier) and the function return an error, then we considered SMCCC 1.0 is implemented. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v2: - Patch added --- xen/arch/arm/psci.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 5dda35cd7c..bc7b2260e8 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -37,6 +37,7 @@ #endif uint32_t psci_ver; +uint32_t smccc_ver; static uint32_t psci_cpu_on_nr; @@ -57,6 +58,14 @@ void call_psci_system_reset(void) call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } +static int __init psci_features(uint32_t psci_func_id) +{ + if ( psci_ver < PSCI_VERSION(1, 0) ) + return PSCI_NOT_SUPPORTED; + + return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); +} + int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; @@ -82,6 +91,24 @@ int __init psci_is_smc_method(const struct dt_device_node *psci) return 0; } +static void __init psci_init_smccc(void) +{ + /* PSCI is using at least SMCC 1.0 calling convention. */ + smccc_ver = ARM_SMCCC_VERSION_1_0; + + if ( psci_features(ARM_SMCCC_VERSION_FID) != PSCI_NOT_SUPPORTED ) + { + uint32_t ret; + + ret = call_smc(ARM_SMCCC_VERSION_FID, 0, 0, 0); + if ( ret != ARM_SMCCC_NOT_SUPPORTED ) + smccc_ver = ret; + } + + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", + SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); +} + int __init psci_init_0_1(void) { int ret; @@ -173,7 +200,12 @@ int __init psci_init(void) if ( ret ) ret = psci_init_0_1(); - return ret; + if ( ret ) + return ret; + + psci_init_smccc(); + + return 0; } /* diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index d0240d64bf..bc067892c7 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -52,6 +52,8 @@ #ifndef __ASSEMBLY__ +extern uint32_t smccc_ver; + /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) { From patchwork Thu Feb 15 15:02:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128474 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1848769ljc; Thu, 15 Feb 2018 07:07:16 -0800 (PST) X-Google-Smtp-Source: AH8x226jja2TWsgEEORUNBkzHl7sgs7ouH89oGWxT/FYYg084/iBmRgvAKVBrCmO0s30de/XO75P X-Received: by 10.202.197.70 with SMTP id v67mr1874843oif.218.1518707236442; Thu, 15 Feb 2018 07:07:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707236; cv=none; d=google.com; s=arc-20160816; b=I/StQFbOSGB4fHjb7S1+MaoXyFLedG6HxJUXNVUtOUnNMrOuC9r8PSEoFVKzxVXuP8 8X3RtHfkEaXs951AiV6z9o4lQFoC0JPG3UQjBORcn90E5gbHVStpmhfWWRawh/TsuPBn 9gnRJsDfTLTwpZ1qy5Bx7VZh42FWB1sIcNp8lwCaMUuk5NH1w2jZdMKwCVsHD1l9VDqo 3ihD6Ko7fXReL2ryIofafI5/Uwx5G0OY+aTs14bBgIGWgDmnQY3iPE6fpMUQ+p42YgiL Nud6tOZGpF5v02mW+TxdDM6/VB1tdglfMD8xVdjfiK8OwZJKj+AqpN4IHDroIuP1max5 c+dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=RbgpMK4oPVMVlrn9q/08wx2jZAC/Wap3/PtHoTQCp1k=; b=dd+Z3wn7yLf5/J/Mwou9mI1Hc8j8omVi2FTbXT9HHaVU5GRBx3WXqHvPiYRebEIeSB YB+lQqco4T3KRrMoDOt7Mcv4V5zmgOS5ywkyWa+ckrxz4kbuCmpakaf4ihglypBEE5WM 88eVfvogADw/tSln6eFCY8rM/AH+0jd7gJM7v2/Qy6kg0F7mf9ffCah/2S6KGmTPTUZt QbUG4XVnYK+5j0dM7H5BbE4wy0FiKUwmSU8CcdW8kIDi6rMleA3vMkoT7jB8rKW/xfYe CIzvrvOd9m4CO0XFH6UihL8AA5Az6uUaDYH6pNeWDAqhoz9YLOeQHP2wQxPv3jsBJFJb w60g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f12si1311987itb.103.2018.02.15.07.07.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:07:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL62-0003NH-Nz; Thu, 15 Feb 2018 15:05:14 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL61-0003JP-6a for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:05:13 +0000 X-Inumbo-ID: 852487fe-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 852487fe-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:29 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62F9A15AD; Thu, 15 Feb 2018 07:03:11 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53E0C3F41F; Thu, 15 Feb 2018 07:03:10 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:40 +0000 Message-Id: <20180215150248.28922-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 09/17] xen/arm: smccc: Implement SMCCC v1.1 inline primitive X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that woudl otherwise be clobbered by SMCCC v1.0. This patch has been adapted to Xen from Linux commit f2d3b2e8759a. The changes mades are: - Using Xen coding style - Remove HVC as not used by Xen - Add arm_smccc_res structure Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index bc067892c7..154772b728 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -78,6 +78,125 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +/* + * struct arm_smccc_res - Result from SMC call + * @a0 - @a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/* SMCCC v1.1 implementation madness follows */ +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register uin32_t r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register uint32_t r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + * + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define arm_smccc_1_1_smc(...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile("smc #0\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if ( ___res ) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while ( 0 ) + #endif /* From patchwork Thu Feb 15 15:02:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128458 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846858ljc; Thu, 15 Feb 2018 07:05:42 -0800 (PST) X-Google-Smtp-Source: AH8x224A0Mc+925GJ5tlJ3cejAyeIPVNEwmowtNFjy+X+3e3Y0OxbjOcWDus7zBpPXIL4SvAlWFF X-Received: by 10.202.237.212 with SMTP id l203mr2104827oih.109.1518707142448; Thu, 15 Feb 2018 07:05:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707142; cv=none; d=google.com; s=arc-20160816; b=K+cyBMWva0GYAmhil+KUgDRBOB7KWxZtk+LzeSqjjGMcttUoUjVNB78Ndqzt5iBt0K E8T6P/2Dl4C4nnbKPmNlQlfRphYgXe+GYn70JReao6skTu3/j0C7hLp2bGn3gZ7cVmqk P73enBogUrUom3TvOXzEjwkVrzbyUjUCd/8rPwW0NTWMZP/4T99t+yS2dKhitjIcXSyL +WuIdQ4pdH0gkonC1M7wI+vNUaOCMXeoyJW+ZCLD4DnO0Encnr9rn7kTI20w/KQfqIxI KSGd5ro4TTTP2m9Igg3r42Zp8vsE1W7KwSUgmCnEn4XZMxIVNqSXQOl5OkKaQisK+sgC zLcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=U+oZkLsBlRLmtnn2hTxx13JA6R04LAD3RBFXU5kKoP0=; b=MjPBv6BsacspgYv4mdJWG6yL4+3PsbfD/Ve9MJRYpxFUVvDoE/xNvXwiIEBcE1PU+l Iv5Lw8NDvrOcH5sBMOk21sahYVP2YmYLGykkDTNV2Bls0uvguni+paqDNI7hydelGE67 2j7eboiyfJN30j8rjx82ToMog90r/zoJ0BfWLiRzUz2zwRDOLu7qFUkCi+lwSbFXi2bb wmJ1PJ0QdWvlsrrooyPvcN/L/XtWsGSitrQrGl9WxngtOg2JxR4FmAMQ194EAzV8TKmn Hl5nYWsAFMdMSnRbs12fz8soe2sLJaJkfxN80eBhCOxzVZhp9togccJbp/+wJ674mpdF tLFw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o205si8179234itd.161.2018.02.15.07.05.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4C-00024n-O2; Thu, 15 Feb 2018 15:03:20 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4B-0001zt-LZ for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:19 +0000 X-Inumbo-ID: 85ef62c7-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 85ef62c7-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B1CBC15BF; Thu, 15 Feb 2018 07:03:12 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A2A9E3F41F; Thu, 15 Feb 2018 07:03:11 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:41 +0000 Message-Id: <20180215150248.28922-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 10/17] xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Changes in v3: - Add the missing call to smc #0. Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 13 +++++++++++++ xen/arch/arm/cpuerrata.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 1 + 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 4b7f1dc21f..981fb83a88 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -16,6 +16,8 @@ * along with this program. If not, see . */ +#include + .macro ventry target .rept 31 nop @@ -81,6 +83,17 @@ ENTRY(__psci_hyp_bp_inval_start) add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) +ENTRY(__smccc_workaround_1_smc_start) + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + smc #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_1_smc_end) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 8d5f8d372a..dec9074422 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -147,6 +147,34 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, return ret; } +extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; + +static bool +check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +{ + struct arm_smccc_res res; + + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return false; + + if ( smccc_ver < SMCCC_VERSION(1, 1) ) + return false; + + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + if ( res.a0 != ARM_SMCCC_SUCCESS ) + return false; + + return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); +} + extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; static int enable_psci_bp_hardening(void *data) @@ -154,12 +182,14 @@ static int enable_psci_bp_hardening(void *data) bool ret = true; static bool warned = false; + if ( check_smccc_arch_workaround_1(data) ) + return 0; /* * The mitigation is using PSCI version function to invalidate the * branch predictor. This function is only available with PSCI 0.2 * and later. */ - if ( psci_ver >= PSCI_VERSION(0, 2) ) + else if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end, "call PSCI get version"); diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 154772b728..8342cc33fe 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -261,6 +261,7 @@ struct arm_smccc_res { /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) +#define ARM_SMCCC_SUCCESS (0) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Thu Feb 15 15:02:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128464 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846991ljc; Thu, 15 Feb 2018 07:05:48 -0800 (PST) X-Google-Smtp-Source: AH8x227FK5AMyaWPWYk8DrlTlq/xT1EUozuE0DB9Y38ex49VFCRnxCPQZorvwanCdId9bUGMQoTg X-Received: by 10.36.233.68 with SMTP id f65mr3580959ith.149.1518707148786; Thu, 15 Feb 2018 07:05:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707148; cv=none; d=google.com; s=arc-20160816; b=pxx10buefjsO/+6EeMqIWx3jHwinzhZeiAQ1U0FdoeVdOoNfdbfe8rlWEbUnQLB5rL w6BEixWYTqFPGHDrFA4i6sl7GNpIr1pBSbxCkJQv8ZDMNJ//syFtWXpFUrl3r0WOvJ5N xcNp78yJCaN8oqNGH4UR9ipOKwZOnDvKbbXgAQjLA/JgwbFH+CCqPzA/XdCgrGkW+tgw IH5AJTvJXO0qr+i+6eRmpllFhOd5A+C1AaxoXkwiH0WjjIkwhvnlbrsVAoGGawmw42uB uIrko3TKksBL4c5i+xWkq8vWvQmhOafdPMJc+z6VRJ8uFVI3R7/3oJilT73vZyM97Kq4 tX6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=g2GU8qcz8xRrLkhm0+WGNac/7NToLJpvPGizIVhaTJs=; b=d0Q7CCsiCFEIERfEGXmbmwVJzTbOfuelouqoUBaveUaes4VM3th5XvcinxJlbLQnbW YKgcMT7I5Ti9ZgP1xA9TCYcOMHst9Bn+BvqOioFFQlz2jzY79ZKKx5ieF3JDBOesAQ+a vnZP+T7NgrqfuopmAL3PInF1DPoF+KUejbYOmpZMPhP718z12r37FcqXDN/eXFae3wWm oQtyRoxvFFdtcNhsvcyxg2iGKPH9FqtxDZASc9vdb6dkikFVrRCF/M/u5Dpr/mK1wiSi bRe+itV21rqbomOnYX99zxnT12QwUEOvqWyQ8FRWXIoTCqJkDjraC5cO6bkQLYzKr097 BSuw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v125si4853503itf.30.2018.02.15.07.05.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4D-00026S-V4; Thu, 15 Feb 2018 15:03:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4C-000204-Di for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:20 +0000 X-Inumbo-ID: 86b79084-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 86b79084-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:31 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B84415AD; Thu, 15 Feb 2018 07:03:14 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F08E63F41F; Thu, 15 Feb 2018 07:03:12 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:42 +0000 Message-Id: <20180215150248.28922-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 11/17] xen/arm64: Kill PSCI_GET_VERSION as a variant-2 workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. This is aligned with the Linux commit 3a0a397ff5ff. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 25 ---------------------- xen/arch/arm/cpuerrata.c | 54 +++++++++++++++++------------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 981fb83a88..27ff801ed3 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -58,31 +58,6 @@ ENTRY(__bp_harden_hyp_vecs_start) .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) - ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) stp x2, x3, [sp, #(8 * 0)] diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index dec9074422..4eb1567589 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -149,10 +149,11 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; -static bool -check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { struct arm_smccc_res res; + static bool warned = false; + const struct arm_cpu_capabilities *entry = data; /* * Enable callbacks are called on every CPU based on the @@ -160,47 +161,30 @@ check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) * entry. */ if ( !entry->matches(entry) ) - return false; + return 0; if ( smccc_ver < SMCCC_VERSION(1, 1) ) - return false; + goto warn; arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); if ( res.a0 != ARM_SMCCC_SUCCESS ) - return false; - - return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, - __smccc_workaround_1_smc_end, - "call ARM_SMCCC_ARCH_WORKAROUND_1"); -} + goto warn; -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); -static int enable_psci_bp_hardening(void *data) -{ - bool ret = true; - static bool warned = false; - - if ( check_smccc_arch_workaround_1(data) ) - return 0; - /* - * The mitigation is using PSCI version function to invalidate the - * branch predictor. This function is only available with PSCI 0.2 - * and later. - */ - else if ( psci_ver >= PSCI_VERSION(0, 2) ) - ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end, - "call PSCI get version"); - else if ( !warned ) +warn: + if ( !warned ) { ASSERT(system_state < SYS_STATE_active); - warning_add("PSCI 0.2 or later is required for the branch predictor hardening.\n"); - warned = true; + warning_add("No support for ARM_SMCCC_ARCH_WORKAROUND_1.\n" + "Please update your firmware.\n"); + warned = false; } - return !ret; + return 0; } #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ @@ -316,22 +300,22 @@ static const struct arm_cpu_capabilities arm_errata[] = { { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR From patchwork Thu Feb 15 15:02:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128459 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846907ljc; Thu, 15 Feb 2018 07:05:45 -0800 (PST) X-Google-Smtp-Source: AH8x2240FPGCrPinjWkI4H0QdlwsMpeq8b59axYcZrynn2L3WLXe04yvBxI0u61vAn/fKfsw9evK X-Received: by 10.36.58.135 with SMTP id m129mr3592157itm.52.1518707145129; Thu, 15 Feb 2018 07:05:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707145; cv=none; d=google.com; s=arc-20160816; b=qNXYf4Eb/UV6hSYTLWfFJHVIU+TktnFZcRDzQWqjOwj3/u4Gm11RuVOaayg7Y9Gb2I f7rX1jGpgYgm11wMYr3IG/nDEe53xt9T6oYn3MIOR0ABezBarBpZ3gSbBjDmgFjflqHP WfMgaDcMHMFJrglBXNh4A9Ltqn30/pJoAHMiPkYod48M6Lb11uFH+cWwJLgJ+1B0A3pv 1eRE8vfEJuSbC1G6HPn7GHhGtSa6KukxiZJ/L0lLCxGKoz0rXaMOrwIA5wMklE7PTpCB a91eOPl7n17/8Y0/QIsrs9TuZQqAACj2JC4Szch9P+OFPNUfXU3BkMrS3xfE9L0ja+KM JT3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=XZh2KG7+YWE1uTP1an54DbDQaurz7Y3NGsUEbbWIgpw=; b=JXmslA+SIjzveRTayOUKWvJc4O0Wnm5icFxVtZUeDDtntit+1c/RPJcplMrA+x9c5o L5ZwHiGjC3ndycuj4wC+5AQHpqIJqyH+W3NtEm8GSXNHarZThcUVgOhebKbAILC1o4ap rHjtefXDZvZiyZCr9ZWsmefxzA31ze5YvD28AvPUsPhtddVgsQ29/Fzf8ELorzqnnhBO FiElYVe9itIwtLL7Onsul/sOeo3pDMidV7auCkLFyef5bzgE47Oj/cHTxalkLFALsUhd aAhqdhuMWNJc0cDmxdaaaBO+Pt1BLA++6hE7VNDJRJoECL4p6lNX+SJVuUOLP1nwd4Al D54w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id j204si881971iof.162.2018.02.15.07.05.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4E-00027A-5k; Thu, 15 Feb 2018 15:03:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4D-00020l-Ct for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:21 +0000 X-Inumbo-ID: 87810186-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 87810186-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5976215BF; Thu, 15 Feb 2018 07:03:15 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4A51D3F41F; Thu, 15 Feb 2018 07:03:14 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:43 +0000 Message-Id: <20180215150248.28922-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 12/17] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- The reviewed-by was kept despite move this patch towards the end of the series because there was no clash with the rest of the series. Changes in v2: - Move the patch towards the end of the series as not strictly necessary for SP2. - Add Volodymyr's reviewed-by --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 19ee7caeb4..7ea3ea58e3 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -137,8 +146,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = { From patchwork Thu Feb 15 15:02:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128473 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1848407ljc; Thu, 15 Feb 2018 07:06:58 -0800 (PST) X-Google-Smtp-Source: AH8x226nObOizD1ySnr8FEKRi2vLk4YMMMlj/el5b/ZxeHt/Cv+wrK9wB93Da9LA39aDC7Zztrif X-Received: by 10.107.134.95 with SMTP id i92mr3851759iod.210.1518707218198; Thu, 15 Feb 2018 07:06:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707218; cv=none; d=google.com; s=arc-20160816; b=VduhuYMr8zz1sMow9Jp8wF3cnouwdY4WGhsHOyWHaIu0U9g5mHCteUkSPVxVJjJv8I hhLCVdnBwnj+duy9pXSAsN9SX/N38y2uvI3Xz9azUegRJpZCSsN3uAVlw8T1QxqLKVkv OoBIx3RfW12mPDRmLy12TX6qEHbrvjUUoks07FYTTmA0BEdVwT2ilEpoxY7t74k4X51e TVuqUZOHrTDTrPG+uw918z5s5pjqKT24Fc7ab0DB3g0MQYlkbnpzPiBrVAtFukP1/afC kMNFfPQINMfI2RHK3v5jH/VGA6uNBSiIlHIv3TgMMmrACOFU1UtVgcleNEpYqMcXX97x O5rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=WQ4h6VxUZbxDmnbl+LNpz19fsQgpEiJgGS1fJEa25QU=; b=uLiMzUtsT8ijGqk3xBTlpeP+5gBcVJ3ZAm9B7cfQoZL4+pwWNAQsmAoqm5o0tOvjav DmmdCLSZsQE9TLlKTRKtwt1SA1I+DpHf/+mdvZfNrppnNIAahraMPEejh2eQOJg9Qjkm Ameg5uxm86o4hYaNjwXLI39mLNfm23xmKQvt/Oy/gtxI6Gi5lVW2ljgSOinQMHwiD3Wc dgK1iNjt0W1EhKI9mMmP7vO9VHquTAE6L9Fo5pU9MQPHktQv0U9C4PbbGYiEKzYTULh1 JsJ6SlUdvMPVxHdQXPkcn5yHATMqvNdDlPxsVEFeqNoKoALpd7b3w1a4A85MHveA0dhm VjBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l6si4616409iog.344.2018.02.15.07.06.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:06:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL5n-0003E9-GJ; Thu, 15 Feb 2018 15:04:59 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL5m-0003BT-1K for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:04:58 +0000 X-Inumbo-ID: 884a5aef-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 884a5aef-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:34 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A79F315AD; Thu, 15 Feb 2018 07:03:16 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9883C3F41F; Thu, 15 Feb 2018 07:03:15 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:44 +0000 Message-Id: <20180215150248.28922-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 13/17] xen/arm: psci: Consolidate PSCI version print X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen is printing the same way the PSCI version for 0.1, 0.2 and later. The only different is the former is hardcoded. Furthermore PSCI is now used for other things than SMP bring up. So only print the PSCI version in psci_init. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/psci.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index bc7b2260e8..7a8cf54e6d 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -136,8 +136,6 @@ int __init psci_init_0_1(void) psci_ver = PSCI_VERSION(0, 1); - printk(XENLOG_INFO "Using PSCI-0.1 for SMP bringup\n"); - return 0; } @@ -183,9 +181,6 @@ int __init psci_init_0_2(void) psci_cpu_on_nr = PSCI_0_2_FN_NATIVE(CPU_ON); - printk(XENLOG_INFO "Using PSCI-%u.%u for SMP bringup\n", - PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); - return 0; } @@ -205,6 +200,9 @@ int __init psci_init(void) psci_init_smccc(); + printk(XENLOG_INFO "Using PSCI v%u.%u\n", + PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); + return 0; } From patchwork Thu Feb 15 15:02:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128471 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847189ljc; Thu, 15 Feb 2018 07:05:57 -0800 (PST) X-Google-Smtp-Source: AH8x225Nu1bmg3cE5rG7P4xOn+YXdiI0O7VDZAuWXpYQCkJGCCcz/UQnL0KLG55Q2kDg6HMHMGfy X-Received: by 10.36.94.199 with SMTP id h190mr3471552itb.21.1518707157602; Thu, 15 Feb 2018 07:05:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707157; cv=none; d=google.com; s=arc-20160816; b=0/59b5hfCcEDoI53LHJzAucVcKSWq8IiMfOosUQnYVbqDMZ05LBTrYcbRJPe7FZ7eM eFZcpwPSnXevUx375ieBf2BTtJRdRf52JmqkI8tTgoTHfHVif3Q3soNPsr7OY2RATU5M 3YQiiCbpRJ2VI5KL1Rn7FvnrWZHbbLSqr0BdKgkoIndMQ/p+48lcFcZLd0M/3mAzu8Md 3sE+c3EVkwyto52A7M1rL1q1wf3DbKu9gyF8MUd30oOq4D8yTRA4ZHGNUvdt5b5JRYF2 jrZQ+XdAXw9Bw40ToVLEX0roQ4u697/UCo/p8/sI/zlHX5KvZXMH58gLUJVKFwEFchz3 HWmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=KXwCV7soUHAjALcgZzeY07UPq0gNOctBsqmp24pApgs=; b=Ei0eLOjNwzKFUcYW/UJ+fDiFPJ9PM+2rUrUG79n9J9i6ibDo/NGnF9dhiXAOvPwzSf 6MgyBTag291H9re/Vs4fx6ESsyjF4tmN7eomAoZnZFJ1hSqYZs+0GQHvkuSC6xCKbaS2 tFc6r7JMgHazLG6sm9tZa5VYkZtiC5AJiJS/uurbtTQNJ8wo6Zs/GIW/LRMAXDC9hbNn pNR7rbhTL2NMf3h5D4vKkyLKyYaoPkjYR9sLvtIYsMxH1QBKUgnNPcO1aOk7mAlMggYi GGMijUT1/LcPa8HYi79KophSonT9DLP7dLUKQ+2BAIHHtI9ans16uGnotn+DVvtiKcdC rwIg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 135si24672itp.149.2018.02.15.07.05.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4C-00024O-HM; Thu, 15 Feb 2018 15:03:20 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4B-000239-FS for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:19 +0000 X-Inumbo-ID: 447669e2-1261-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 447669e2-1261-11e8-ba59-bc764e045a96; Thu, 15 Feb 2018 16:02:40 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0173415BF; Thu, 15 Feb 2018 07:03:18 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E650A3F41F; Thu, 15 Feb 2018 07:03:16 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:45 +0000 Message-Id: <20180215150248.28922-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 14/17] xen/arm: psci: Prefix with static any functions not exported X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A bunch of PSCI functions are not prefixed with static despite no one is using them outside the file and the prototype is not available in psci.h. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v2: - Patch added --- xen/arch/arm/psci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 7a8cf54e6d..5d94a9a9ae 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -66,7 +66,7 @@ static int __init psci_features(uint32_t psci_func_id) return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); } -int __init psci_is_smc_method(const struct dt_device_node *psci) +static int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; const char *prop_str; @@ -109,7 +109,7 @@ static void __init psci_init_smccc(void) SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } -int __init psci_init_0_1(void) +static int __init psci_init_0_1(void) { int ret; const struct dt_device_node *psci; @@ -139,7 +139,7 @@ int __init psci_init_0_1(void) return 0; } -int __init psci_init_0_2(void) +static int __init psci_init_0_2(void) { static const struct dt_device_match psci_ids[] __initconst = { From patchwork Thu Feb 15 15:02:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128466 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847035ljc; Thu, 15 Feb 2018 07:05:51 -0800 (PST) X-Google-Smtp-Source: AH8x225m5/uap+vJxwiGg37uv+TGyZNUpne7MohcUdy86l0TjDocJcTZmR+Xsy4ndkHWoqekyJZs X-Received: by 10.157.54.134 with SMTP id h6mr1877622otc.243.1518707150984; Thu, 15 Feb 2018 07:05:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707150; cv=none; d=google.com; s=arc-20160816; b=OVsBnCPDolqWq/eri0Nm3VxhCMgCD+rjTWUEltsEhvP0luUX8IWCqiSr1S4zNQwIUg eo9Pq5v6MYiL7ey6TSs3jD76s4sG89B2rgu9XwnMMQJymECeXjvRrB6sxW9CkU5HuAuw WhAoJhxdaz0MF5aa3bLiafFk2BR5UKfDcRVjW49dLXio1CTpgvyx+c2hFzwfwPjyvFMZ AB5lhLedeCHV3DVt4Cj5aK8TkgksoxfSKOoH4VtenwvKcyyfbTxZj0yafcM5kHeuzB86 3UhCFWo5PNv1k6XE0lrTfvNydBC6NQq2aORBXQtTDVNPMgL6dF6N/Gue5d7SM1wHg9XI mizg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=yMZHhv3cygTgEtBBq22SIcF+sb9WycPtwWcSdEZ5Z30=; b=PBFNTWC750OppjiL4O0yAqpELNF9qiW2twPSYAntF8750KTHdWkC92XRsf+Gr7Pwd5 I11XRlaEJT03HcY9Rg92T7ilCOZedazGIWLdI6DciN50fm/0UUJ+Hfi8qy0QUgeS2WFk Mq8SQTKQKsmyIUY9qKpF9FxJxJu587hl7/scHRv/m4ywrUe/WF/sO7H8VfZjtvSBOk/9 E1VbRCQBtWVGeNN6lWlX/g3BNf6PO26VsUTp6e9yciOBZztiV3hLPgGGBgqHb4b5zfjx f/zhOojX+lNrIjIXydpqBHboo7wKFhJVy+mEujGhHu1D2IZqF1JT6OenhWaczUuy8k4w kbPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t1si8610027itg.87.2018.02.15.07.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4I-0002Cp-Nt; Thu, 15 Feb 2018 15:03:26 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4H-00024N-Iw for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:25 +0000 X-Inumbo-ID: 89f45d75-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 89f45d75-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:37 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 748E01610; Thu, 15 Feb 2018 07:03:19 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4193E3F41F; Thu, 15 Feb 2018 07:03:18 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:46 +0000 Message-Id: <20180215150248.28922-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 15/17] xen/arm: vpsci: Update the return type for MIGRATE_INFO_TYPE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" >From the specification, the PSCI call MIGRATE_INFO_TYPE will return an int32_t. Update the function return type to match it. Signed-off-by: Julien Grall Cc: mirela.simonovic@aggios.com Reviewed-by: Stefano Stabellini --- Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 7ea3ea58e3..9a082aa6ee 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -186,7 +186,7 @@ static int32_t do_psci_0_2_affinity_info(register_t target_affinity, return PSCI_0_2_AFFINITY_LEVEL_OFF; } -static uint32_t do_psci_0_2_migrate_info_type(void) +static int32_t do_psci_0_2_migrate_info_type(void) { return PSCI_0_2_TOS_MP_OR_NOT_PRESENT; } From patchwork Thu Feb 15 15:02:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128470 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847108ljc; Thu, 15 Feb 2018 07:05:53 -0800 (PST) X-Google-Smtp-Source: AH8x2273XtOHk7DwzulABp8T4UptJH8nUdE7Z4YPbVZ8LSKku2Qv8WysBaxqqeYtNQb91OXsY4lD X-Received: by 10.36.39.129 with SMTP id g123mr3535496ita.91.1518707153704; Thu, 15 Feb 2018 07:05:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707153; cv=none; d=google.com; s=arc-20160816; b=iEX6qK3KjUD690Kxo8zi1huYXURGnC6+tnVupLFMjn99DfksygEw1UGxXfTYeNsO44 xJNzegeArx8agGSZLfLlgq9bj2ycO4xb1IIaCCFKftUEAkRJNumSz6oCyLCi99s9ArEy nx6Q6W9ONW2Ea5oGM8YMo+jqAWS4G9KUUNlNFcABl3j9sQGHRK39cgNlLcVPP7zqrLi9 5PcSNWeKIT2ug2w4awGoERi+XXAcq8ketCPXupcMBQy0RdWDvS5Densjewz3VKTb7UQ1 bB3LPqD2XSFUSMcxbo+i+vv3FZes7Nsc4NWXiveqAgVopert4Sxy8eeX6jnnpH/LsLNH LsFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=a2cJjh23PDW30aJ2X5AoGwZApoCCEwTJIATcRLYHi5I=; b=zNqwDh8tvP0/m5zIs9wbqnWY4+OCIic8s1trY2A+FNqfbK/S1q1P60Zg/IR4Sz1f5d wB9Hy5gIrfHIlARO9zcr3Otc0zq8+0txcoPSQu3YfeUvBUcv8femDKtcGCdkxeWdxXGc 3+RMYTXgQ20gsjKBoRb8/EApeUzLAU1tuRsHURCM9cz5vl+azmcTYCjJOtQxkXLF/hyH 9n4b9enyNKHm2jmbgvv1h1op47a7PmYCqmE1J+puVUcAjjN4wZ7E8MiB9I4o+OWxVRhr d8XYuxylrlBlRNYQ6jk4WW2OVr8710ZSH3i5LQ0sIY5aiu25/pPVo1D0sazgAfJ5K1tX SuIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l6si4615095iog.344.2018.02.15.07.05.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4G-0002AK-GW; Thu, 15 Feb 2018 15:03:24 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4E-000280-O8 for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:22 +0000 X-Inumbo-ID: 463695b1-1261-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 463695b1-1261-11e8-ba59-bc764e045a96; Thu, 15 Feb 2018 16:02:43 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E61E515BF; Thu, 15 Feb 2018 07:03:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B36183F41F; Thu, 15 Feb 2018 07:03:19 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:47 +0000 Message-Id: <20180215150248.28922-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 16/17] xen/arm: vpsci: Introduce and use PSCI_INVALID_ADDRESS X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 added the error return PSCI_INVALID_ADDRESS. It is used to indicate the entry point address is known to be invalid. In Xen case, this error could be returned when a 64-bit vCPU is using a Thumb entry address. For PSCI 0.1 implementation, return PSCI_INVALID_PARAMETERS instead. Suggested-by: mirela.simonovic@aggios.com Signed-off-by: Julien Grall Cc: mirela.simonovic@aggios.com Reviewed-by: Stefano Stabellini --- Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 10 +++++++--- xen/include/asm-arm/psci.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 9a082aa6ee..1729f7071e 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -38,7 +38,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, /* THUMB set is not allowed with 64-bit domain */ if ( is_64bit_domain(d) && is_thumb ) - return PSCI_INVALID_PARAMETERS; + return PSCI_INVALID_ADDRESS; if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; @@ -99,10 +99,14 @@ static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) ret = do_common_cpu_on(vcpuid, entry_point, 0); /* - * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * PSCI 0.1 does not define the return codes PSCI_ALREADY_ON and + * PSCI_INVALID_ADDRESS. * Instead, return PSCI_INVALID_PARAMETERS. */ - return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; + if ( ret == PSCI_ALREADY_ON || ret == PSCI_INVALID_ADDRESS ) + ret = PSCI_INVALID_PARAMETERS; + + return ret; } static int32_t do_psci_cpu_off(uint32_t power_state) diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index e2629eed01..9ac820e94a 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -13,6 +13,7 @@ #define PSCI_INTERNAL_FAILURE -6 #define PSCI_NOT_PRESENT -7 #define PSCI_DISABLED -8 +#define PSCI_INVALID_ADDRESS -9 /* availability of PSCI on the host for SMP bringup */ extern uint32_t psci_ver; From patchwork Thu Feb 15 15:02:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128457 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846859ljc; Thu, 15 Feb 2018 07:05:42 -0800 (PST) X-Google-Smtp-Source: AH8x225/ypjpeLDDEzgG3cezLMYlDCj/IbKuclXsZjpCMT1usNDTXwF4TY9nK1Qxzqz+7pNOpfBv X-Received: by 10.202.215.86 with SMTP id o83mr1905756oig.125.1518707142448; Thu, 15 Feb 2018 07:05:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707142; cv=none; d=google.com; s=arc-20160816; b=NQd/pO8BOqDcCqhXv15Vam67cilnOpfICb1lgLoah5ly6a1gOlmRgwjimysB5zHCGG JDRW5Rz64EeQ1beY2z/Ju0Hwl/vP0ODv17a8HKZFabtu+ARzimZjcwPXv3RTUVVI0sdd 0azmi3+fBWvL9//reQFDAMAcf56sVznWkNRHc9lVY2llRSDMMAD8k6JJxhNFLPIxcg7c 8pmhQ9m2B+AgoBaabP3hl2/1MLt+kguVk9VwGAaMl7jdLEK5VuqMUcHGBZplQY538DVs 6OtRi/wKAoLmMeBkIJ+DZcvaOHPbazkKcYA9qqvfwTtA2ax8SCrgafOFhf1q+ILQBLIA P5kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=uTGBTk2AJDyI9pmU2IanUrmkx38ZnBdKDs5QSOFIKaI=; b=hf6DGk0MG/uGQv/DoaJGH/SR2FSDvmDhKsI99ipxh5s+tkjsyZlPcurUbBLmRfWa1n gvlqqgTO1vRD4bEvhWgsFqcBydE/vNxkN3NN8I/n50NfJxH4oKQdESQTotZiUh8k7tp0 uJQJy6Ekei80cZA3fWkQ9IsAfoKeQHoHrVeuA+h8sIfbr7gFSjun5HoLn7DOFfbshL1g DpQhAYeydI2z/79VzyYBtTFTlATc4ziyU3thzxX5Q4xS7r3zCfGHfXaT0f4xiJj+jrwo ElPnYAGqum5yxYn0ZRS1nV1XxaeAc3QGMrkPVYEurE2DshSM2EkEQmMPTL2fHb55fQ6A 0xCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k34si1462658ioi.117.2018.02.15.07.05.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4K-0002FX-VS; Thu, 15 Feb 2018 15:03:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4K-00028n-FH for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:28 +0000 X-Inumbo-ID: 8b9d4e1c-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 8b9d4e1c-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:39 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FED21610; Thu, 15 Feb 2018 07:03:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30B213F41F; Thu, 15 Feb 2018 07:03:21 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:48 +0000 Message-Id: <20180215150248.28922-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 17/17] xen/arm: vpsci: Rework the logic to start AArch32 vCPU in Thumb mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" 32-bit domain is able to select the instruction (ARM vs Thumb) to use when boot a new vCPU via CPU_ON. This is indicated via bit[0] of the entry point address (see "T32 support" in PSCI v1.1 DEN0022D). bit[0] must be cleared when setting the PC. At the moment, Xen is setting the CPSR.T but never clear bit[0]. Clear it to match the specification. At the same time, slighlty rework the code to make clear thumb is only for 32-bit domain. Lastly, take the opportunity to switch is_thumb from int to bool. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 1729f7071e..9f4e5b8844 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -28,7 +28,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, struct domain *d = current->domain; struct vcpu_guest_context *ctxt; int rc; - int is_thumb = entry_point & 1; + bool is_thumb = entry_point & 1; register_t vcpuid; vcpuid = vaffinity_to_vcpuid(target_cpu); @@ -62,6 +62,13 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; + /* Start the VCPU with THUMB set if it's requested by the kernel */ + if ( is_thumb ) + { + ctxt->user_regs.cpsr |= PSR_THUMB; + ctxt->user_regs.pc64 &= ~(u64)1; + } + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 @@ -71,10 +78,6 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->user_regs.x0 = context_id; } #endif - - /* Start the VCPU with THUMB set if it's requested by the kernel */ - if ( is_thumb ) - ctxt->user_regs.cpsr |= PSR_THUMB; ctxt->flags = VGCF_online; domain_lock(d);