From patchwork Mon Jan 4 12:22:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356369 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924389jai; Mon, 4 Jan 2021 04:24:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJx3p1EJGUNNkXoTBxeoAA/AgoJyQIdrDEDzYkYfuNfqM1buXxav7Irjc0wNNfoLhx1ldqY2 X-Received: by 2002:a17:906:a29a:: with SMTP id i26mr65677256ejz.45.1609763084505; Mon, 04 Jan 2021 04:24:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609763084; cv=none; d=google.com; s=arc-20160816; b=Qk89JD520sLGepdOfFU+il8rtxKenO2cqXajFoYe55lOAjwyFkWx61wmiFNOad8M6q KPt3XpqYrY+uxaUVjScmsVmkBbZFpp7jaPDFH4qN+acu2z2MkM1qrbRhNsvgj1pT0KfK 2P8Uk+m2SHZEDKYX6tHbm5ywLUlui3dO5swW3bbAUkGE/LpMfe9QQUA7zT/AlJZPyhaE FsIMp1A3YhyKO1GUOz8qay6UVhgMM565j46qptDREyuhWhXCm7rvTYTawykqey4HyrBp iYsSd3Y73XVqY2G88j9J8fPr2J6z8LtucUrMvpCTJIaMsVcV+3v7b7gY2FMLTkA0iX1P ZlwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jGh02B5M1rvfYl69hvxasPDk9iriEgMEUYJWXaLhXmQ=; b=O0WKhRRuxl99vFhICWWt3T8ARLgjw36RGbrnkwos2vacQ09mm5HRK4Du5IYdOpkXvz MUFPmSwRXgxm7AvQC4+IQt8/vJ4keVUP04PqDv3DyShYoiyw1GJ0+9uMFKCCnA8/u6bW 4tFnl8Q7noz41i2layJNGCSEBjeKNVnpNTPbZff54QERroNT+EIzxGVL96qC4ZnYtTuh FFft110j8HOO9L9O8zD2znk/1hMfbK1y3XSJj0VxiNcM8vt9WiiDk6nSSZGwAseccDqP mmzMoX8SyRwoGGHRQwXY5wHaVQuDsdBx8m49kbJRS3dzkutxjdX4Mmng1+2Gc/EEpwlC WVBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=b6+yRp58; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m10si32308434eda.139.2021.01.04.04.24.44; Mon, 04 Jan 2021 04:24:44 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=b6+yRp58; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726846AbhADMYW (ORCPT + 6 others); Mon, 4 Jan 2021 07:24:22 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52830 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726855AbhADMYW (ORCPT ); Mon, 4 Jan 2021 07:24:22 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 104CMfwi092606; Mon, 4 Jan 2021 06:22:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1609762961; bh=jGh02B5M1rvfYl69hvxasPDk9iriEgMEUYJWXaLhXmQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b6+yRp584jslSbjl63Z38w08lNrluEhg754zrrpytqptztfteSKmFE3yP0tFao4ox i+LqwARjRyGFu7DjgMWw98Xyol1JJNK8CQAAwIDku3dld0Ufgd3MIUzk2DaMckiX1G jODYSNcvUDRzJxaxizLYXYAhHymv9WtEhML44cj8= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 104CMfng054773 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Jan 2021 06:22:41 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 4 Jan 2021 06:22:40 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 4 Jan 2021 06:22:40 -0600 Received: from a0393678-ssd.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 104CMZhN002211; Mon, 4 Jan 2021 06:22:38 -0600 From: Kishon Vijay Abraham I To: Nishanth Menon , Rob Herring , Kishon Vijay Abraham I CC: , , Subject: [PATCH v3 1/6] arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions Date: Mon, 4 Jan 2021 17:52:27 +0530 Message-ID: <20210104122232.24071-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210104122232.24071-1-kishon@ti.com> References: <20210104122232.24071-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence IP in J721E supports a maximum of 32 outbound regions. However commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") incorrectly added this as 16 outbound regions. Now that "cdns,max-outbound-regions" is an optional property with default value as 32, remove "cdns,max-outbound-regions" from endpoint DT node. Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b32df591c766..1c11da612c67 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -651,7 +651,6 @@ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -700,7 +699,6 @@ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -749,7 +747,6 @@ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 241 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -798,7 +795,6 @@ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 242 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; From patchwork Mon Jan 4 12:22:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356370 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924401jai; Mon, 4 Jan 2021 04:24:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyG36KB1hb0LzjI/VZJWwbw6fp9bc3Qwl5Lij8lc7hgyCVy+UBeEtJz751WIZ6b88wvd6lN X-Received: by 2002:aa7:cd15:: with SMTP id b21mr64594817edw.114.1609763085842; Mon, 04 Jan 2021 04:24:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609763085; cv=none; d=google.com; s=arc-20160816; b=MF/420UiCD+P4/BGW5ge76XSl38BZDXM2/SmR1zsz6OXwmkV1aJxIvOBGgCJ/yBfYm F5S5AfLvJZUeG5zMfA3gumWoj4eYox/F14LZZqoVxZb5TnBRVCekJ3Uxe3MwdlbbR5z2 iiMPSZ4qd3TKgP+bIU0XLABVKEAcsrOog4bf+yngrP0Jf7ZZkfi+FL/j5UfjD4EUfvPB 4llfwX7Le+rEsrAxCd2SYf+tuDVL8eS6nbIDTkMKMuo4n870URECeeVitOAet0llTY7w 9RyMQuIc0VtEmEw6pAaJJSx9BT/7gj8e3gLZJ8HqCoycYxwuEmMswYhT5RcoCsBJWIUW rSOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=lH1IwpnnOjZmwF8k9RePKE8rDB2DJOszN7HCS1PLkvQ=; b=WBjIF0uRYFHfeOXIHFQ9CK6kUPjPKMkTEImIGPdTWQFXBDo9sx/6ztNs4BSB4qtHU8 EKmY2UQ1u5BRJp/qPHUBstNdmeDU0XBlMxb2wiUVimtVtAmQdHPWONtcDzBBS3l7Ya1n /ZFWgmELe9ha3+6CqPWYEJ7jf8aw51MZXo5/euywsyV6nQ0EiRL6gVG5y8S7ffQzNO07 JKRfoY4gxsSxLDKhvpRRu/fbOwrOJ9Kw0VlQKrwB1UDuGqL0oT7IdXN6TXf2yf2mOIoD 0YwrwWxhn4wNxF084uN6S1ZkLT+yq4TcV1+VjzzFl6W0Jxrjb1ML6D33zc7xqTrG1+IZ DdRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RxNQ2dXK; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m10si32308434eda.139.2021.01.04.04.24.45; Mon, 04 Jan 2021 04:24:45 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RxNQ2dXK; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726855AbhADMYY (ORCPT + 6 others); Mon, 4 Jan 2021 07:24:24 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59424 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726864AbhADMYX (ORCPT ); Mon, 4 Jan 2021 07:24:23 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 104CMipc009258; Mon, 4 Jan 2021 06:22:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1609762964; bh=lH1IwpnnOjZmwF8k9RePKE8rDB2DJOszN7HCS1PLkvQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RxNQ2dXK/fFAKzGFzAbKo4Mb3vzLo4CDaS9OWf3qnVPCbw6+17aQfx2f7MXEFIyHU fp0rjfNXyhKN5gYl7rBSesTAI9k/6co1Z9SrKHxjzO9YWhhw/Okhc3Y2rZrI1jQDC0 HNwBJf5JEeS78suqtLRzfqckUr4fOukg0sai10uE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 104CMi23055740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Jan 2021 06:22:44 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 4 Jan 2021 06:22:43 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 4 Jan 2021 06:22:43 -0600 Received: from a0393678-ssd.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 104CMZhO002211; Mon, 4 Jan 2021 06:22:41 -0600 From: Kishon Vijay Abraham I To: Nishanth Menon , Rob Herring , Kishon Vijay Abraham I CC: , , Subject: [PATCH v3 2/6] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Date: Mon, 4 Jan 2021 17:52:28 +0530 Message-ID: <20210104122232.24071-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210104122232.24071-1-kishon@ti.com> References: <20210104122232.24071-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++------------------- 1 file changed, 8 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 1c11da612c67..2d526ea44a85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,38 +28,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_ctrl: syscon@4070 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4070 0x4070 0x4>; - }; - - pcie1_ctrl: syscon@4074 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4074 0x4074 0x4>; - }; - - pcie2_ctrl: syscon@4078 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4078 0x4078 0x4>; - }; - - pcie3_ctrl: syscon@407c { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0000407c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x407c 0x407c 0x4>; - }; - serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; @@ -618,7 +586,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -645,7 +613,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -666,7 +634,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -693,7 +661,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -714,7 +682,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -741,7 +709,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -762,7 +730,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; @@ -789,7 +757,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; From patchwork Mon Jan 4 12:22:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356368 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924376jai; 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index b0094212aa82..fbe4cd1e6e09 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -5,6 +5,13 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -531,6 +538,62 @@ dma-coherent; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 292 85>; + assigned-clock-parents = <&k3_clks 292 89>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&wiz0_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Jan 4 12:22:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356367 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924369jai; Mon, 4 Jan 2021 04:24:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJwsZi0GC5rqMEmZrfkseAWzm026lorf9PWe9eCqsqbKMhQ51iqciAPvePh0HC2uXkV0WDiL X-Received: by 2002:a05:6402:797:: with SMTP id d23mr70014569edy.302.1609763083315; Mon, 04 Jan 2021 04:24:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609763083; cv=none; d=google.com; s=arc-20160816; b=RQrqaIdvwpvSHi/esp7wqsfrRTIbLW6NQeSJlFNbIwV0HVjvR/bui5gQUmOrUZboRN mpzla6HTOoQdkfoDxpZv585t0oLasdpeLeh9ADcQUMyoVxePtzIGmKbSNjcBtQxPtY1l ACaMVq3zwvKBpGa3nIgoj8TwvXV0+40g0PgdeozyNBbUTFbDgIuuh1Ouj2yAeg1t0p0d 1CCusJ3SuYZFT2CJr/h5y+4SwdRTdiSbwmBsBc4I/HAjo/L+aD7LSQMnuo7lVZ+K5hfv nlONGSMXjaL8z8LAbKrl5Tua2wR4i6rSwSK+TdQZ/81d68HMouG1+XY/iVMvl3N+7uER zEcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=a5c+PysASIVxRTBhsge2AmvKiHMXJJVRD93ZeuiTO60=; b=gVh+udLlmxr/Kxh62EGQFyc7meJNzdlqgUsHjVT3zai0Mnvdb3AU21UDroaFolL5wz PKkuTz6RmyH6sX0mcVG9EE4ojEKeb+105JV1XA6zzS5x/kUVT0ePHvAptIEZvFfw2PWi qcdhAG5B+xewWhjPwu/LMYf2DzkUQNxKcX/NGrytDhpO06sXRB1jNF134BttKyv7Ch+/ U9qDkvY6Ql9VAV9o/K0Ejt9c5fi4dqeIkOSeXmscvZby+T8J8GQV//8+ahtQNyqIcX1h do3W9igSJY/vHF6J+UYRNGy8gvQHRiq7LDeA8CFDt2VkBaQUl4akWgJ7dKArof+afjXH NmkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="s/OguA11"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index fbe4cd1e6e09..4e39f0325c03 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -594,6 +594,54 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Jan 4 12:22:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356371 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924410jai; Mon, 4 Jan 2021 04:24:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJyE5ES2X4ukzjlVS9OFlzwGmZ5y8IQHtiAr/pjViCqieOuPEvNvQQWAPG0AGD2aSlYnhg9+ X-Received: by 2002:a17:906:b08f:: with SMTP id x15mr67034749ejy.36.1609763086642; Mon, 04 Jan 2021 04:24:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609763086; cv=none; d=google.com; s=arc-20160816; b=HSDzxwkqiuqmIbyJlsiHK5KUGF5Dttwb6B3doHYjJZsxM1qJg/K7u8vzQIsErgtQcF TAdnokUu09hooHXxbzXgW8Zre2Z7uD1xT6bVrZDKuN5DLHhYQKyn+LRQ16jVQOoEE8/0 e33Oe8Ly+UPgRGX7AxfBCYtUPoUrX+AyXAFUga+NoTyq1cF9fz/JqlbrsFnkZGhB6a0l xLc356k9Mlx87cgYRGBgEiNuie4M9p8g07TLgmxh33hvcCi0VXbaf+8rfijDCCIOARZD aSi4f0Q4TV4yvqHMeFT7cyxJJl4H1uY3sRJ4k4m1VhAe+vhpekx7kfH+/ClcxWlFDxFi Fs/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TCT4o2ep6cw3Hu4jevsOOwo8iY51in45dTp+iGuuPKs=; b=Hq50Eeh4llj3n40ZeECy94v1HbbOT5tb6QnU0cuSzLAeyhPKtHuw8E1yG6qo6/aSmW NhIVGQsVH4dHOA5+7Qxz3x9qbdFAIB6wa2Qiuhn06Zu/+2NnavcEh1BCx3pf7Ds0wfcM lpuB8hNg5CmXQaAkJkoqZdQKAeNuKZP5fOCfWNqUJkbewxP7TBCZo7nqVVoj9/+UGJjC Yt6uLXOe7YnGCFGQi49PQ2pBcy/GyHHNoJ2kk0QT0e9grHbjK2d8kQO+FdqBsRzPvGqv J75kCZ2o++Lyu16FLCs/F2nEv9BMsSP2nSFq2ohNAwTrWtRP2hX4TTpzNhYwuXvww6T1 HSbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=e6Eu5Nb7; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 331b388e1d1b..def98f563336 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j7200-som-p0.dtsi" #include #include +#include / { chosen { @@ -218,3 +219,25 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_qsgmii_link: phy@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; +}; From patchwork Mon Jan 4 12:22:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 356366 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp14924364jai; Mon, 4 Jan 2021 04:24:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1pX97/W+HE8QpVbMIi6T3CbQFhXtJU39iS7hAfqymDK5VD9+3bRkOkKAaxDVQd/R6u9E4 X-Received: by 2002:a17:907:101c:: with SMTP id ox28mr62739544ejb.201.1609763082960; Mon, 04 Jan 2021 04:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609763082; cv=none; d=google.com; s=arc-20160816; b=poRNC3U891njn3C8D/IlCqkM26Kym5XIDXKRu3R3r6TwkUCE1n/HGtu/Qgluk2Nn8d hK/+SIMwOfdBNcF+9ZXETgAe5FK+Qwh+MTdvUbKxehUlPBKBO+3DPWOd+Hd822o88jKH 8lDX0POrk+sqTazBY5qtWzEGYi2u6O3yJcZcLg5M8CRWP9B4OdaIAVxkF2w1X6DScikv ZPUn8MLMm8r3aPjJEu3KDnfA833khEh2b2Phr75jovTevTrdt4HgFuc69J5OIILVbpth CZ00ww/f4eu7Gk2H2x2ZmWGOKOLkCKKJBWfosWSs9ueAazgDgDNc+4GHEqiUFNXpKi6b mArw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=v8DeDg+aSnj9XDWh6SjoEmvU220d2QLKrD8S48HIXT4=; b=k9MqCQG0bEo1/jhsgsONCTXtdLeLOswjdjgtTmCXrgUJhFBCFBwNP61wDPs4aXJDff 4jgzEFEsCaFSHBZc+9o2e1MLWcj+XlUb6Vkzk3fjYU0bOOXKI42axMz2wruhi99s2oxt JS16I3C1PXN0uCP4AwSf0uH0DJn9lhYAp/DKpTWctaRM3jrgTIuH42LOdL8796v+rMqL hjNbe64qqQFRHy+H6UdIETwECfF0J9iNmeGObISpygXjFh03yjIwAtxttT4aoUwQi9Vp FdKcAaEOSDFHnDGQQLx3VzU2kSCroCgdZzSgd50ahRNu4rsGjAWY9FuCjg7h8hW+dWoC tImg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=haLnkUev; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index def98f563336..4a7182abccf5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include #include #include #include @@ -241,3 +242,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +};