From patchwork Tue Feb 13 17:45:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128287 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4472819ljc; Tue, 13 Feb 2018 09:16:20 -0800 (PST) X-Google-Smtp-Source: AH8x226J4l4DMdgJ03lo1E3JycOlVTTx31TeC8q+GcLt0nFlDhK1hcCTvHjSADlMFeuzVexSrowg X-Received: by 2002:a17:902:7614:: with SMTP id k20-v6mr1727290pll.343.1518542180342; Tue, 13 Feb 2018 09:16:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518542180; cv=none; d=google.com; s=arc-20160816; b=r4yAvAr+oMMGbvrFQPv2TsEnWTsYbJBAiLfQVY27j7GlzkTM6td5sf7Uey3WHDbdxD D/+Deh9XyaQfbo/egdwo0ZUpHV5+1GafznTLNe6GhvFVkfvK4wv7ITIcnHxt0YjcZg/3 01k4JMk/4JokaybV5sZ2ijdoFx7lfD00PldHRZ3cGQAGQuWiuHOMtTej7edAAEnVHh95 4SMP/vYlS8pewfmi1x5TDx/H+IXE52Q4zgjj5vHYMmlDjZK+qsM8zmnVhIZ9F5583oIQ kC0GL46tARUARCXOs+aENdfuZhrzBSxrfMGrYvEamrhIQ2Wq4xQBhK+yamaegDHBCulE VUFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=mlVkmxDw4Klx2/fzuVBKvQGUENVjUWoFKzAqAGli078=; b=hNTbVwoLCK9x2AfF0PrbTajYDLTVqFrxBfkQE/GDFy2RQHQiV9ynrVH+Ws+XSSPaM1 M+2NDUlncYHXzACeEYQKxVWwbMAjhspm6HloywKkG5UJ0sCO5c0wNQlG5phSxrglLwiO XedxC3YKDS6NckYNdUy8WLiPmdRJETo8eD2Wv/eQ5dfuKWov/fVGVgNw63Vl4zypvMtk AgAQu7cBrQAOMQWmNDlHo/g2uEwKnrBUVMyaCmjN/Fa0N54+OwQJOFAFZQfaoUIKNF3x DxGHi4dg8L6NiRR7TAjCajESIjO3iw3VewvxjI9LQ9s8+0tr+C94yeZ9sQRh/i9U7SjX bU3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o13-v6si1144035pli.799.2018.02.13.09.16.20; Tue, 13 Feb 2018 09:16:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935102AbeBMRQQ (ORCPT + 28 others); Tue, 13 Feb 2018 12:16:16 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:5646 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934279AbeBMQ4r (ORCPT ); Tue, 13 Feb 2018 11:56:47 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id DB2A6797A3C5C; Wed, 14 Feb 2018 00:56:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:26 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 1/9] LIB: Introduce a generic PIO mapping method Date: Wed, 14 Feb 2018 01:45:25 +0800 Message-ID: <1518543933-22456-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan In commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and pci_pio_to_address()"), a new I/O space management was supported. With that driver, the I/O ranges configured for PCI/PCIe hosts on some architectures can be mapped to logical PIO, converted easily between CPU address and the corresponding logicial PIO. Based on this, PCI I/O devices can be accessed in a memory read/write way through the unified in/out accessors. But on some archs/platforms, there are bus hosts which access I/O peripherals with host-local I/O port addresses rather than memory addresses after memory-mapped. To support those devices, a more generic I/O mapping method is introduced here. Through this patch, both the CPU addresses and the host-local port can be mapped into the logical PIO space with different logical/fake PIOs. After this, all the I/O accesses to either PCI MMIO devices or host-local I/O peripherals can be unified into the existing I/O accessors defined in asm-generic/io.h and be redirected to the right device-specific hooks based on the input logical PIO. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: John Garry --- include/asm-generic/io.h | 2 + include/linux/logic_pio.h | 131 ++++++++++++++++++++++ lib/Kconfig | 15 +++ lib/Makefile | 2 + lib/logic_pio.c | 272 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 422 insertions(+) create mode 100644 include/linux/logic_pio.h create mode 100644 lib/logic_pio.c -- 1.9.1 diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3..b7996a79 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -351,6 +351,8 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer, #define IO_SPACE_LIMIT 0xffff #endif +#include + /* * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be * implemented on hardware that needs an additional delay for I/O accesses to diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h new file mode 100644 index 0000000..b3322fd --- /dev/null +++ b/include/linux/logic_pio.h @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + */ + +#ifndef __LINUX_LOGIC_PIO_H__ +#define __LINUX_LOGIC_PIO_H__ + +#ifdef __KERNEL__ + +#include + +#define PIO_INDIRECT 0x01UL /* indirect IO flag */ +#define PIO_CPU_MMIO 0x00UL /* memory mapped io flag */ + +struct logic_pio_hwaddr { + struct list_head list; + struct fwnode_handle *fwnode; + resource_size_t hw_start; + resource_size_t io_start; + resource_size_t size; /* range size populated */ + unsigned long flags; + + void *devpara; /* private parameter of the host device */ + struct hostio_ops *ops; /* ops operating on this node */ +}; + +struct hostio_ops { + u32 (*pfin)(void *devobj, unsigned long ptaddr, size_t dlen); + void (*pfout)(void *devobj, unsigned long ptaddr, u32 outval, + size_t dlen); + u32 (*pfins)(void *devobj, unsigned long ptaddr, void *inbuf, + size_t dlen, unsigned int count); + void (*pfouts)(void *devobj, unsigned long ptaddr, + const void *outbuf, size_t dlen, unsigned int count); +}; + +#ifdef CONFIG_INDIRECT_PIO +u8 logic_inb(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +u16 logic_inw(unsigned long addr); +u32 logic_inl(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +void logic_insb(unsigned long addr, void *buffer, unsigned int count); +void logic_insl(unsigned long addr, void *buffer, unsigned int count); +void logic_insw(unsigned long addr, void *buffer, unsigned int count); +void logic_outsb(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsw(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); + +#ifndef inb +#define inb logic_inb +#endif + +#ifndef inw +#define inw logic_inw +#endif + +#ifndef inl +#define inl logic_inl +#endif + +#ifndef outb +#define outb logic_outb +#endif + +#ifndef outw +#define outw logic_outw +#endif + +#ifndef outl +#define outl logic_outl +#endif + +#ifndef insb +#define insb logic_insb +#endif + +#ifndef insw +#define insw logic_insw +#endif + +#ifndef insl +#define insl logic_insl +#endif + +#ifndef outsb +#define outsb logic_outsb +#endif + +#ifndef outsw +#define outsw logic_outsw +#endif + +#ifndef outsl +#define outsl logic_outsl +#endif + +/* + * Below we reserve 0x4000 bytes for Indirect IO as so far this library is only + * used by Hisilicon LPC Host. If needed in future we may reserve a wider IO + * area by redefining the macro below. + */ +#define PIO_INDIRECT_SIZE 0x4000 +#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) +#else +#define MMIO_UPPER_LIMIT IO_SPACE_LIMIT +#endif /* CONFIG_INDIRECT_PIO */ + + +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode); + +unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, + resource_size_t hw_addr, resource_size_t size); + +int logic_pio_register_range(struct logic_pio_hwaddr *newrange); + + +extern resource_size_t logic_pio_to_hwaddr(unsigned long pio); + +extern unsigned long logic_pio_trans_cpuaddr(resource_size_t hw_addr); + +#endif /* __KERNEL__ */ +#endif /* __LINUX_LOGIC_PIO_H__ */ diff --git a/lib/Kconfig b/lib/Kconfig index e960894..7ad1e69 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -55,6 +55,21 @@ config ARCH_USE_CMPXCHG_LOCKREF config ARCH_HAS_FAST_MULTIPLIER bool +config INDIRECT_PIO + bool "Access I/O in non-MMIO mode" + depends on ARM64 + help + On some platforms where no separate I/O space exists, there are I/O + hosts which can not be accessed in MMIO mode. Using the logical PIO + mechanism, the host-local I/O resource can be mapped into system + logic PIO space shared with MMIO hosts, such as PCI/PCIE, then the + system can access the I/O devices with the mapped logic PIO through + I/O accessors. + This way has a relatively little I/O performance cost. Please make + sure your devices really need this configure item enabled. + + When in doubt, say N. + config CRC_CCITT tristate "CRC-CCITT functions" help diff --git a/lib/Makefile b/lib/Makefile index a90d4fc..4a9eacd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -81,6 +81,8 @@ obj-$(CONFIG_HAS_IOMEM) += iomap_copy.o devres.o obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o +obj-y += logic_pio.o + obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o diff --git a/lib/logic_pio.c b/lib/logic_pio.c new file mode 100644 index 0000000..1006d9d --- /dev/null +++ b/lib/logic_pio.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + */ + +#define pr_fmt(fmt) "LOGIC PIO: " fmt + +#include +#include +#include +#include +#include +#include +#include + +/* The unique hardware address list. */ +static LIST_HEAD(io_range_list); +static DEFINE_MUTEX(io_range_mutex); + +/* + * register a new io range node in the io range list. + * + * @newrange: pointer to the io range to be registered. + * + * returns 0 on success, the error code in case of failure + */ +int logic_pio_register_range(struct logic_pio_hwaddr *new_range) +{ + struct logic_pio_hwaddr *range; + int ret = 0; + resource_size_t start = new_range->hw_start; + resource_size_t end = new_range->hw_start + new_range->size; + resource_size_t allocated_mmio_size = 0; + resource_size_t allocated_iio_size = MMIO_UPPER_LIMIT; + + if (!new_range || !new_range->fwnode || !new_range->size) + return -EINVAL; + + mutex_lock(&io_range_mutex); + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == new_range->fwnode) { + /* range already there */ + ret = -EFAULT; + goto end_register; + } + if (range->flags == PIO_CPU_MMIO && + new_range->flags == PIO_CPU_MMIO) { + /* for MMIO ranges we need to check for overlap */ + if (start >= range->hw_start + range->size || + end < range->hw_start) + allocated_mmio_size += range->size; + else { + ret = -EFAULT; + goto end_register; + } + } else if (range->flags == PIO_INDIRECT && + new_range->flags == PIO_INDIRECT) { + allocated_iio_size += range->size; + } + } + + /* range not registered yet, check for available space */ + if (new_range->flags == PIO_CPU_MMIO) { + if (allocated_mmio_size + new_range->size - 1 > + MMIO_UPPER_LIMIT) { + /* if it's too big check if 64K space can be reserved */ + if (allocated_mmio_size + SZ_64K - 1 > + MMIO_UPPER_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->size = SZ_64K; + pr_warn("Requested IO range too big, new size set to 64K\n"); + } + new_range->io_start = allocated_mmio_size; + } else if (new_range->flags == PIO_INDIRECT) { + if (allocated_iio_size + new_range->size - 1 > + IO_SPACE_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->io_start = allocated_iio_size; + } else { + /* invalid flag */ + ret = -EINVAL; + goto end_register; + } + + list_add_tail_rcu(&new_range->list, &io_range_list); + +end_register: + mutex_unlock(&io_range_mutex); + return ret; +} + +/* + * traverse the io_range_list to find the registered node whose device node + * and/or physical IO address match to. + */ +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == fwnode) + return range; + } + return NULL; +} + +/* return a registered range given an input PIO token */ +static struct logic_pio_hwaddr *find_io_range(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (pio >= range->io_start && + pio < range->io_start + range->size) + return range; + } + pr_err("PIO entry token invalid\n"); + return NULL; +} + +/* + * Translate the input logical pio to the corresponding hardware address. + * The input pio should be unique in the whole logical PIO space. + */ +resource_size_t logic_pio_to_hwaddr(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + resource_size_t hwaddr = -1; + + range = find_io_range(pio); + if (range) + hwaddr = range->hw_start + pio - range->io_start; + + return hwaddr; +} + +/* + * This function is generic for translating a hardware address to logical PIO. + * @hw_addr: the hardware address of host, can be CPU address or host-local + * address; + */ +unsigned long +logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, resource_size_t addr, + resource_size_t size) +{ + struct logic_pio_hwaddr *range; + + range = find_io_range_by_fwnode(fwnode); + if (!range || range->flags == PIO_CPU_MMIO) { + pr_err("range not found or invalid\n"); + return -1; + } + if (range->size < size) { + pr_err("resource size %pa cannot fit in IO range size %pa\n", + &size, &range->size); + return -1; + } + return addr - range->hw_start + range->io_start; +} + +unsigned long +logic_pio_trans_cpuaddr(resource_size_t addr) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->flags != PIO_CPU_MMIO) + continue; + if (addr >= range->hw_start && + addr < range->hw_start + range->size) + return addr - range->hw_start + + range->io_start; + } + pr_err("addr not registered in io_range_list\n"); + return -1; +} + +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) +#define BUILD_LOGIC_IO(bw, type) \ +type logic_in##bw(unsigned long addr) \ +{ \ + type ret = -1; \ + \ + if (addr < MMIO_UPPER_LIMIT) { \ + ret = read##bw(PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + ret = entry->ops->pfin(entry->devpara, \ + addr, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ + return ret; \ +} \ + \ +void logic_out##bw(type value, unsigned long addr) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + write##bw(value, PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfout(entry->devpara, \ + addr, value, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} \ + \ +void logic_ins##bw(unsigned long addr, void *buffer, unsigned int count)\ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + reads##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfins(entry->devpara, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ + \ +} \ + \ +void logic_outs##bw(unsigned long addr, const void *buffer, \ + unsigned int count) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + writes##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfouts(entry->devpara, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} + +BUILD_LOGIC_IO(b, u8) + +EXPORT_SYMBOL(logic_inb); +EXPORT_SYMBOL(logic_outb); +EXPORT_SYMBOL(logic_insb); +EXPORT_SYMBOL(logic_outsb); + +BUILD_LOGIC_IO(w, u16) + +EXPORT_SYMBOL(logic_inw); +EXPORT_SYMBOL(logic_outw); +EXPORT_SYMBOL(logic_insw); +EXPORT_SYMBOL(logic_outsw); + +BUILD_LOGIC_IO(l, u32) + +EXPORT_SYMBOL(logic_inl); +EXPORT_SYMBOL(logic_outl); +EXPORT_SYMBOL(logic_insl); +EXPORT_SYMBOL(logic_outsl); +#endif /* CONFIG_INDIRECT_PIO && PCI_IOBASE */ From patchwork Tue Feb 13 17:45:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128253 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4452827ljc; Tue, 13 Feb 2018 08:57:00 -0800 (PST) X-Google-Smtp-Source: AH8x227AJch5z2Ytr/QPwfRpiLqcjVqbW2X4Eo8ywiwyDxEOZLdF7bSmljXYFHNrj5vDvAuFoxI5 X-Received: by 10.101.92.138 with SMTP id a10mr1475160pgt.191.1518541020424; Tue, 13 Feb 2018 08:57:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518541020; cv=none; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id q69si8289122pfa.300.2018.02.13.08.57.00; Tue, 13 Feb 2018 08:57:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965185AbeBMQ4x (ORCPT + 28 others); Tue, 13 Feb 2018 11:56:53 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:5648 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934845AbeBMQ4u (ORCPT ); Tue, 13 Feb 2018 11:56:50 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 285A01B703A54; Wed, 14 Feb 2018 00:56:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:26 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 3/9] PCI: Add fwnode handler as input param of pci_register_io_range() Date: Wed, 14 Feb 2018 01:45:27 +0800 Message-ID: <1518543933-22456-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriele Paoloni In preparation for having the PCI MMIO helpers to use the new generic I/O space management(logical PIO) we need to add the fwnode handler as extra input parameter. This patch changes the signature of pci_register_io_range() and of its callers as needed. Signed-off-by: Gabriele Paoloni Acked-by: Bjorn Helgaas Acked-by: Rob Herring --- drivers/acpi/pci_root.c | 8 +++++--- drivers/of/address.c | 4 +++- drivers/pci/pci.c | 3 ++- include/linux/pci.h | 3 ++- 4 files changed, 12 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 6fc204a..1213479 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -729,7 +729,8 @@ static void acpi_pci_root_validate_resources(struct device *dev, } } -static void acpi_pci_root_remap_iospace(struct resource_entry *entry) +static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode, + struct resource_entry *entry) { #ifdef PCI_IOBASE struct resource *res = entry->res; @@ -738,7 +739,7 @@ static void acpi_pci_root_remap_iospace(struct resource_entry *entry) resource_size_t length = resource_size(res); unsigned long port; - if (pci_register_io_range(cpu_addr, length)) + if (pci_register_io_range(fwnode, cpu_addr, length)) goto err; port = pci_address_to_pio(cpu_addr); @@ -780,7 +781,8 @@ int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info) else { resource_list_for_each_entry_safe(entry, tmp, list) { if (entry->res->flags & IORESOURCE_IO) - acpi_pci_root_remap_iospace(entry); + acpi_pci_root_remap_iospace(&device->fwnode, + entry); if (entry->res->flags & IORESOURCE_DISABLED) resource_list_destroy_entry(entry); diff --git a/drivers/of/address.c b/drivers/of/address.c index ce4d3d8..cdf047b 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -2,6 +2,7 @@ #define pr_fmt(fmt) "OF: " fmt #include +#include #include #include #include @@ -333,7 +334,8 @@ int of_pci_range_to_resource(struct of_pci_range *range, if (res->flags & IORESOURCE_IO) { unsigned long port; - err = pci_register_io_range(range->cpu_addr, range->size); + err = pci_register_io_range(&np->fwnode, range->cpu_addr, + range->size); if (err) goto invalid_range; port = pci_address_to_pio(range->cpu_addr); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4666a01..07290a3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3455,7 +3455,8 @@ struct io_range { * Record the PCI IO range (expressed as CPU physical address + size). * Return a negative value if an error has occured, zero otherwise */ -int pci_register_io_range(phys_addr_t addr, resource_size_t size) +int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, + resource_size_t size) { int err = 0; diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1be..be686fd 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1226,7 +1226,8 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, void *alignf_data); -int pci_register_io_range(phys_addr_t addr, resource_size_t size); +int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, + resource_size_t size); unsigned long pci_address_to_pio(phys_addr_t addr); phys_addr_t pci_pio_to_address(unsigned long pio); int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); From patchwork Tue Feb 13 17:45:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128254 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4452933ljc; Tue, 13 Feb 2018 08:57:05 -0800 (PST) X-Google-Smtp-Source: AH8x225rIm0CdwUiaurETQTY1EAzxbJDIWQAwGRqmaLoRG2HcK87SXtel5IODNR474sPAKVc6D2P X-Received: by 10.98.138.129 with SMTP id o1mr1883514pfk.182.1518541025383; Tue, 13 Feb 2018 08:57:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518541025; cv=none; d=google.com; s=arc-20160816; b=J1tUoW/gkDuKisvdkO/dTHqWYMEbksmNauAMG+/OE452gaDlb4pQStPXRan/0e0QsR CS7/2txfJUhkKZGidfc1lqKHt1s6LKDr+hpG9wGcHSrxRI96l2Xjwe6Dct/EVhzAsCMo zeDQ0eq5XzaVLnlhxYjteXqdy8zi+sIQxWVhuUzJnZb0C9s7hhaw+XJKL3Qobfn5Wq7L n1zci7TyQWbN2Z+4qGtuTG5VkNAWxa+hb6B5hL5+XZYT3EO80VKN2B4TqC4T7s5E/RP+ j+8OjVpIsX9QCnuJ88sOXHXIQg8iXhHwAYiG+72tFL/gNEekPktR+jGDNV5YmXCu/fKE otLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=uRS7Cg60OutKaL4zKnjI6lYkA/kAsEsxpV5jvIGymMg=; b=CSwe4gGZl/o5+0UtstJYq/n0EWOE/HP0TA5ogB20YWAVyw1rGxQujLihIBYiYNIf1b 0z8CLTBI78S3n9MuD0Tg5c7a3nv1MQK/LO9grI7pWrY7NS78a4ynllx+xTw7xQrkBNDT hu2AgkF5updxsosPD4bgIr90Y5FqWvezcdevsr+HsN+Kare/A+WHw3+Z3Q/b9m7D1E87 Tm2h5lUunAt+tHhopzMWmF0JjnHG4SXvs5f0zU2idqXMmHB+io3gKEluZp7nJzxqsQ6q AWZGU+q5Ox3qswerXjnq67/OfT/x6J89slz2hA9Cd5IBUtKSLj6sp7mn8ToZk7cqfOgz 0NTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m8si1180703pgu.551.2018.02.13.08.57.05; Tue, 13 Feb 2018 08:57:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965221AbeBMQ46 (ORCPT + 28 others); Tue, 13 Feb 2018 11:56:58 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5236 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934962AbeBMQ4x (ORCPT ); Tue, 13 Feb 2018 11:56:53 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 77E49182AF831; Wed, 14 Feb 2018 00:56:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:27 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 4/9] PCI: Apply the new generic I/O management on PCI IO hosts Date: Wed, 14 Feb 2018 01:45:28 +0800 Message-ID: <1518543933-22456-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan After introducing the new generic I/O space management in logic pio, the original PCI MMIO relevant helpers need to be updated based on the new interfaces. This patch adapts the corresponding code to match the changes introduced by logic pio. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Bjorn Helgaas --- drivers/pci/pci.c | 95 +++++++++--------------------------------------- include/asm-generic/io.h | 2 +- 2 files changed, 18 insertions(+), 79 deletions(-) -- 1.9.1 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 07290a3..8aa5c54 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -3440,17 +3441,6 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) } EXPORT_SYMBOL(pci_request_regions_exclusive); -#ifdef PCI_IOBASE -struct io_range { - struct list_head list; - phys_addr_t start; - resource_size_t size; -}; - -static LIST_HEAD(io_range_list); -static DEFINE_SPINLOCK(io_range_lock); -#endif - /* * Record the PCI IO range (expressed as CPU physical address + size). * Return a negative value if an error has occured, zero otherwise @@ -3458,51 +3448,28 @@ struct io_range { int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, resource_size_t size) { - int err = 0; - + int ret = 0; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - /* check if the range hasn't been previously recorded */ - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (addr >= range->start && addr + size <= range->start + size) { - /* range already registered, bail out */ - goto end_register; - } - allocated_size += range->size; - } + struct logic_pio_hwaddr *range; - /* range not registed yet, check for available space */ - if (allocated_size + size - 1 > IO_SPACE_LIMIT) { - /* if it's too big check if 64K space can be reserved */ - if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { - err = -E2BIG; - goto end_register; - } - - size = SZ_64K; - pr_warn("Requested IO range too big, new size set to 64K\n"); - } + if (!size || addr + size < addr) + return -EINVAL; - /* add the range to the list */ range = kzalloc(sizeof(*range), GFP_ATOMIC); - if (!range) { - err = -ENOMEM; - goto end_register; - } + if (!range) + return -ENOMEM; - range->start = addr; + range->fwnode = fwnode; range->size = size; + range->hw_start = addr; + range->flags = PIO_CPU_MMIO; - list_add_tail(&range->list, &io_range_list); - -end_register: - spin_unlock(&io_range_lock); + ret = logic_pio_register_range(range); + if (ret) + kfree(range); #endif - return err; + return ret; } phys_addr_t pci_pio_to_address(unsigned long pio) @@ -3510,21 +3477,10 @@ phys_addr_t pci_pio_to_address(unsigned long pio) phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - if (pio > IO_SPACE_LIMIT) + if (pio >= MMIO_UPPER_LIMIT) return address; - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (pio >= allocated_size && pio < allocated_size + range->size) { - address = range->start + pio - allocated_size; - break; - } - allocated_size += range->size; - } - spin_unlock(&io_range_lock); + address = logic_pio_to_hwaddr(pio); #endif return address; @@ -3533,25 +3489,8 @@ phys_addr_t pci_pio_to_address(unsigned long pio) unsigned long __weak pci_address_to_pio(phys_addr_t address) { #ifdef PCI_IOBASE - struct io_range *res; - resource_size_t offset = 0; - unsigned long addr = -1; - - spin_lock(&io_range_lock); - list_for_each_entry(res, &io_range_list, list) { - if (address >= res->start && address < res->start + res->size) { - addr = address - res->start + offset; - break; - } - offset += res->size; - } - spin_unlock(&io_range_lock); - - return addr; + return logic_pio_trans_cpuaddr(address); #else - if (address > IO_SPACE_LIMIT) - return (unsigned long)-1; - return (unsigned long) address; #endif } diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b7996a79..5a59931 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -901,7 +901,7 @@ static inline void iounmap(void __iomem *addr) #define ioport_map ioport_map static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { - return PCI_IOBASE + (port & IO_SPACE_LIMIT); + return PCI_IOBASE + (port & MMIO_UPPER_LIMIT); } #endif From patchwork Tue Feb 13 17:45:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128259 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4454783ljc; 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[209.132.180.67]) by mx.google.com with ESMTP id q24si2697523pff.249.2018.02.13.08.59.26; Tue, 13 Feb 2018 08:59:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965219AbeBMQ7B (ORCPT + 28 others); Tue, 13 Feb 2018 11:59:01 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5233 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934677AbeBMQ4w (ORCPT ); Tue, 13 Feb 2018 11:56:52 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 297FA1A4AE7AD; Wed, 14 Feb 2018 00:56:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:27 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 5/9] OF: Add missing I/O range exception for indirect-IO devices Date: Wed, 14 Feb 2018 01:45:29 +0800 Message-ID: <1518543933-22456-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan There are some special ISA/LPC devices that work on a specific I/O range where it is not correct to specify a 'ranges' property in DTS parent node as cpu addresses translated from DTS node are only for memory space on some architectures, such as Arm64. Without the parent 'ranges' property, current of_translate_address() return an error. Here we add special handlings for this case. During the OF address translation, some checkings will be perfromed to identify whether the device node is registered as indirect-IO. If yes, the I/O translation will be done in a different way from that one of PCI MMIO. In this way, the I/O 'reg' property of the special ISA/LPC devices will be parsed correctly. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Rob Herring --- drivers/of/address.c | 92 +++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 76 insertions(+), 16 deletions(-) -- 1.9.1 diff --git a/drivers/of/address.c b/drivers/of/address.c index cdf047b..2db8b56 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -562,9 +563,14 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus, * that translation is impossible (that is we are not dealing with a value * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things + * + * Whenever the translation fails, the *host pointer will be set to the + * device that had registered logical PIO mapping, and the return code is + * relative to that node. */ static u64 __of_translate_address(struct device_node *dev, - const __be32 *in_addr, const char *rprop) + const __be32 *in_addr, const char *rprop, + struct device_node **host) { struct device_node *parent = NULL; struct of_bus *bus, *pbus; @@ -577,6 +583,7 @@ static u64 __of_translate_address(struct device_node *dev, /* Increase refcount at current level */ of_node_get(dev); + *host = NULL; /* Get parent & match bus type */ parent = of_get_parent(dev); if (parent == NULL) @@ -597,6 +604,8 @@ static u64 __of_translate_address(struct device_node *dev, /* Translate */ for (;;) { + struct logic_pio_hwaddr *iorange; + /* Switch to parent bus */ of_node_put(dev); dev = parent; @@ -609,6 +618,19 @@ static u64 __of_translate_address(struct device_node *dev, break; } + /* + * For indirectIO device which has no ranges property, get + * the address from reg directly. + */ + iorange = find_io_range_by_fwnode(&dev->fwnode); + if (iorange && (iorange->flags != PIO_CPU_MMIO)) { + result = of_read_number(addr + 1, na - 1); + pr_debug("indirectIO matched(%s) 0x%llx\n", + of_node_full_name(dev), result); + *host = of_node_get(dev); + break; + } + /* Get new parent bus and counts */ pbus = of_match_bus(parent); pbus->count_cells(dev, &pna, &pns); @@ -640,13 +662,32 @@ static u64 __of_translate_address(struct device_node *dev, u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) { - return __of_translate_address(dev, in_addr, "ranges"); + struct device_node *host; + u64 ret; + + ret = __of_translate_address(dev, in_addr, "ranges", &host); + if (host) { + of_node_put(host); + return OF_BAD_ADDR; + } + + return ret; } EXPORT_SYMBOL(of_translate_address); u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) { - return __of_translate_address(dev, in_addr, "dma-ranges"); + struct device_node *host; + u64 ret; + + ret = __of_translate_address(dev, in_addr, "dma-ranges", &host); + + if (host) { + of_node_put(host); + return OF_BAD_ADDR; + } + + return ret; } EXPORT_SYMBOL(of_translate_dma_address); @@ -688,29 +729,48 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, } EXPORT_SYMBOL(of_get_address); +static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr, + u64 size) +{ + u64 taddr; + unsigned long port; + struct device_node *host; + + taddr = __of_translate_address(dev, in_addr, "ranges", &host); + if (host) { + /* host specific port access */ + port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size); + of_node_put(host); + } else { + /* memory mapped I/O range */ + port = pci_address_to_pio(taddr); + } + + if (port == (unsigned long)-1) + return OF_BAD_ADDR; + + return port; +} + static int __of_address_to_resource(struct device_node *dev, const __be32 *addrp, u64 size, unsigned int flags, const char *name, struct resource *r) { u64 taddr; - if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) + if (flags & IORESOURCE_MEM) + taddr = of_translate_address(dev, addrp); + else if (flags & IORESOURCE_IO) + taddr = of_translate_ioport(dev, addrp, size); + else return -EINVAL; - taddr = of_translate_address(dev, addrp); + if (taddr == OF_BAD_ADDR) return -EINVAL; memset(r, 0, sizeof(struct resource)); - if (flags & IORESOURCE_IO) { - unsigned long port; - port = pci_address_to_pio(taddr); - if (port == (unsigned long)-1) - return -EINVAL; - r->start = port; - r->end = port + size - 1; - } else { - r->start = taddr; - r->end = taddr + size - 1; - } + + r->start = taddr; + r->end = taddr + size - 1; r->flags = flags; r->name = name ? name : dev->full_name; From patchwork Tue Feb 13 17:45:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128256 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4453456ljc; Tue, 13 Feb 2018 08:57:46 -0800 (PST) X-Google-Smtp-Source: AH8x224X8JA0+Jaxcs+D5hHFH5rKM1bwAV9gHL0BK/P3O00uv+rxsyYcFlyhzfpGdYUffREsnOIQ X-Received: by 10.99.95.81 with SMTP id t78mr1510241pgb.380.1518541066236; Tue, 13 Feb 2018 08:57:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518541066; cv=none; d=google.com; s=arc-20160816; b=Z3ds676sEpDU4cZruI5fgC5n8ZrtP0pSqDOFinm1RP2YTSkgG8GtU5XjZAJiwS9ePM qzvqFAlygG5cNylkpRAvdfE/ACqKc9flzwWLMMQWBCjdq3VrK8oVxN+MJMWrCvbLRyQq RRIn5Rtnebb1Yb9ICJz4edR1n88/MvDM7YzGCTglivK7zBm8gjq7tiHE0Tt/GCNmcocg uMKW8ffzSXTlQpqNWUrQT1WRGJgzJXMyR7VOEW4+hcixnBj/WRfhuqdBEuMLBdDMKpKw MMKIFnEFkvnyz1x+N3usj5ai9b+FE7leoavTdJE4Us4LpH1XyQhWzQ/7b9i8UIMku2Np +wsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3lW/hvvcJZiXUCfCfsfFtsC769IJrg0tfWT4JinOak4=; b=hBbVSpSAht+5qeHY6S9+gz/DkHofm7Dm3uYAV1a/XGFkbubwkW0hsWefM/QUVP69qW t6Y6uGFtYdguQfXAsmAPHVoMLLDXrFvbrLzoN7uqbTZyLcnZ/+ZRft63nUh3FN6kd/WN VBUJcp+piuPcJrkB6sC8iY/bnQQkB0rrx/ZhmyBFvtqvCailGwYaadiLZ1pKRjhdQ/or AOFSfjI2Ec8FknbZg+nK1dJakK426kTdC+QQ/YInLRhXNxjhVDW6O22zsc9BNcjQO6WR yRd2CKecLw9s+npgMsS4vZbf+FeL6pCGgPI1QQA66h6rfBYG3MFrQCiCJk5tV2rJtJpV fKLQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v67si128376pfj.77.2018.02.13.08.57.45; Tue, 13 Feb 2018 08:57:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965288AbeBMQ5Z (ORCPT + 28 others); Tue, 13 Feb 2018 11:57:25 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5232 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934943AbeBMQ4w (ORCPT ); Tue, 13 Feb 2018 11:56:52 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 13904E2BAC814; Wed, 14 Feb 2018 00:56:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:28 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 7/9] ACPI: Translate the I/O range of non-MMIO devices before scanning Date: Wed, 14 Feb 2018 01:45:31 +0800 Message-ID: <1518543933-22456-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some platforms (such as arm64-based hip06/hip07), access to legacy ISA/LPC devices through access IO space is required, similar to x86 platforms. As the I/O for these devices are not memory mapped like PCI/PCIE MMIO host bridges, they require special low-level device operations through some host to generate IO accesses, i.e. a non- transparent bridge. Through the logical PIO framework, hosts are able to register address ranges in the logical PIO space for IO accesses. For hosts which require a LLDD to generate the IO accesses, through the logical PIO framework the host also registers accessors as a backend to generate the physical bus transactions for IO space accesses (called indirect IO). When describing the indirect IO child device in APCI tables, the IO resource is the host-specific address for the child (generally a bus address). An example is as follows: Device (LPC0) { Name (_HID, "HISI0191") // HiSi LPC Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) }) } Device (LPC0.IPMI) { Name (_HID, "IPI0001") Name (LORS, ResourceTemplate() { QWordIO ( ResourceConsumer, MinNotFixed, // _MIF MaxNotFixed, // _MAF PosDecode, EntireRange, 0x0, // _GRA 0xe4, // _MIN 0x3fff, // _MAX 0x0, // _TRA 0x04, // _LEN , , BTIO ) }) Since the IO resource for the child is a host-specific address, special translation are required to retrieve the logical PIO address for that child. To overcome the problem of associating this logical PIO address with the child device, a scan handler is added to scan the ACPI namespace for known indirect IO hosts. This scan handler creates an MFD per child with the translated logical PIO address as it's IO resource, as a substitute for the normal platform device which ACPI would create during device enumeration. Signed-off-by: John Garry Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni --- drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/acpi_indirectio.c | 250 +++++++++++++++++++++++++++++++++++ drivers/acpi/internal.h | 5 + drivers/acpi/scan.c | 1 + 4 files changed, 257 insertions(+) create mode 100644 drivers/acpi/arm64/acpi_indirectio.c -- 1.9.1 Acked-by: Rafael J. Wysocki diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile index 1017def..f4a7f46 100644 --- a/drivers/acpi/arm64/Makefile +++ b/drivers/acpi/arm64/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ACPI_IORT) += iort.o obj-$(CONFIG_ACPI_GTDT) += gtdt.o +obj-$(CONFIG_INDIRECT_PIO) += acpi_indirectio.o diff --git a/drivers/acpi/arm64/acpi_indirectio.c b/drivers/acpi/arm64/acpi_indirectio.c new file mode 100644 index 0000000..51a1b92 --- /dev/null +++ b/drivers/acpi/arm64/acpi_indirectio.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 HiSilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * Author: John Garry + * + * This file implements functunality to scan the ACPI namespace and config + * devices under "indirect IO" hosts. An "indirect IO" host allows child + * devices to use logical IO accesses when the host, itself, does not provide + * a transparent bridge. The device setup creates a per-child MFD with a + * logical port IO resource. + */ + +#include +#include +#include +#include + +ACPI_MODULE_NAME("indirect IO"); + +#define ACPI_INDIRECT_IO_NAME_LEN 255 + +struct acpi_indirect_io_mfd_cell { + struct mfd_cell_acpi_match acpi_match; + char name[ACPI_INDIRECT_IO_NAME_LEN]; + char pnpid[ACPI_INDIRECT_IO_NAME_LEN]; +}; + +static int acpi_indirect_io_xlat_res(struct acpi_device *adev, + struct acpi_device *host, + struct resource *res) +{ + unsigned long sys_port; + resource_size_t len = res->end - res->start; + + sys_port = logic_pio_trans_hwaddr(&host->fwnode, res->start, len); + if (sys_port == -1UL) + return -EFAULT; + + res->start = sys_port; + res->end = sys_port + len; + + return 0; +} + +/* + * acpi_indirect_io_set_res - set the resources for a child device + * (MFD) of an "indirect IO" host. + * @child: the device node to be updated the I/O resource + * @hostdev: the device node associated with the "indirect IO" host + * @res: double pointer to be set to the address of translated resources + * @num_res: pointer to variable to hold the number of translated resources + * + * Returns 0 when successful, and a negative value for failure. + * + * For a given "indirect IO" host, each child device will have associated + * host-relevative address resource. This function will return the translated + * logical PIO addresses for each child devices resources. + */ +static int acpi_indirect_io_set_res(struct device *child, + struct device *hostdev, + const struct resource **res, + int *num_res) +{ + struct acpi_device *adev; + struct acpi_device *host; + struct resource_entry *rentry; + LIST_HEAD(resource_list); + struct resource *resources; + int count; + int i; + int ret = -EIO; + + if (!child || !hostdev) + return -EINVAL; + + host = to_acpi_device(hostdev); + adev = to_acpi_device(child); + + /* check the device state */ + if (!adev->status.present) { + dev_info(child, "device is not present\n"); + return 0; + } + /* whether the child had been enumerated? */ + if (acpi_device_enumerated(adev)) { + dev_info(child, "had been enumerated\n"); + return 0; + } + + count = acpi_dev_get_resources(adev, &resource_list, NULL, NULL); + if (count <= 0) { + dev_err(child, "failed to get resources\n"); + return count ? count : -EIO; + } + + resources = kcalloc(count, sizeof(*resources), GFP_KERNEL); + if (!resources) { + acpi_dev_free_resource_list(&resource_list); + return -ENOMEM; + } + count = 0; + list_for_each_entry(rentry, &resource_list, node) + resources[count++] = *rentry->res; + + acpi_dev_free_resource_list(&resource_list); + + /* translate the I/O resources */ + for (i = 0; i < count; i++) { + if (!(resources[i].flags & IORESOURCE_IO)) + continue; + ret = acpi_indirect_io_xlat_res(adev, host, &resources[i]); + if (ret) { + kfree(resources); + dev_err(child, "translate IO range failed(%d)\n", ret); + return ret; + } + } + *res = resources; + *num_res = count; + + return ret; +} + +/* + * acpi_indirect_io_setup - scan handler for "indirect IO" host. + * @adev: "indirect IO" host ACPI device pointer + * Returns 0 when successful, and a negative value for failure. + * + * Setup an "indirect IO" host by scanning all child devices, and + * create a per-device MFD with logical PIO translated IO resources. + */ +static int acpi_indirect_io_setup(struct acpi_device *adev) +{ + struct platform_device *pdev; + struct mfd_cell *mfd_cells; + struct logic_pio_hwaddr *range; + struct acpi_device *child; + struct acpi_indirect_io_mfd_cell *acpi_indirect_io_mfd_cells; + int size, ret, count = 0, cell_num = 0; + + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (!range) + return -ENOMEM; + range->fwnode = &adev->fwnode; + range->flags = PIO_INDIRECT; + range->size = PIO_INDIRECT_SIZE; + + ret = logic_pio_register_range(range); + if (ret) + goto free_range; + + list_for_each_entry(child, &adev->children, node) + cell_num++; + + /* allocate the mfd cell and companion acpi info, one per child */ + size = sizeof(*mfd_cells) + sizeof(*acpi_indirect_io_mfd_cells); + mfd_cells = kcalloc(cell_num, size, GFP_KERNEL); + if (!mfd_cells) { + ret = -ENOMEM; + goto free_range; + } + + acpi_indirect_io_mfd_cells = (struct acpi_indirect_io_mfd_cell *) + &mfd_cells[cell_num]; + /* Only consider the children of the host */ + list_for_each_entry(child, &adev->children, node) { + struct mfd_cell *mfd_cell = &mfd_cells[count]; + struct acpi_indirect_io_mfd_cell *acpi_indirect_io_mfd_cell = + &acpi_indirect_io_mfd_cells[count]; + const struct mfd_cell_acpi_match *acpi_match = + &acpi_indirect_io_mfd_cell->acpi_match; + char *name = &acpi_indirect_io_mfd_cell[count].name[0]; + char *pnpid = &acpi_indirect_io_mfd_cell[count].pnpid[0]; + struct mfd_cell_acpi_match match = { + .pnpid = pnpid, + }; + + snprintf(name, ACPI_INDIRECT_IO_NAME_LEN, "indirect-io-%s", + acpi_device_hid(child)); + snprintf(pnpid, ACPI_INDIRECT_IO_NAME_LEN, "%s", + acpi_device_hid(child)); + + memcpy((void *)acpi_match, (void *)&match, sizeof(*acpi_match)); + mfd_cell->name = name; + mfd_cell->acpi_match = acpi_match; + + ret = acpi_indirect_io_set_res(&child->dev, &adev->dev, + &mfd_cell->resources, + &mfd_cell->num_resources); + if (ret) { + dev_err(&child->dev, "set resource failed (%d)\n", ret); + goto free_mfd_resources; + } + count++; + } + + pdev = acpi_create_platform_device(adev, NULL); + if (IS_ERR_OR_NULL(pdev)) { + dev_err(&adev->dev, "create platform device for host failed\n"); + ret = PTR_ERR(pdev); + goto free_mfd_resources; + } + acpi_device_set_enumerated(adev); + + ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, + mfd_cells, cell_num, NULL, 0, NULL); + if (ret) { + dev_err(&pdev->dev, "failed to add mfd cells (%d)\n", ret); + goto free_mfd_resources; + } + + return ret; + +free_mfd_resources: + while (cell_num--) + kfree(mfd_cells[cell_num].resources); + kfree(mfd_cells); +free_range: + kfree(range); + + return ret; +} + +/* All the host devices which apply indirect-IO can be listed here. */ +static const struct acpi_device_id acpi_indirect_io_host_id[] = { + {} +}; + +static int acpi_indirect_io_attach(struct acpi_device *adev, + const struct acpi_device_id *id) +{ + int ret = acpi_indirect_io_setup(adev); + + if (ret < 0) + return ret; + + return 1; +} + +static struct acpi_scan_handler acpi_indirect_io_handler = { + .ids = acpi_indirect_io_host_id, + .attach = acpi_indirect_io_attach, +}; + +void __init acpi_indirect_io_scan_init(void) +{ + acpi_scan_add_handler(&acpi_indirect_io_handler); +} diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h index 1d0a501..680f3cf 100644 --- a/drivers/acpi/internal.h +++ b/drivers/acpi/internal.h @@ -31,6 +31,11 @@ void acpi_platform_init(void); void acpi_pnp_init(void); void acpi_int340x_thermal_init(void); +#ifdef CONFIG_INDIRECT_PIO +void acpi_indirect_io_scan_init(void); +#else +static inline void acpi_indirect_io_scan_init(void) {} +#endif #ifdef CONFIG_ARM_AMBA void acpi_amba_init(void); #else diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 8e63d93..204da8a 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2155,6 +2155,7 @@ int __init acpi_scan_init(void) acpi_amba_init(); acpi_watchdog_init(); acpi_init_lpit(); + acpi_indirect_io_scan_init(); acpi_scan_add_handler(&generic_device_handler); From patchwork Tue Feb 13 17:45:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128258 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4454186ljc; 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[209.132.180.67]) by mx.google.com with ESMTP id m3-v6si7670217pld.358.2018.02.13.08.58.41; Tue, 13 Feb 2018 08:58:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965236AbeBMQ5T (ORCPT + 28 others); Tue, 13 Feb 2018 11:57:19 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5237 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934845AbeBMQ44 (ORCPT ); Tue, 13 Feb 2018 11:56:56 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 65A9BFB41FF87; Wed, 14 Feb 2018 00:56:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:28 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 8/9] LPC, ACPI: Add the HISI LPC ACPI support Date: Wed, 14 Feb 2018 01:45:32 +0800 Message-ID: <1518543933-22456-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Based on the previous patches, this patch supports the LPC host on Hip06/Hip07 for ACPI FW. Signed-off-by: John Garry Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Tested-by: Dann Frazier --- drivers/acpi/arm64/acpi_indirectio.c | 1 + drivers/bus/hisi_lpc.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/acpi/arm64/acpi_indirectio.c b/drivers/acpi/arm64/acpi_indirectio.c index 51a1b92..52519a21 100644 --- a/drivers/acpi/arm64/acpi_indirectio.c +++ b/drivers/acpi/arm64/acpi_indirectio.c @@ -225,6 +225,7 @@ static int acpi_indirect_io_setup(struct acpi_device *adev) /* All the host devices which apply indirect-IO can be listed here. */ static const struct acpi_device_id acpi_indirect_io_host_id[] = { + {"HISI0191"}, {} }; diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c index 2290cf2..6211c95 100644 --- a/drivers/bus/hisi_lpc.c +++ b/drivers/bus/hisi_lpc.c @@ -439,7 +439,13 @@ static int hisilpc_probe(struct platform_device *pdev) } /* register the LPC host PIO resources */ - { + if (has_acpi_companion(dev)) { + lpcdev->io_host = find_io_range_by_fwnode(dev->fwnode); + if (!lpcdev->io_host) { + dev_err(dev, "range not registered!\n"); + return -EFAULT; + } + } else { struct logic_pio_hwaddr *range; range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); @@ -496,10 +502,19 @@ static int hisilpc_probe(struct platform_device *pdev) {}, }; +#ifdef CONFIG_ACPI +static const struct acpi_device_id hisilpc_acpi_match[] = { + {"HISI0191", }, + {}, +}; + +#endif + static struct platform_driver hisilpc_driver = { .driver = { .name = "hisi_lpc", .of_match_table = hisilpc_of_match, + .acpi_match_table = ACPI_PTR(hisilpc_acpi_match), }, .probe = hisilpc_probe, }; From patchwork Tue Feb 13 17:45:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 128257 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4453581ljc; Tue, 13 Feb 2018 08:57:56 -0800 (PST) X-Google-Smtp-Source: AH8x22482+tTYy+HdfK3U6F2Jcp1xZX67ugGjW4UZfvUNsBgPvMWycCPy0wkAvXWMMzGpV6AOj2O X-Received: by 10.101.69.13 with SMTP id n13mr1506362pgq.62.1518541076244; Tue, 13 Feb 2018 08:57:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518541076; cv=none; d=google.com; s=arc-20160816; b=QRH9GuA2aGCSakNan4TAceG6dbNNHULKO2rQqLs4CYSvB0D/XXjFnJImk8lfH6NyK9 IJm9QawHcec39VV1JkdP1gZjApPfymHCjHpa/CzEymWV00vIDCkiVHjI4ST3/3PfpS7t sBwzg/sIl5YjT7IvGkH73xGAcfMkYbzZIJsLCD+vipnGbbLLxO5Rtzxv82ZDchej5eho nRWtrJblPmklNSw/anaXSVLSkFUa4Yrr5gN0Qk+AAEDQvZdPJrxMw7TKXbepKybnpB+x 2foXAZ4UdlnZasp3mHZwdH+nmDrXr0Ng6rbcz/MIRgBevwvy+hbeL5wgDmREDUCgRC89 n1XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=v8v7sEbP+nTIX2VI8Ijuh+EanW8sp/F0OgF/6dRAc+I=; b=SmoGzdpSee3mJwlJpJEbZ3D+7kjCI6L2SV/zxJ3PGA+aaw69WJYnHpLpuqJ8G7Ugox kPexyznVg1736hnlOwaB0s5Yab2WiuPAkuY//R87w/IWopnxHPXv7L0QnqVi44LNpgHc jok4jAGq/ZQGmkixJ4y/gZMueGbrnX+ASOglFY48P/H2K/qwX3TgPwIaqzt58gRH4J0g 3QmzYXgaTi6F82GV9wgRkwn26rsSGTzlCPJ3CVXbOu0//c3gYlshXyKQOPlQjtU5WVUC h97KJvrwG/LSPhiI4VGrghP3hrmUkySrDDxQ3NhIqh7ivKOOljfmvn1JQv+sIy6V4DE+ 8aOg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v67si128376pfj.77.2018.02.13.08.57.55; Tue, 13 Feb 2018 08:57:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965018AbeBMQ5W (ORCPT + 28 others); Tue, 13 Feb 2018 11:57:22 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:5235 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934950AbeBMQ4w (ORCPT ); Tue, 13 Feb 2018 11:56:52 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 53BF715A680D8; Wed, 14 Feb 2018 00:56:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Wed, 14 Feb 2018 00:56:29 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v13 9/9] MAINTAINERS: Add maintainer for HiSilicon LPC driver Date: Wed, 14 Feb 2018 01:45:33 +0800 Message-ID: <1518543933-22456-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518543933-22456-1-git-send-email-john.garry@huawei.com> References: <1518543933-22456-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added maintainer for drivers/bus/hisi_lpc.c Signed-off-by: John Garry --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) -- 1.9.1 diff --git a/MAINTAINERS b/MAINTAINERS index fc538a9..9a2fe10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6386,6 +6386,13 @@ W: http://www.hisilicon.com S: Maintained F: drivers/net/ethernet/hisilicon/hns3/ +HISILICON LPC BUS DRIVER +M: john.garry@huawei.com +W: http://www.hisilicon.com +S: Maintained +F: drivers/bus/hisi_lpc.c +F: Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt + HISILICON NETWORK SUBSYSTEM DRIVER M: Yisen Zhuang M: Salil Mehta