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[213.113.116.203]) by smtp.gmail.com with ESMTPSA id l13sm1539318lfi.35.2018.02.12.13.42.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Feb 2018 13:42:27 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij Subject: [PATCH] gpio: ftgpio010: Fix some more registers Date: Mon, 12 Feb 2018 22:40:23 +0100 Message-Id: <20180212214023.6873-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org There is a register for "bypass" which seems to not be used for anything in some silicon designs, but may be used in others, and there is both a raw and masked interrupt status register. Define them all for clarity, no semantic changes. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ftgpio010.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/gpio-ftgpio010.c b/drivers/gpio/gpio-ftgpio010.c index b7a3a2db699b..e80634c464a9 100644 --- a/drivers/gpio/gpio-ftgpio010.c +++ b/drivers/gpio/gpio-ftgpio010.c @@ -21,12 +21,14 @@ #define GPIO_DATA_OUT 0x00 #define GPIO_DATA_IN 0x04 #define GPIO_DIR 0x08 +#define GPIO_BYPASS_IN 0x0C #define GPIO_DATA_SET 0x10 #define GPIO_DATA_CLR 0x14 #define GPIO_PULL_EN 0x18 #define GPIO_PULL_TYPE 0x1C #define GPIO_INT_EN 0x20 -#define GPIO_INT_STAT 0x24 +#define GPIO_INT_STAT_RAW 0x24 +#define GPIO_INT_STAT_MASKED 0x28 #define GPIO_INT_MASK 0x2C #define GPIO_INT_CLR 0x30 #define GPIO_INT_TYPE 0x34 @@ -147,7 +149,7 @@ static void ftgpio_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irqchip, desc); - stat = readl(g->base + GPIO_INT_STAT); + stat = readl(g->base + GPIO_INT_STAT_RAW); if (stat) for_each_set_bit(offset, &stat, gc->ngpio) generic_handle_irq(irq_find_mapping(gc->irq.domain,