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Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index c33e9bc79521..4a1f9c27b5f0 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -12,9 +12,13 @@ maintainers: properties: compatible: - enum: - - ti,j721e-wiz-16g - - ti,j721e-wiz-10g + oneOf: + - const: ti,j721e-wiz-16g + - const: ti,j721e-wiz-10g + - const: ti,am64-wiz-10g + - items: + - const: ti,am64-wiz-10g + - const: ti,j721e-wiz-10g power-domains: maxItems: 1 From patchwork Thu Dec 24 11:42:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351902 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949192jai; Thu, 24 Dec 2020 03:45:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJwfH0SUpLG6lq50aOMpQbNg6PVN7Doo6BeBGgIkykl7R/C7REoGqZaaKuI6AqIP3G/gmMJx X-Received: by 2002:aa7:d906:: with SMTP id a6mr28471364edr.121.1608810316009; Thu, 24 Dec 2020 03:45:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608810316; cv=none; d=google.com; s=arc-20160816; b=EtkI03xgZgSNpIJWNB9ImcX1S3Cs1nsiNNOOvFM+dgdyNLeMYHguIuKekcLbbEJH38 x3QZvnhpKbUzq46o19hQEn0AJDEy5Ih2iSkUdN0rKQ6Ae8eUEms/9LYax8Dl5T6pyPQe QyqX+K9rlXyvoLBn1omELfPDOrbumgITXZQrJ7rUZqTBuRXHd0YyU3w0eHSY/PuHQCQa eerWPUU0ZWB/OkV0eykNakIBgyMw2nNmqsL+xv+SAttfS4x27u5U+VfbcPUBVPNXh3Ih uF6EEzcuWkuV7zNYxxGg6qvQ4wo8LlBctXcFywDFt5h+EBHnHBibl4CTBN3PEO2Fw6nt vYyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=94E65ixmOJZFX7TRdsWv8gU0jihL6XoZszoQCsm3YLE=; b=KI2q7sUj3B9y9tzRF3b6FPQ2Sd6l08kqqlJcp7HaBqVpiTJYnpbno9q5SBjYAynOku 7xlsPk0+h+lcGk8P76oXnYftNvsUWL+y2pI5vxd8wH5DpeVnQEJHA60P2V3IGDDWoy3C l6974DWX0UDa7q76yc6OKq2LGdwRXgNb1wrNWLFgkTQhQFHXwff2D3TelNYc0yqVthnn uQjUTQK6yP65AIgIXiwHksnOhZUhXMXpISLH+OmV11eLEQJA4yvZoyCaRMa2o90Vd5+v uvaBvYrV09ZBg4BRSkUx1DgT0LGBPe7PqXeU4TpumMYDSVt0wZY1XlLey+YCjm0NzmDS avYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=veF4Uir3; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 4a1f9c27b5f0..14823588bc94 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -149,6 +149,19 @@ patternProperties: - assigned-clocks - assigned-clock-parents + "^phy-en-refclk$": + type: object + description: | + In order to drive the refclk out from the SERDES (Cadence Torrent), + PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model phy-en-refclk + as a clock so that it can be enabled directly or as a parent clock. + properties: + "#clock-cells": + const: 0 + + required: + - "#clock-cells" + "^serdes@[0-9a-f]+$": type: object description: | From patchwork Thu Dec 24 11:42:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351898 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949160jai; Thu, 24 Dec 2020 03:45:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSAwVishKL0cBVmGShqNFtykEQTqYBE5iab4jNDCWs5hN84zDBV8+16/0azB9xvoSqM2Ew X-Received: by 2002:a17:906:4a4f:: with SMTP id a15mr28394268ejv.541.1608810312522; Thu, 24 Dec 2020 03:45:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608810312; cv=none; d=google.com; s=arc-20160816; b=Qw/rV3AvMh51LN0Co/AYvBzubVuiSKlorgS6xkBX9vZ8F0ehgN7b7hBKnCfoeTOTaG vGrOc74UeEy2i62rTMJ3lLRqPF549y9XrUhTMS2cQ2LcVgI4vpCjEdovtiR/Do2AZ0O6 va/NfzBVGw1QQXOZafcb2x33YcUuqWTlLmn3sHz3hKJS+MIQ6zAHhiBkoWtAivp9hdH9 ke4NMPO6mGj5usvjkf+VWpVn/RcLNEG+fgobMGGsnQxhGOE8aGn0cjRrBAm3jDqfANuF Wd0U5hRr33Gp3rrMjFNh+bHT8NHuhZpdzuk0wbvGKFRt0Zx0/hTf2jejGmx/x1BNfmnU /VJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ovMxIAcf6Y9YiGb7+AcUSIA6TimQiEmhgqrwck2ZN7c=; b=bTRmFwyYS1nymxASF6oHMwH3hz+kYNwRKunDEliA7n7UGIzbUI/tjxdwNfZxaMl25Q JstzdjTGXgavwadr2XLG6AmwmDy70vktr7Zl+q7GH0r7WXSp/rKt05TLR9tS1HrlV08C 8I+1WyqZU4zOE4LN3s4bzFTRP4oOjUF3w9wrpRjGvvx9tPMrl/+TVIME7gLg1+zDry1X SFYDeQuNsRqoxRRYwJ9fpkBUf9V0UFYKtezKMf56KoqT62zzFtl5iRMdHwmTUZTt/nOU ARB7TwlC2CfnsBc2CSVh0DI3SCwIkOzTpYfnhw15bfscpQRILd/nDhnVJR3yUA4bubeL kIfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="V941GK/m"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o4si12933767ejr.495.2020.12.24.03.45.12; Thu, 24 Dec 2020 03:45:12 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="V941GK/m"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgLXLoE (ORCPT + 7 others); Thu, 24 Dec 2020 06:44:04 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:41422 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726611AbgLXLoE (ORCPT ); Thu, 24 Dec 2020 06:44:04 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBhGIM048674; Thu, 24 Dec 2020 05:43:16 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608810196; bh=ovMxIAcf6Y9YiGb7+AcUSIA6TimQiEmhgqrwck2ZN7c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V941GK/mI2vmaMrEwitGERPd0l0Y1N8LBcpi5lCKWuzNbWiAEEcsbaJC9l2zgAYpE wgYjUnFmZAhn9oRgwDmp+05vIrqofFDJb7y7uMu/vuwJoA3+yAxu4sIlK1yW/xs0Nj 1Quuw7Hn6vpZIaDuNvF98BH3wyLkzws8ReLX6l3Q= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBhG6X089826 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:43:16 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:43:15 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:43:15 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBgtwW026267; Thu, 24 Dec 2020 05:43:11 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Swapnil Jakhade , Peter Rosin CC: , , Subject: [PATCH 3/7] dt-bindings: phy: cadence-torrent: Add binding for refclk driver Date: Thu, 24 Dec 2020 17:12:46 +0530 Message-ID: <20201224114250.1083-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224114250.1083-1-kishon@ti.com> References: <20201224114250.1083-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for refclk driver used to route the refclk out of the SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-torrent.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index e266ade53d87..d3b96afd514c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -125,6 +125,23 @@ patternProperties: additionalProperties: false + "^refclk-driver": + type: object + description: | + Driver to route the reference clock out of the SERDES. + properties: + clocks: + maxItems: 1 + description: Phandle to clock nodes representing the input to the + refclk driver. + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + required: - compatible - "#address-cells" From patchwork Thu Dec 24 11:42:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351899 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949168jai; Thu, 24 Dec 2020 03:45:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJw5YD4otLAK4rbSGnAh+EfhS7gOHO3lADpj1smeSFiapdc05lP0/oG6RXutRJigg90WJh/7 X-Received: by 2002:a50:b246:: with SMTP id o64mr16919794edd.132.1608810313374; Thu, 24 Dec 2020 03:45:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608810313; cv=none; d=google.com; s=arc-20160816; b=iLjBUYRBewQFOFG3KD1urU3aKxoQTgrzzn1bykrzXFztscn49yYDvikosRRjolt3KN roSo7vDpJDcQCW200valELP1ffT4oM24qWY4N9zx+XhvU5lt+tm8hmTmy9bJrphcfw1o ehbyCcwsjWOJ9uY4XW31hvp3PrlAzvi84RK/h+mCdxYDMuHP02gy1D9DKz9KA/MYdEOm S6CM9oxcrN77gnO7Xb3lXD7d6PBn5qSwvZ3P3kk6iLBLbvhmKfebGj+c7p4fZWNGnVt6 dcfzQjYTgV8NhZdbom4CqLbMvCRqHDZ9EPReQV/8Sv76FP8r3qCvZR5x02nhuEh6d7L7 LQ0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uBuv+SA+RAdeWsnzltldKqL0qlFzkvQrF1N+8ccx8gk=; b=IvOGK4EddrorEF2u6nQQy5lAoHVoakkSDVjOkL/qQ0qc1vshqClUxdaQsliHC0/yr/ hjPC6ZN+n6STY9PM/0fMoiVNuk21zeA1RDCMS8EPl0/IjVbjqCyA32kCJFSq9SsaVv2F T9fZIzNdHOlyQnmk5H9967/yYLlVBjN1VzecN+B9pMEAMFBJ0Ffaws4NzLAqns81p6KH Gst/qpSM7rtb2EoohKSVjJ8ReUdHUE2vyqWBoRO3MLJhP+//dMmlnikTMNZ4RHpSKMqg YX1nwZsM5fyqzRCY/g95DILNb6pXcnvNEYWf/TDBc6+23rm5ybzs+epDlcjeTCkEamRu qloA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=I6jlv3LZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o4si12933767ejr.495.2020.12.24.03.45.13; Thu, 24 Dec 2020 03:45:13 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=I6jlv3LZ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728133AbgLXLoO (ORCPT + 7 others); Thu, 24 Dec 2020 06:44:14 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:41482 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726611AbgLXLoO (ORCPT ); Thu, 24 Dec 2020 06:44:14 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBhLQa048694; Thu, 24 Dec 2020 05:43:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608810201; bh=uBuv+SA+RAdeWsnzltldKqL0qlFzkvQrF1N+8ccx8gk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I6jlv3LZ56tG8A5SF+PGZAkywdcemQjOT8goLIABBZgy4hwbzgu4bR/eyaglKHpi6 WPNhArtCFdimOdz6CnPxMi5dPEayqnWxft/v28ydTz1PzRYbHOIUsr5dQGKYAaErSw clygsuCuqRDFHdY/juheFJ+83THOagwKpi4GEx0U= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBhL2E000655 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:43:21 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:43:20 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:43:20 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBgtwX026267; Thu, 24 Dec 2020 05:43:16 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Swapnil Jakhade , Peter Rosin CC: , , Subject: [PATCH 4/7] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Date: Thu, 24 Dec 2020 17:12:47 +0530 Message-ID: <20201224114250.1083-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224114250.1083-1-kishon@ti.com> References: <20201224114250.1083-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/mux/ti-serdes.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 Acked-by: Peter Rosin diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 9047ec6bd3cf..68e0f76deed1 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -90,4 +90,8 @@ #define J7200_SERDES0_LANE3_USB 0x2 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +/* AM64 */ +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ From patchwork Thu Dec 24 11:42:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351903 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949197jai; Thu, 24 Dec 2020 03:45:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJxZjcphPlb0YQDPk8TTMt2APdQQy1e42XM/Gmuo5m5uJXP7fOy4hT4TAf7TXUrkFvJydpj8 X-Received: by 2002:a17:906:65a:: with SMTP id t26mr21456811ejb.394.1608810316927; Thu, 24 Dec 2020 03:45:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608810316; cv=none; d=google.com; s=arc-20160816; b=K04yGaKG7VqJVkrRy5HYXLn8Zam+F8AKQLzWvtj5wH6+kZkZCvoKHHM17Q57ogl4+Q dXhkT1xmYQO8gA2SkkOUqnFDHlsT1wravRF4wNAgFl8Gtjl/6SRe15f5KYCdllzsQvll LhoBBh867n/7PSBexWAo0tF5rW/xwAQApUI82XUA9mSvkbBTetEtT7WV5IIj5qEyYuT8 dEfC0Q47TezTQZ+x2/Ib+7ldh7vmm2lvcdB7rHlH+hkD+vyYbp2zYA5okTFy84d22NsT 9UfRGV7pCfQuJ0AJfl12pox3GDOzvftu+3Mpye1H55tSjGlEHII+1Rt5FdFM2hRiGUuC khAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Vz2S1Lgq/nohS1dKmSuXj6sZuS4dVt0If4oumnEmOOI=; b=rsV5cJT0ooFnlMhzwgA++j1uLKJlVNTe7IJPtSFrB1JD+IhS2EXoMtw1v2OsKzGGGe dkCaLdlmWhnbXRJLh2FAxgyu72fWpR+pWojhlgjcJvNAqnL9Z7dj+VKdKGo0CYqDs8E4 WsmMu3XtGujlIGKh+6OuQIhURnRHPuvPWX41FpWazGykDhP3MEN7MQe7xpFYTXB7nkq+ Mq2RvjcdXHd9vlxiSGrf6RQNojsbtSC9Qx9t0KH67c1+9yujKhJBSYpirV3pbPrxP7ZW fhUAMmdiOyTwH68W5ga9ExcWkx/nbGRb9gaq5s8qiyFrDegN94uqYBOs2SgqYBr5mH5K eJGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wCdyM6k5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o4si12933767ejr.495.2020.12.24.03.45.16; Thu, 24 Dec 2020 03:45:16 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wCdyM6k5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726609AbgLXLpL (ORCPT + 7 others); Thu, 24 Dec 2020 06:45:11 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39682 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726591AbgLXLpK (ORCPT ); Thu, 24 Dec 2020 06:45:10 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBhQac083386; Thu, 24 Dec 2020 05:43:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608810206; bh=Vz2S1Lgq/nohS1dKmSuXj6sZuS4dVt0If4oumnEmOOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wCdyM6k5tIH51U1b+FqqTy3WyGK9OIHQ8QyF8msHEphu8uMSdtqBFRFqlqG1mLbDj Owg/QhSIgcThbggdx6RG4IY4LpcdOcFsbt5k7NztNQzv8+Zq00HmM2dDUjFodczXIu +weDJvU93M40R/r+WX/iq9cu7oa/I+DAXYMy992I= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BOBhQ0Z000767 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Dec 2020 05:43:26 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 24 Dec 2020 05:43:25 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 24 Dec 2020 05:43:25 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BOBgtwY026267; Thu, 24 Dec 2020 05:43:21 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Nishanth Menon , Swapnil Jakhade , Peter Rosin CC: , , Subject: [PATCH 5/7] phy: ti: j721e-wiz: Configure full rate divider for AM64 Date: Thu, 24 Dec 2020 17:12:48 +0530 Message-ID: <20201224114250.1083-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224114250.1083-1-kishon@ti.com> References: <20201224114250.1083-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 43 +++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 2a03191eac64..08acfab1ebe6 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -101,6 +101,13 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 24, 25), }; +static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { + REG_FIELD(WIZ_LANECTL(0), 22, 23), + REG_FIELD(WIZ_LANECTL(1), 22, 23), + REG_FIELD(WIZ_LANECTL(2), 22, 23), + REG_FIELD(WIZ_LANECTL(3), 22, 23), +}; + static const struct reg_field typec_ln10_swap = REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); @@ -193,6 +200,7 @@ static struct wiz_clk_div_sel clk_div_sel[] = { enum wiz_type { J721E_WIZ_16G, J721E_WIZ_10G, + AM64_WIZ_10G, }; #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ @@ -210,6 +218,7 @@ struct wiz { struct regmap_field *p_align[WIZ_MAX_LANES]; struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; + struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; struct regmap_field *pma_cmn_refclk_int_mode; struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; @@ -380,7 +389,7 @@ static int wiz_regfield_init(struct wiz *wiz) } clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; - if (wiz->type == J721E_WIZ_10G) + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, refclk_dig_sel_10g); @@ -424,6 +433,14 @@ static int wiz_regfield_init(struct wiz *wiz) i); return PTR_ERR(wiz->p_standard_mode[i]); } + + wiz->p0_fullrt_div[i] = + devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); + if (IS_ERR(wiz->p0_fullrt_div[i])) { + dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", + i); + return PTR_ERR(wiz->p0_fullrt_div[i]); + } } wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, @@ -719,6 +736,19 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, return ret; } +static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) +{ + int ret = 0; + + if (wiz->type != AM64_WIZ_10G) + return 0; + + if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) + ret = regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + + return ret; +} + static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { @@ -742,6 +772,10 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, return ret; } + ret = wiz_phy_fullrt_div(wiz, id - 1); + if (ret) + return ret; + if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); else @@ -769,6 +803,9 @@ static const struct of_device_id wiz_id_table[] = { { .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G }, + { + .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G + }, {} }; MODULE_DEVICE_TABLE(of, wiz_id_table); @@ -904,14 +941,14 @@ static int wiz_probe(struct platform_device *pdev) wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes; - if (wiz->type == J721E_WIZ_10G) + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) wiz->clk_mux_sel = clk_mux_sel_10g; else wiz->clk_mux_sel = clk_mux_sel_16g; wiz->clk_div_sel = clk_div_sel; - if (wiz->type == J721E_WIZ_10G) + if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; else wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; From patchwork Thu Dec 24 11:42:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351900 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949175jai; Thu, 24 Dec 2020 03:45:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwPPBhH6R/0YkVinm2Z7n54td6q1gPw0EH2hqy8HqyyL2+32KPVhGWzDTngXxISwIEcnwZ9 X-Received: by 2002:aa7:d2c9:: with SMTP id k9mr28220096edr.74.1608810314284; Thu, 24 Dec 2020 03:45:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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Date: Thu, 24 Dec 2020 17:12:49 +0530 Message-ID: <20201224114250.1083-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224114250.1083-1-kishon@ti.com> References: <20201224114250.1083-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cmn_refclk_

lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_

can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 115 +++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) -- 2.17.1 diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 08acfab1ebe6..d60a9a01a8b2 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -54,6 +54,7 @@ enum wiz_refclk_div_sel { static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); +static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); static const struct reg_field pll1_refclk_mux_sel = REG_FIELD(WIZ_SERDES_RST, 29, 29); static const struct reg_field pll0_refclk_mux_sel = @@ -141,6 +142,15 @@ struct wiz_clk_div_sel { const char *node_name; }; +struct wiz_phy_en_refclk { + struct clk_hw hw; + struct regmap_field *phy_en_refclk; + struct clk_init_data clk_data; +}; + +#define to_wiz_phy_en_refclk(_hw) \ + container_of(_hw, struct wiz_phy_en_refclk, hw) + static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { { /* @@ -214,6 +224,7 @@ struct wiz { unsigned int clk_div_sel_num; struct regmap_field *por_en; struct regmap_field *phy_reset_n; + struct regmap_field *phy_en_refclk; struct regmap_field *p_enable[WIZ_MAX_LANES]; struct regmap_field *p_align[WIZ_MAX_LANES]; struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; @@ -450,9 +461,96 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->typec_ln10_swap); } + wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, + phy_en_refclk); + if (IS_ERR(wiz->phy_en_refclk)) { + dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); + return PTR_ERR(wiz->phy_en_refclk); + } + return 0; } +static int wiz_phy_en_refclk_enable(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + + regmap_field_write(phy_en_refclk, 1); + + return 0; +} + +static void wiz_phy_en_refclk_disable(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + + regmap_field_write(phy_en_refclk, 0); +} + +static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); + struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; + int val; + + regmap_field_read(phy_en_refclk, &val); + + return !!val; +} + +static const struct clk_ops wiz_phy_en_refclk_ops = { + .enable = wiz_phy_en_refclk_enable, + .disable = wiz_phy_en_refclk_disable, + .is_enabled = wiz_phy_en_refclk_is_enabled, +}; + +static int wiz_phy_en_refclk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *phy_en_refclk) +{ + struct wiz_phy_en_refclk *wiz_phy_en_refclk; + struct device *dev = wiz->dev; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + char clk_name[100]; + struct clk *clk; + int ret; + + wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), + GFP_KERNEL); + if (!wiz_phy_en_refclk) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &wiz_phy_en_refclk->clk_data; + + init->ops = &wiz_phy_en_refclk_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + wiz_phy_en_refclk->phy_en_refclk = phy_en_refclk; + wiz_phy_en_refclk->hw.init = init; + + clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Fail to add clock provider: %s\n", clk_name); + + return ret; +} + static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) { struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); @@ -713,6 +811,20 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node) of_node_put(clk_node); } + clk_node = of_get_child_by_name(node, "phy-en-refclk"); + if (clk_node) { + ret = wiz_phy_en_refclk_register(wiz, clk_node, + wiz->phy_en_refclk); + if (ret) { + dev_err(dev, "Failed to register %s clock\n", + node_name); + of_node_put(clk_node); + goto err; + } + + of_node_put(clk_node); + } + return 0; err: wiz_clock_cleanup(wiz, node); @@ -828,6 +940,9 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) of_node_name_eq(subnode, "link"))) continue; + if (!(of_node_name_eq(subnode, "link"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { dev_err(dev, From patchwork Thu Dec 24 11:42:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 351904 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp6949942jai; Thu, 24 Dec 2020 03:46:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJwl3aZ7ce3OSr/EUOF4StKRiZ0/48mVwIb/j0ay/sLDUk7dPrkgxGz/OUE+PlbTuy6o0stA X-Received: by 2002:a17:906:15c7:: with SMTP id l7mr28156464ejd.226.1608810398992; Thu, 24 Dec 2020 03:46:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608810398; cv=none; d=google.com; s=arc-20160816; b=vWQThk68wnrc6pCHbZWog47nE42nWaXa97F2EYOVwnUWa8R2tAhitRUjelgaWKZgK+ Zxiqm8VNxgQRhPs++GQ+d2GHh9FimsiW3b+xquV4mnpYVh3xa2eQkKly2FLyFY1Cgp8S h3EoT4S1ks+u4l/fhcvot8GkeVsFrHufoazZxZgFH5/Id6s9nrnhTpEDnPkV4yn0Id3u v7fQhQS0z+KyJlvne/Yrl5Hb2Izb3GvVVYiUmwHspDVsN/2+QH6s65xFHfvjTD4iwNGH OBbxeiRIqN1xKIpL6bhVTHXT5R1u2gf3GBxw/soyyQLWW4J2bBNdwogM1s4CqtjY8llS QIfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=C6VmPER5GCq2++TCYUbhbv+YgfcUFKsHywohrusjcBI=; b=tavKVO7I2PrIMTQpV9dK+s5wKYQOjECMvxjVoCsdpSi7LUZHgpg9KWVgsVQ5SS88XQ 1VBkaApl1JhFJmj0RzerGXjC7lDIqg+GyAgTowNo13CEJLrYRsuZ+MYd7E0PkPdnrKey gskkR96b78HF3NX52K6P743M8RZ1D9hkINYSyBUaTJ4pdNOSlFO0/AOlnpI2ZnCys3Qw 8SMmPkQ/IaLkkRjxs2jqDFs0ApZaIuRKreJkamuQ46To+vu9HGKFM5kAr6j5VNSMpmJQ xpklDYGP4CLr48tTLMiMCvNP4T6bMb6DhJjb8UFS7ar3aiOAUCGsxUuokCFeo/mtpM3o qbQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yq4RPbtt; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_

can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-torrent.c | 158 ++++++++++++++++++++++ 1 file changed, 158 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index f310e15d94cb..ad01fb61cfa4 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,8 @@ * register offsets from SD0801 PHY register block base (i.e MHDP * register base + 0x500000) */ +#define CMN_CDIAG_REFCLK_OVRD 0x004CU +#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U #define CMN_SSM_BANDGAP_TMR 0x0021U #define CMN_SSM_BIAS_TMR 0x0022U #define CMN_PLLSM0_PLLPRE_TMR 0x002AU @@ -206,6 +209,8 @@ #define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ +#define PHY_PIPE_CMN_CTRL1 0x0000U +#define PHY_ISO_CMN_CTRL 0x0008U #define PHY_PLL_CFG 0x000EU #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U @@ -231,6 +236,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl = static const struct reg_field phy_reset_ctrl = REG_FIELD(PHY_RESET, 8, 8); +#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2 + +enum cdns_torrent_refclk_out_pcs { + PHY_ISO_CMN_CTRL_8, + PHY_PIPE_CMN_CTRL1_0, +}; + +#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5 + +enum cdns_torrent_refclk_out_cmn { + CMN_CDIAG_REFCLK_OVRD_4, + CMN_CDIAG_REFCLK_DRV0_CTRL_1, + CMN_CDIAG_REFCLK_DRV0_CTRL_4, + CMN_CDIAG_REFCLK_DRV0_CTRL_5, + CMN_CDIAG_REFCLK_DRV0_CTRL_6, +}; + +static const struct reg_field refclk_out_pcs_cfg[] = { + [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8, 8), + [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0), +}; + +static const struct reg_field refclk_out_cmn_cfg[] = { + [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4), + [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), + [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), + [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), + [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), +}; + enum cdns_torrent_phy_type { TYPE_NONE, TYPE_DP, @@ -288,6 +323,16 @@ enum phy_powerstate { POWERSTATE_A3 = 3, }; +struct cdns_torrent_derived_refclk { + struct clk_hw hw; + struct regmap_field *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG]; + struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG]; + struct clk_init_data clk_data; +}; + +#define to_cdns_torrent_derived_refclk(_hw) \ + container_of(_hw, struct cdns_torrent_derived_refclk, hw) + static int cdns_torrent_phy_init(struct phy *phy); static int cdns_torrent_dp_init(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, @@ -1604,6 +1649,110 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) return ret; } +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); + regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1); + regmap_field_write(derived_refclk->pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1); + regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 1); + + return 0; +} + +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + + regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 0); +} + +static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) +{ + struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); + int val; + + regmap_field_read(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], &val); + + return !!val; +} + +static const struct clk_ops cdns_torrent_derived_refclk_ops = { + .enable = cdns_torrent_derived_refclk_enable, + .disable = cdns_torrent_derived_refclk_disable, + .is_enabled = cdns_torrent_derived_refclk_is_enabled, +}; + +static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy, + struct device_node *node) +{ + struct cdns_torrent_derived_refclk *derived_refclk; + struct device *dev = cdns_phy->dev; + struct regmap_field *field; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + struct regmap *regmap; + char clk_name[100]; + struct clk *clk; + int ret, i; + + derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); + if (!derived_refclk) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &derived_refclk->clk_data; + + init->ops = &cdns_torrent_derived_refclk_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + regmap = cdns_phy->regmap_phy_pcs_common_cdb; + for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG; i++) { + field = devm_regmap_field_alloc(dev, regmap, refclk_out_pcs_cfg[i]); + if (IS_ERR(field)) { + dev_err(dev, "PCS reg field init failed\n"); + return PTR_ERR(field); + } + derived_refclk->pcs_fields[i] = field; + } + + regmap = cdns_phy->regmap_common_cdb; + for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG; i++) { + field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); + if (IS_ERR(field)) { + dev_err(dev, "CMN reg field init failed\n"); + return PTR_ERR(field); + } + derived_refclk->cmn_fields[i] = field; + } + + derived_refclk->hw.init = init; + + clk = devm_clk_register(dev, &derived_refclk->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add refrcv clock provider: %s\n", + clk_name); + + return ret; +} + static int cdns_torrent_phy_on(struct phy *phy) { struct cdns_torrent_inst *inst = phy_get_drvdata(phy); @@ -2150,6 +2299,15 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) /* Enable APB */ reset_control_deassert(cdns_phy->apb_rst); + child = of_get_child_by_name(dev->of_node, "refclk-driver"); + if (child) { + ret = cdns_torrent_derived_refclk_register(cdns_phy, child); + if (ret) { + dev_err(dev, "failed to register derived refclk\n"); + return ret; + } + } + for_each_available_child_of_node(dev->of_node, child) { struct phy *gphy;