From patchwork Wed Dec 23 11:03:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 351560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C1E1C433E0 for ; Wed, 23 Dec 2020 11:05:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E42C9222F9 for ; Wed, 23 Dec 2020 11:05:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728362AbgLWLFT (ORCPT ); Wed, 23 Dec 2020 06:05:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728303AbgLWLFS (ORCPT ); Wed, 23 Dec 2020 06:05:18 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6F99C061794 for ; Wed, 23 Dec 2020 03:04:37 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id v2so10176329pfm.9 for ; Wed, 23 Dec 2020 03:04:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UCpNXBLs8298nV11fod2O1HtjRRraxH4UkX4Yv1+PQk=; b=rm0mYdbD8d/695juRo4oy1IhUDYL/Y71+amkr3dlh0zAnX5bfUVgOBuvAQND8lHddt WVejHFLn4Qt5W3WAA7Gijrl9RvF7URyAu32CGp/dXAIpDiFRIUNUqZAgRfmcynEMPfTG 65BAtDPIfCoglSwbjtP2urQGVgQux0TtQSDQo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UCpNXBLs8298nV11fod2O1HtjRRraxH4UkX4Yv1+PQk=; b=lF3O1ov6QTNCobXBdii8dTFDAx5UYV5FZpmNsQedRQ0jOsNctHC1lBgTf16MxWYqp2 qsW/p5c2psNScZ+8GPjdeRn8Cl7JTdvr0qYuJUIdWt5kBrf/zqYunNy32xCtSvjle0nQ 9TFiQzs3UgS9Fwet02NQfwfCNBveWXkpqWJVyrnMOJf/NS96vjzZStrd+5gGwoSkUwQY n/+B4zS7+cCmP7lOOZJiM9dS7YZQjeds1b+F0MEfkhwTqX9dj9whFd545BuCquFWSfBs 3J7/4taIUzskXygMWcK8sNSU4zycOZcF6afrhZVIgtbXCF8dDNWNGXundMVjRE9A9U1O DyiQ== X-Gm-Message-State: AOAM532UyuJqmVYr80VbPG2hob7G3pqAcB4w99PHsgTUXnr8UAmOxNHv H9OukEUKXlTTLnNpF/EqqgZsEQ== X-Google-Smtp-Source: ABdhPJxA1TmgS+k2PrAa5h6XdzoifIMR7/nUKrYzrTet4Atk7S1muCkIPsTTTIs8XyWpr+0rzjEcpg== X-Received: by 2002:aa7:8499:0:b029:19e:6c5:b103 with SMTP id u25-20020aa784990000b029019e06c5b103mr23502520pfn.13.1608721477401; Wed, 23 Dec 2020 03:04:37 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a884:eca4:40c1:8784:571c]) by smtp.gmail.com with ESMTPSA id 3sm23275909pfv.92.2020.12.23.03.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 03:04:36 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon Subject: [PATCH v3 1/6] arm64: defconfig: Enable REGULATOR_PF8X00 Date: Wed, 23 Dec 2020 16:33:38 +0530 Message-Id: <20201223110343.126638-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PF8X00 regulator driver by default as it used in some of i.MX8MM hardware platforms. Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jagan Teki --- Changes for v3: - collect Krzysztof r-b Changes for v2: - updated commit message arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index fae83673c3c3..e952c76ee970 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -594,6 +594,7 @@ CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PF8X00=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y From patchwork Wed Dec 23 11:03:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 352074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EF7FC433DB for ; Wed, 23 Dec 2020 11:05:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FEE1223E4 for ; Wed, 23 Dec 2020 11:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728403AbgLWLFl (ORCPT ); Wed, 23 Dec 2020 06:05:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728233AbgLWLFl (ORCPT ); Wed, 23 Dec 2020 06:05:41 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16CB0C0613D3 for ; Wed, 23 Dec 2020 03:05:01 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id x18so8964456pln.6 for ; Wed, 23 Dec 2020 03:05:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EVAwYhY605SAEDbOs0QxfT3jdZd8fH4RLlfZ8Qm9ewI=; b=aZ0/Y7+Mf3kkO9Xty9DO4lPriwuLnt171ioy6SSo/fw32sk+OGtXhqC3FMtw3DAeQl ig879whOupO+Sm39SobJVKcH5Udrm6JRsZ8f8q7jrniAXHQrr2yerK9U2HXrdVDrKuQP syRccRnTjNIeX2b2+kBMDfjGPMZgnHZLdA1Bs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EVAwYhY605SAEDbOs0QxfT3jdZd8fH4RLlfZ8Qm9ewI=; b=CVorZ05D9F+XaOwjdOpiM8rXLp64tzDy/EWz7Cd9MSVa3Kcz16YN9BnuD98hU+nrIB qO9GHXS1ggyMy9iJqS9wnH+U88BDLMN9FmtOvJRxdH6xSHRXRFsN0bpcljafIPVPV0l6 5JbiXjoRykZ5zPvj5rwgqKXcGDvpiBz0e+vQ6jqN5Zv+R+k3wNBUbSKY6Gc1AvmsVizb miVCWIVYt7tQBxSwJBKI9Hb9ZZalsfM343nlUFxju0I+lJ5yFRm7brUA1rXXYi3UJ8gl iBaBap5/JpLlCfjAc/U8DuFEiqYBO1/HD4SPnaPrUo0MSZ/KIGLS3f17w/KjpIbg0IP1 ZqdA== X-Gm-Message-State: AOAM53326RY5blu2vGWCt3xeg/Ph/NDrj6Kp0aQqq9vnZdVxRVSdhzpz CAbFiNuc9nkqMp+thhGXp1eplQ== X-Google-Smtp-Source: ABdhPJwvSsuoooLM88eoPtgxrmNj7/6mKz2LqwPuxzBF/oFBJQLN2LgnJNKLMe9Rvm2fLOQqQW/how== X-Received: by 2002:a17:902:8d8d:b029:dc:4609:58a9 with SMTP id v13-20020a1709028d8db02900dc460958a9mr6511503plo.27.1608721500658; Wed, 23 Dec 2020 03:05:00 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a884:eca4:40c1:8784:571c]) by smtp.gmail.com with ESMTPSA id 3sm23275909pfv.92.2020.12.23.03.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 03:05:00 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon Subject: [PATCH v3 2/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0 Date: Wed, 23 Dec 2020 16:33:39 +0530 Message-Id: <20201223110343.126638-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring --- Changes for v3: - add proper bindings Changes for v2: - updated commit message Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 67980dcef66d..f1de68341873 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -673,6 +673,12 @@ properties: - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm + - description: Engicam i.Core MX8M Mini SoM based boards + items: + - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core MX8M Mini C.TOUCH 2.0 + - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM + - const: fsl,imx8mm + - description: Kontron BL i.MX8MM (N801X S) Board items: - const: kontron,imx8mm-n801x-s From patchwork Wed Dec 23 11:03:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 351559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 723F5C433E0 for ; Wed, 23 Dec 2020 11:06:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39AB2222F9 for ; Wed, 23 Dec 2020 11:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728428AbgLWLGC (ORCPT ); Wed, 23 Dec 2020 06:06:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728295AbgLWLGB (ORCPT ); Wed, 23 Dec 2020 06:06:01 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DDDDC061793 for ; Wed, 23 Dec 2020 03:05:21 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id s21so10150260pfu.13 for ; Wed, 23 Dec 2020 03:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IeBVDoKx8P7ruCXAEHPJs+rWdNCAKxiwqnaq9oGNJaU=; b=PVZhsMw+EGTb36uwbHOLAk6aRi7kJqSViCf9/n+n5kHjr1+dEyeSmLBzeZZ7ODDgLO yVLx4vEaobtksPOKXx9+ihR4bUQ7F02xgCBq6Jnri47uSp066DeS54JFy/G42rfPubaJ 1o3K8mT48km2an3dMYZFsI4ltFxiAh2Fk8zYI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IeBVDoKx8P7ruCXAEHPJs+rWdNCAKxiwqnaq9oGNJaU=; b=W0wuionpA9icl9Boo8x+VtdBW6GSUouqYrTUasc39QhmHh5JD/mCGmolOUficdQzdq 4APaXVYO3PMDKjghjtxyQGUbFROs9DOqz/TkQ/B7FzYpuiT6byF5c+noT0FwaofQKCwl xtaHwjMFxoZEmpceMovkrxpzxJFb/JkW9TOUc2hj3F+4w3rfwvkW0jJ9+3anXKQ/ykP5 IMTK7MqCOCsgGW3umEcuf5JsthzrvJ9VKntHHoydGztH2W34Hnqj8bJQ9EhCb5o2W0XH XqVjQzlncVSmGESKlFAYkSZfByWK4V+Qem1SfelD/qQ1F725AxwW0uOzQihjK8w5Chw5 D20w== X-Gm-Message-State: AOAM530UIWz6MnNNqoAc0UlQpYKgUOLPaw6JHI2vXmTKjrHosQ07AK05 hA5gk1aozHF0nEIlZYkDIBLXdQ== X-Google-Smtp-Source: ABdhPJx8XT38O5aXRz0uJ6uxfOz0+ZxoA0IWTlpJG4CpRhtLNv7vOqnIHliMKsXKbfsMLuBBKYvZuQ== X-Received: by 2002:a63:1401:: with SMTP id u1mr12411577pgl.229.1608721521191; Wed, 23 Dec 2020 03:05:21 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a884:eca4:40c1:8784:571c]) by smtp.gmail.com with ESMTPSA id 3sm23275909pfv.92.2020.12.23.03.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 03:05:20 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon , Matteo Lisi Subject: [PATCH v3 3/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM Date: Wed, 23 Dec 2020 16:33:40 +0530 Message-Id: <20201223110343.126638-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Jagan Teki --- Changes for v3: - keep regulator min/max hoping Changes for v2: - updated commit message - add cpu nodes - add fec1 node - fixed pmic tree comments - dropped engicam from filename since it aligned with imx6 engicam dts files naming conventions. .../dts/freescale/imx8mm-icore-mx8mm.dtsi | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi new file mode 100644 index 000000000000..b40148d728ea --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; +}; + +&A53_0 { + cpu-supply = <®_buck4>; +}; + +&A53_1 { + cpu-supply = <®_buck4>; +}; + +&A53_2 { + cpu-supply = <®_buck4>; +}; + +&A53_3 { + cpu-supply = <®_buck4>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_ldo1: ldo1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_ldo2: ldo2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_ldo3: ldo3 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_ldo4: ldo4 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck1: buck1 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck2: buck2 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck3: buck3 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck4: buck4 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck5: buck5 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck6: buck6 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_buck7: buck7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vsnvs: vsnvs { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; From patchwork Wed Dec 23 11:03:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 352073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58CF0C433DB for ; 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Wed, 23 Dec 2020 03:05:41 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a884:eca4:40c1:8784:571c]) by smtp.gmail.com with ESMTPSA id 3sm23275909pfv.92.2020.12.23.03.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 03:05:40 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon , Matteo Lisi Subject: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0 Date: Wed, 23 Dec 2020 16:33:41 +0530 Message-Id: <20201223110343.126638-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Jagan Teki --- Changes for v3: - don't maintain common nodes and include it, if no feature diff Changes for v2: - enabled fec1 node - updated commit message - dropped engicam from filename since it aligned with imx6 engicam dts files naming conventions. - add i2c nodes - fixed v1 comments arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++++++++++++++++++ .../freescale/imx8mm-icore-mx8mm-ctouch2.dts | 21 +++++ 3 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6f0777ee6cd6..8d49a2c74604 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi new file mode 100644 index 000000000000..f7870efd9dab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +&fec1 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + max-frequency = <50000000>; + bus-width = <4>; + no-1-8-v; + pm-ignore-notify; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts new file mode 100644 index 000000000000..8eb01b1f882a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "imx8mm.dtsi" +#include "imx8mm-engicam-ctouch2.dtsi" +#include "imx8mm-icore-mx8mm.dtsi" + +/ { + model = "Engicam i.Core MX8M Mini C.TOUCH 2.0"; + compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm", + "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; From patchwork Wed Dec 23 11:03:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 351558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05E40C433DB for ; Wed, 23 Dec 2020 11:07:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCD37222F9 for ; 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Wed, 23 Dec 2020 03:06:04 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon Subject: [PATCH v3 5/6] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit Date: Wed, 23 Dec 2020 16:33:42 +0530 Message-Id: <20201223110343.126638-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring --- Changes for v3: - fix dt-bindings Changes for v2: - update commit message Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f1de68341873..2dab4b5bf99a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -675,7 +675,9 @@ properties: - description: Engicam i.Core MX8M Mini SoM based boards items: - - const: engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core MX8M Mini C.TOUCH 2.0 + - enum: + - engicam,icore-mx8mm-ctouch2 # i.MX8MM Engicam i.Core MX8M Mini C.TOUCH 2.0 + - engicam,icore-mx8mm-edimm2.2 # i.MX8MM Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit - const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM - const: fsl,imx8mm From patchwork Wed Dec 23 11:03:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 352072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A67C433DB for ; Wed, 23 Dec 2020 11:07:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEC24223E0 for ; Wed, 23 Dec 2020 11:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728504AbgLWLHN (ORCPT ); Wed, 23 Dec 2020 06:07:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728349AbgLWLHM (ORCPT ); Wed, 23 Dec 2020 06:07:12 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A4CEC0613D3 for ; Wed, 23 Dec 2020 03:06:32 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id g3so8971611plp.2 for ; Wed, 23 Dec 2020 03:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WOYP5E3jVy3ELBPtvkaJkjlrVuze1hWdvp4c36IdX2U=; b=p3zJlQz9Vlmt36EFHGxNdzwYc4aV+7XCBflEqgsTMb4FTSKRZYqq2Kgc3l05TNhmoe TrEhfhVw3v57V994HdPezMp64a38t6W4la0KAlq4CgYPTaGPMwyfK7g2XcBh+QuYSepw 0HWs3qxskX56JfLec1g2i209x5d/WUYbU7PSI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WOYP5E3jVy3ELBPtvkaJkjlrVuze1hWdvp4c36IdX2U=; b=C+9YNM6n1YNaCi5mSP4BhaANX17vkxmuPJAAePNKLKqER8eZP0Vmp3KdDbXJ+fcb7J w4C5vHKIWpnmpR2p1HbXMC/d74AR4J5YZEA8GAZxEmnGr7KXRvmVqlqmSplMRha3ZoNR Hgk6MUj/Yx6UgJU+ntA1TVQDl0FSK4ZXlIAMulNmoVzEBnxoEps3XtNWxsjLt87nRP2T 0b6Np1sNkASnFUO2/1yhS/meCSg627gY3JtVIQ+vc1MyaxbAiIXaxM7jWUy9hz0ovIY/ ehVl33F6AGWO22scRRIc7IrWOZgeivuUDeKdZMMX1049QjUacFnXieGsE3SCOYasy1j+ ++Wg== X-Gm-Message-State: AOAM532QkeB0yoJ3AuDm5gv3KxVEMh6BaDJwJZST7QN+RtZdqKzW09Dz vCwCUdugeY3wd9xY1GzpjuTKOIcZH1Gacx/z X-Google-Smtp-Source: ABdhPJyyfZ4l2rzFh4pr9Dn3ybD3K7BTXS5p8IgzG46e6KJLQl7UdKawwMBZ5zh6mv7hoChOneyX0w== X-Received: by 2002:a17:90a:cc0a:: with SMTP id b10mr25930062pju.59.1608721592088; Wed, 23 Dec 2020 03:06:32 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a884:eca4:40c1:8784:571c]) by smtp.gmail.com with ESMTPSA id 3sm23275909pfv.92.2020.12.23.03.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 03:06:31 -0800 (PST) From: Jagan Teki To: Rob Herring , Shawn Guo , Li Yang , Fabio Estevam , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula@amarulasolutions.com, Jagan Teki , Catalin Marinas , Will Deacon , Matteo Lisi Subject: [PATCH v3 6/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit Date: Wed, 23 Dec 2020 16:33:43 +0530 Message-Id: <20201223110343.126638-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223110343.126638-1-jagan@amarulasolutions.com> References: <20201223110343.126638-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. PCIe, DSI, CSI nodes will add it into imx8mm-engicam-edimm2.2.dtsi once Mainline Linux supported. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Jagan Teki --- Changes for v3: - don't maintain common nodes and include it, if no feature diff Changes for v2: - updated commit message - dropped engicam from filename since it aligned with imx6 engicam dts files naming conventions. arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-engicam-edimm2.2.dtsi | 82 +++++++++++++++++++ .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 21 +++++ 3 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8d49a2c74604..43783076f856 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi new file mode 100644 index 000000000000..f7870efd9dab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-edimm2.2.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +&fec1 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + max-frequency = <50000000>; + bus-width = <4>; + no-1-8-v; + pm-ignore-notify; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts new file mode 100644 index 000000000000..672aee1800c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "imx8mm.dtsi" +#include "imx8mm-engicam-edimm2.2.dtsi" +#include "imx8mm-icore-mx8mm.dtsi" + +/ { + model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", + "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +};