From patchwork Wed Dec 23 16:32:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 351537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A79DDC433E0 for ; Wed, 23 Dec 2020 16:34:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69C1C2229C for ; Wed, 23 Dec 2020 16:34:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725957AbgLWQeP (ORCPT ); Wed, 23 Dec 2020 11:34:15 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:62857 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbgLWQeP (ORCPT ); Wed, 23 Dec 2020 11:34:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1608741254; x=1640277254; h=from:to:cc:subject:date:message-id:mime-version; bh=YwYB+WOtpYKvAv4y2yVoR1fKm+XG11/A71tqgdjHX1A=; b=mmNtZy2o6UVot1qOWKHsYcfl6Oi6SvhoB40xIUqBuaqcqtJN1cqxc5VW oV/09KMatzntOZymFcfSTVNFvoP6Xctte9DE2mlHBe4P4jdtrYaQ9Y8Zb 4B9WLdSF8Sj/t0LlKq74f8NTWe6059gTRMy+fWUM8enNbiO0Vuycy7Kt+ CKFI1ax4etm+8C2munOroRVYepmT80GoX1amne0Us7Fn2ZN5Nt7Phjy2l B7EIkKOFsmM2WYdKPUu49OCkyJQEvborY+HTSW7IJrmZ2Sm97TYXL1N7g ho6q8lckSUti5RbZp4JKU5QmU7TcHULTwiJk3DuO/+PZCfEVih9cvBnid w==; IronPort-SDR: 14SSg/UVpgo6PP51cEFaFXIwH1I6WRqAcqXtiKgLqvn8rRLnIUH/uZRzOm6iGuy3ZrE+ra879C uuqNOyytORxQ8bB3MlhBiXWySxBjHZ0keV+Nv0aX9mpGrKnqtZXaHxCtd9kzrKhsqveEDIKeeX s+X/2x20eVZ9zRnXO1lmSmxjzd5OetCFTqu5QMFv8xgKvlgB0PjITtUNJ8B7aVXx/wP/ssBYdS 1eAmVFxFKtEQ9u5TUk7MfvKY6SZjTbuHdySA4z/gIJKxpqO1IvFMZISr8fpe6GBZFceG+SDaYZ cic= X-IronPort-AV: E=Sophos;i="5.78,441,1599548400"; d="scan'208";a="103833415" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:32:58 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:32:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:32:56 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 1/5] mbox: add polarfire soc system controller mailbox Date: Wed, 23 Dec 2020 16:32:55 +0000 Message-ID: <20201223163255.28992-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/mailbox/Kconfig | 12 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox-mpfs.c | 285 +++++++++++++++++++++++++++++++++ include/soc/microchip/mpfs.h | 51 ++++++ 4 files changed, 350 insertions(+) create mode 100644 drivers/mailbox/mailbox-mpfs.c create mode 100644 include/soc/microchip/mpfs.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 05b1009e2820..9aa18631c50b 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -153,6 +153,18 @@ config MAILBOX_TEST Test client to help with testing new Controller driver implementations. +config POLARFIRE_SOC_MAILBOX + tristate "PolarFire SoC (MPFS) Mailbox" + depends on HAS_IOMEM + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + help + This driver adds support for the PolarFire SoC (MPFS) mailbox controller. + + To compile this driver as a module, choose M here. the + module will be called mailbox-mpfs. + + If unsure, say N. + config QCOM_APCS_IPC tristate "Qualcomm APCS IPC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 2e06e02b2e03..77b79a0c384c 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o +obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) += mailbox-mpfs.o + obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c new file mode 100644 index 000000000000..b31317a8f44e --- /dev/null +++ b/drivers/mailbox/mailbox-mpfs.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERVICES_CR_OFFSET 0x50u +#define SERVICES_SR_OFFSET 0x54u +#define MAILBOX_REG_OFFSET 0x800u +#define MSS_SYS_BUSY -EBUSY +#define MSS_SYS_PARAM_ERR -EINVAL +#define MSS_SYS_MAILBOX_DATA_OFFSET 0u +#define SCB_MASK_WIDTH 16u + +/* SCBCTRL service control register */ + +#define SCB_CTRL_REQ (0) +#define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ) + +#define SCB_CTRL_BUSY (1) +#define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY) + +#define SCB_CTRL_ABORT (2) +#define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT) + +#define SCB_CTRL_NOTIFY (3) +#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY) + +#define SCB_CTRL_POS (16) +#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS) + +/* SCBCTRL service status registers */ + +#define SCB_STATUS_REQ (0) +#define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ) + +#define SCB_STATUS_BUSY (1) +#define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY) + +#define SCB_STATUS_ABORT (2) +#define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT) + +#define SCB_STATUS_NOTIFY (3) +#define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY) + +#define SCB_STATUS_POS (16) +#define SCB_STATUS_MASK GENMASK(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS) + +struct mpfs_mbox { + struct mbox_controller controller; + struct device *dev; + int irq; + void __iomem *mailbox_base; + void __iomem *int_reg; + struct mbox_chan *chan; + u16 response_size; + u16 response_offset; +}; + +static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) +{ + u32 status; + + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET); + + return status & SCB_STATUS_BUSY_MASK; +} + +static struct mpfs_mbox *mbox_chan_to_mpfs_mbox(struct mbox_chan *chan) +{ + if (!chan) + return NULL; + + return (struct mpfs_mbox *)chan->con_priv; +} + +static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) +{ + u32 index; + u32 *word_buf; + u8 *byte_buf; + u8 byte_off; + u8 extra_bits; + u8 i; + u32 mailbox_val = 0u; + u16 mbox_offset; + u16 mbox_options_select; + u32 mbox_tx_trigger; + struct mpfs_mss_msg *msg = data; + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + mbox_offset = msg->mailbox_offset; + mbox->response_size = msg->response_size; + mbox->response_offset = msg->response_offset; + + if (mpfs_mbox_busy(mbox)) + return MSS_SYS_BUSY; + + mbox_options_select = ((mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu)); + mbox_tx_trigger = (((mbox_options_select << SCB_CTRL_POS) & + SCB_CTRL_MASK) | SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK); + + /* Code for MSS_SYS_PARAM_ERR is not implemented with this version of driver. */ + + writel_relaxed(0, mbox->int_reg); + + if (msg->cmd_data_size) { + byte_buf = msg->cmd_data; + + for (index = 0; index < (msg->cmd_data_size / 4); index++) + writel_relaxed(word_buf[index], + mbox->mailbox_base + MAILBOX_REG_OFFSET + index); + extra_bits = msg->cmd_data_size & 3; + if (extra_bits) { + byte_off = ALIGN_DOWN(msg->cmd_data_size, 4); + byte_buf = msg->cmd_data + byte_off; + + mailbox_val = readl_relaxed(mbox->mailbox_base + + MAILBOX_REG_OFFSET + index); + + for (i = 0u; i < extra_bits; i++) { + mailbox_val &= ~(0xffu << (i * 8u)); + mailbox_val |= (byte_buf[i] << (i * 8u)); + } + + writel_relaxed(mailbox_val, + mbox->mailbox_base + MAILBOX_REG_OFFSET + index); + } + } + + writel_relaxed(mbox_tx_trigger, mbox->mailbox_base + SERVICES_CR_OFFSET); + + return 0; +} + +static inline bool mpfs_mbox_pending(struct mpfs_mbox *mbox) +{ + u32 status; + + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET); + + return !(status & SCB_STATUS_BUSY_MASK); +} + +static void mpfs_mbox_rx_data(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + u32 *data; + u32 i; + u32 response_limit; + + data = devm_kzalloc(mbox->dev, sizeof(*data) * mbox->response_size, GFP_ATOMIC); + if (!data) + dev_err(mbox->dev, "failed to assign memory for response\n", -ENOMEM); + + response_limit = mbox->response_size + mbox->response_offset; + if (mpfs_mbox_pending(mbox) && mbox->response_size > 0U) { + for (i = mbox->response_offset; i < response_limit; i++) { + data[i - mbox->response_offset] = + readl_relaxed(mbox->mailbox_base + MAILBOX_REG_OFFSET + i * 0x4); + } + } + + mbox_chan_received_data(chan, (void *)data); + devm_kfree(mbox->dev, data); +} + +static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data) +{ + struct mbox_chan *chan = (struct mbox_chan *)data; + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + writel_relaxed(0, mbox->int_reg); + + mpfs_mbox_rx_data(chan); + + mbox_chan_txdone(chan, 0); + return IRQ_HANDLED; +} + +static int mpfs_mbox_startup(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + int ret = 0; + + if (!mbox) + return -EINVAL; + ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan); + if (ret) + dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret); + + return ret; +} + +static void mpfs_mbox_shutdown(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan); + + devm_free_irq(mbox->dev, mbox->irq, chan); +} + +static const struct mbox_chan_ops mpfs_mbox_ops = { + .send_data = mpfs_mbox_send_data, + .startup = mpfs_mbox_startup, + .shutdown = mpfs_mbox_shutdown, +}; + +static int mpfs_mbox_probe(struct platform_device *pdev) +{ + struct mpfs_mbox *mbox; + struct resource *regs; + struct mbox_chan *chans; + int ret; + + mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL); + if (!chans) + return -ENOMEM; + + mbox->mailbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); + if (IS_ERR(mbox->mailbox_base)) + return PTR_ERR(mbox->mailbox_base); + + mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s); + if (IS_ERR(mbox->int_reg)) + return PTR_ERR(mbox->int_reg); + + mbox->irq = platform_get_irq(pdev, 0); + if (mbox->irq < 0) + return mbox->irq; + + mbox->dev = &pdev->dev; + + chans[0].con_priv = mbox; + mbox->controller.dev = mbox->dev; + mbox->controller.num_chans = 1; + mbox->controller.chans = chans; + mbox->controller.ops = &mpfs_mbox_ops; + mbox->controller.txdone_irq = true; + + ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller); + if (ret) { + dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n"); + return ret; + } + dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n"); + + return 0; +} + +static const struct of_device_id mpfs_mbox_of_match[] = { + {.compatible = "microchip,polarfire-soc-mailbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match); + +static struct platform_driver mpfs_mbox_driver = { + .driver = { + .name = "mpfs-mailbox", + .of_match_table = mpfs_mbox_of_match, + }, + .probe = mpfs_mbox_probe, +}; +module_platform_driver(mpfs_mbox_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS mailbox controller driver"); diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h new file mode 100644 index 000000000000..4a9d335154a1 --- /dev/null +++ b/include/soc/microchip/mpfs.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Microchip PolarFire SoC (MPFS) mailbox + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#ifndef __SOC_MPFS_H__ +#define __SOC_MPFS_H__ + +#include +#include + +struct mpfs_sys_controller; + +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + u16 response_size; + u8 *cmd_data; + u16 mailbox_offset; + u16 response_offset; +}; + +#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes); + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node); + +#else + +static int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + return -ENOSYS; +} + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node) +{ + return NULL; +} + +#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ + +#endif /* __SOC_MPFS_H__ */ From patchwork Wed Dec 23 16:33:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 352051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1570C433E0 for ; Wed, 23 Dec 2020 16:34:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C1632226A for ; Wed, 23 Dec 2020 16:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725988AbgLWQeX (ORCPT ); Wed, 23 Dec 2020 11:34:23 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:10493 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbgLWQeW (ORCPT ); Wed, 23 Dec 2020 11:34:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1608741262; x=1640277262; h=from:to:cc:subject:date:message-id:mime-version; bh=h1uU/xZB+u65R9PycjaTtcUTsDJER2E6v6lRjGcr7MY=; b=BVwbE267a1p/y1SrZLus0qaBJuY0VulufgTMIni6buwrw6+bxkHrrPQv A/CazTIk3KOhXCL1hnNBsQFMSDtOUrP0qW4ylr/e7dznGIuRvtFUbQorA qzmDyxE7VEju5JMdryW5bzwJVdOwMZIITc9qjsu09YpxrvNhuU7VF07BM 7D15558H6EVunocHIZRSAbQC4/APo7hmzqyWpJxIK6UGAU3PFgtEDLibg UPWeeS8GzsMZdbbbURSFzpfUT4aSmOD+Y3HvnE18AnEzIcSR5ncDyQSGE Er+RDYTDdIT6aOHPJvG8MbDLANWfJs2qIshPdxK42TuhdD3eHzQzrPQ8U w==; IronPort-SDR: oh4ujwtW0+2ocjPCLo+sBsWgV7rQeYWKTsmjw3cPi2gPsVn361FffOmr+D6Whuw8TlodKwcVb0 hgZk+Dl2pxIYGCET6DDNaIOiaVFMgwSCeVS792woC7SBNAcuco4CfXaE3VfqwmGE/HUQX/svGq ov0ns3IFfSTb/WmsS7WQ1OAGn4I21LfIDo0xeybb0ZTeXQzk74Q4AtpRuOch4s6wzdB2ObC6G4 sTMXVWXumOyi+29LoOnSyVoEgeTQXCu/rHkrWfgDD14Z0fxjFeWZJ5EtkeURZlXYC/wV79WcfE Yv0= X-IronPort-AV: E=Sophos;i="5.78,441,1599548400"; d="scan'208";a="108748448" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:03 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 2/5] dt-bindings: add bindings for polarfire soc mailbox Date: Wed, 23 Dec 2020 16:33:02 +0000 Message-ID: <20201223163302.29057-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../mailbox/microchip,mailbox-mpfs.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml new file mode 100644 index 000000000000..c5b126c6fb66 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,mailbox-mpfs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) mss mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox + + reg: + items: + - description: mailbox data registers + - description: mailbox int registers + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + mbox: mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + interrupt-parent = <&L1>; + interrupts = <96>; + #mbox-cells = <1>; + }; + }; From patchwork Wed Dec 23 16:33:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 351536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F31AC433E0 for ; Wed, 23 Dec 2020 16:34:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D69C72229C for ; Wed, 23 Dec 2020 16:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726012AbgLWQea (ORCPT ); Wed, 23 Dec 2020 11:34:30 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:37429 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbgLWQea (ORCPT ); Wed, 23 Dec 2020 11:34:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1608741270; x=1640277270; h=from:to:cc:subject:date:message-id:mime-version; bh=aPhRJJpl+JraMj58CcbSvP1w+OJ7MRJUj8wOChAJIAA=; b=di5U/MHmka1mnwu9iAQu3vF/DrU9D0vFgprnTn3JtiGVTIBflK2BynB7 YDKInDLIjmiCfWjhOmQmIlFU872E7eLiBcIpSVo5NwTo6VnYoIGjm7x3/ ebBDk3aXk1FOvGktFzFgMZJeeeVraw2j842o0CsCy4oS1cmCIDjGGFcII p10ngp1Ixg6mx2m56ROkepy1rxRm6o6un0AqsP2EUwUQ5Do6CImCfoYjS awlSYDumjVQN61039VHJI4C7U4XNm+e2zi463AYBtCQzCM/DSPrysieML hwgHZIL5eXGDUIvizv1hAnT+YBhtBvwQM8OBGey8j4wcO1XpUTUbG5MrY Q==; IronPort-SDR: qqnan1vkMrwyzNmQZ/kgmxSwjGEO1jH0XJDETCV6lpkrnxFkg/2gnF7lzYcLsKYA+sOl+z5dHH Oo1D+UWO8UyM+KSDWQqzbX1w+7Ti5oNouUiqchfCJDMaUkczwcjQowOgJ7w6kIVh1N2wpGeZ+X 2yEQd9Zoj4xBRa+cbiRQMzk3xunBwzsfJkghUf8ZeP8GfxUifqRehIZYE2ayCJ7PBPXwAz/NoX JONtiUp7qVoyTizvJ7Yrqn5aTJcEjosPtZf1V8+lqML4keo6SGElMXtopbGL23MdnzY3j9/+9S oZU= X-IronPort-AV: E=Sophos;i="5.78,441,1599548400"; d="scan'208";a="103299252" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:15 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:11 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 3/5] soc: add polarfire soc system controller Date: Wed, 23 Dec 2020 16:33:10 +0000 Message-ID: <20201223163310.29122-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-sys-controller.c | 127 ++++++++++++++++++++ 5 files changed, 140 insertions(+) create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..22cb097bcbdc 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..fb084cf2d12e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..eb656b33156b --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config POLARFIRE_SOC_SYS_CTRL + tristate "POLARFIRE_SOC_SYS_CTRL" + depends on POLARFIRE_SOC_MAILBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say N. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..14489919fe4b --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c new file mode 100644 index 000000000000..e8b44beb5ac5 --- /dev/null +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + u32 enabled; + void *response; + u16 response_size_bytes; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + int ret; + + mpfs_client->response = response; + mpfs_client->response_size_bytes = response_size_bytes; + + mutex_lock_interruptible(&transaction_lock); + + reinit_completion(&mpfs_client->c); + + ret = mbox_send_message(mpfs_client->chan, msg); + if (ret >= 0) { + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) { + ret = 0; + } else { + ret = -ETIMEDOUT; + dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout"); + } + } else { + dev_err(mpfs_client->client.dev, + "mpfs sys controller transaction returned %d\r\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *mpfs_client = + container_of(client, struct mpfs_sys_controller, client); + + memcpy(mpfs_client->response, (u8 *)msg, mpfs_client->response_size_bytes); + + complete(&mpfs_client->c); +} + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *mpfs_client; + + mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL); + if (!mpfs_client) + return -ENOMEM; + + mpfs_client->client.dev = dev; + mpfs_client->client.rx_callback = rx_callback; + mpfs_client->client.tx_block = 1U; + + mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0); + if (IS_ERR(mpfs_client->chan)) + return dev_err_probe(dev, PTR_ERR(mpfs_client->chan), + "Failed to get mbox channel\n"); + + init_completion(&mpfs_client->c); + + platform_set_drvdata(pdev, mpfs_client); + + dev_info(&pdev->dev, "Registered MPFS system controller driver\n"); + + return 0; +} + +struct mpfs_sys_controller * +mpfs_sys_controller_get(struct device_node *mss_node) +{ + struct platform_device *pdev = of_find_device_by_node(mss_node); + + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + {.compatible = "microchip,polarfire-soc-sys-controller", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver"); From patchwork Wed Dec 23 16:33:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 351535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326B7C433E0 for ; Wed, 23 Dec 2020 16:34:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F15932226A for ; Wed, 23 Dec 2020 16:34:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726072AbgLWQen (ORCPT ); Wed, 23 Dec 2020 11:34:43 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:10493 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbgLWQen (ORCPT ); Wed, 23 Dec 2020 11:34:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1608741282; x=1640277282; h=from:to:cc:subject:date:message-id:mime-version; bh=tjw0tl7bjtaxEZV9EBKLzBZuGR484w4552aqADq9SFc=; b=H+RDkM8owj8SQUUT00iN6VeTMqdY4zRJJjRfR76zX7EndWBdagNbeiM1 Kny+yIOx7S4E1NexiOXq1q9PlDgmYvINyx7NnbFNr7WypGpLFbwQ4d2dr OhdVs+ZgcqzxuMypCCwrbNFMBRLkw3pHDRnxXYUqUrdymfbOCybNoR574 j3oYDrctnNYcL5+MniEriE83bPgFluVkSWYATvBj19m7ioNuK1vd3ZAw2 2+e+fwt0Plo1PdekdB1TMx4m9lrlgRaLEEHTB9/n4ape7BcgeEtGOMzzh SddOpLCKmu6a7B0hdMLiWIQR3SgMAaWviQKy/JmviEmnye+0oRt+mEGqF w==; IronPort-SDR: wytZxmg8k8NTQAaVcd0srjIc7fVwHONouyyTd42iwJ2nq88dbriRXgRY5XZ6aH8UrdNsiPtJDx wD4SUYQvLiKqa2uBYc63ZpteEWgYweFQw3eTtGAuTNDBauVJzE1cP8IePbOM2fse2LZGCogNRw GF/6f85GFC8k4cZr309Pr3oOFjQ9JDV5kb2FUew6bTos2SEFEnuL6mcUgG15JpyQ4Zpu7HrRku FFtWMdQDEnTWNdm+5hIxF3AdXzuqOJEoS+ZVnrA9wVfd7lA7mL+VeYIyzPynh1TMCabWnOykoz VME= X-IronPort-AV: E=Sophos;i="5.78,441,1599548400"; d="scan'208";a="108748466" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:19 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:17 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 4/5] dt-bindings: add bindings for polarfire soc system controller Date: Wed, 23 Dec 2020 16:33:16 +0000 Message-ID: <20201223163316.29186-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../microchip,mpfs_sys_controller.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml new file mode 100644 index 000000000000..60fde1925910 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs_sys_controller.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) system controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-sys-controller + + mboxes: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + phandle and index of the mailbox controller device node. + See: ../mailbox/mailbox.txt for more information. + maxItems: 1 + +required: + - compatible + - "mboxes" + +additionalProperties: false + +examples: + - | + syscontroller: syscontroller { + compatible = "microchip,polarfire-soc-sys-controller"; + mboxes = <&mbox 0>; + }; From patchwork Wed Dec 23 16:33:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 352050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CB09C433E0 for ; Wed, 23 Dec 2020 16:34:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE8512226A for ; Wed, 23 Dec 2020 16:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726047AbgLWQeg (ORCPT ); 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d="scan'208";a="103833490" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:28 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:25 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 5/5] MAINTAINERS: add maintainers for polarfire soc mailbox driver Date: Wed, 23 Dec 2020 16:33:25 +0000 Message-ID: <20201223163325.29270-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add the mailbox driver to the existing MAINTAINERS entry for the polarfire soc Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5da634ea3adb..1e9b08ae1266 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15016,6 +15016,7 @@ M: Lewis Hanly M: Cyril Jean L: linux-riscv@lists.infradead.org S: Supported +F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h