From patchwork Tue Dec 22 07:05:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346612 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095866jai; Mon, 21 Dec 2020 23:08:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJzMPPTKc3y3VlbJrgUuzpUVUOV474urCGfqE7h2tWGW1EFBULH5k03uvq6nm5gcwq6oW9LY X-Received: by 2002:a17:906:a008:: with SMTP id p8mr5680510ejy.117.1608620881242; Mon, 21 Dec 2020 23:08:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620881; cv=none; d=google.com; s=arc-20160816; b=jV1Wb0yH24VdfOpkb98PXhsWOFI7W4lrlcUnesUh6pCSS+lu1orj/3kpIUSfz8IRnI gKD6F+nDGMswwe9HV0k5VafvjhGznTg10K+KIyD+krOaagPdyYfkwKcPA9r+EFMXraf4 P3KYnJTtLMW4uHh34ye6wAkxTXg+5sNIQdOhMw0+r6U6VCqtFrILb1j8hfcb2iew3N1I RHu7Pc/2SWoDLOFG73r6pu9xqrunfEJzObPR8ZvaL4cODweJbt1m/CEzZykCws4+cH/h ItBl4Kt0LgLkjvsOro/u80ONR9Vv0D6vq5r5OBgxyHNUSrUHsr4HWhbxHVx7ahuAzrIA Z80g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=HHTvmMjtTJRPNFpN3zkcx0PIiGXY1RMP1eK0a1ouBO4=; b=GO/YZyGb1jdW0NHBcnp2m/OGXRdN7VV1jk+qNGMwTlBgHnUVkXDVlJyGbz/55VEStJ LouqAwE+dpcs8zpnkgAZ+F9rSWtEj3TAZqGVkR/rBf3XpVerJNaiem9rdpCQlLoqfSQs GiNlvzuBuayKdi2f5PGz4D+MY5VFT0NhYhgEhgCyqnDYR5wfN+MYyDpnfUMSkYIbdEj8 s24EtDvjzmE6Rv8eFkCDRLLl6uqr+vmhU7zHT+LhzzuB1E4N8wmZOvXjlPFUPE5nZQtJ Sy4S5CikZ1ks5dmjy1LKbKFJ6Bb90Ub7PdhN1aMv1D8ujW3UCWRG2fttbOyOsTF3y/mR 6fEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aGAEk04v; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.08.01; Mon, 21 Dec 2020 23:08:01 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aGAEk04v; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726413AbgLVHHS (ORCPT + 7 others); Tue, 22 Dec 2020 02:07:18 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53844 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726396AbgLVHHR (ORCPT ); Tue, 22 Dec 2020 02:07:17 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75UJO064018; Tue, 22 Dec 2020 01:05:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620730; bh=HHTvmMjtTJRPNFpN3zkcx0PIiGXY1RMP1eK0a1ouBO4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aGAEk04v60w1DV9ToCDUcSTdb5TacFqifX2ky8qkVMtFrePrgzSzDVvnqAZm6sMrz RTq8jDtEle+Yg3A/g0f3+forpgz33cttvCa9F9l3gX1phah2abQxvEaQwjsAbbVkCQ d4y8rxDY4JQ2hlU+px4YBPd9xpzlG+pMr/a3pDos= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75UFo014639 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:30 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:30 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:30 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7A050344; Tue, 22 Dec 2020 01:05:27 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel , Subject: [PATCH v2 01/14] phy: cadence: Sierra: Fix PHY power_on sequence Date: Tue, 22 Dec 2020 12:35:07 +0530 Message-ID: <20201222070520.28132-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I Cc: # v5.4+ --- drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 26a0badabe38..19f32ae877b9 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy) u32 val; int ret; + ret = reset_control_deassert(sp->phy_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY out of reset\n"); + return ret; + } + /* Take the PHY lane group out of reset */ ret = reset_control_deassert(ins->lnk_rst); if (ret) { @@ -616,7 +622,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - reset_control_deassert(sp->phy_rst); return PTR_ERR_OR_ZERO(phy_provider); put_child: From patchwork Tue Dec 22 07:05:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C99CC43142 for ; Tue, 22 Dec 2020 07:07:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F061B2313F for ; Tue, 22 Dec 2020 07:07:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726065AbgLVHGX (ORCPT ); Tue, 22 Dec 2020 02:06:23 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53848 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726048AbgLVHGX (ORCPT ); Tue, 22 Dec 2020 02:06:23 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75Z4q064046; Tue, 22 Dec 2020 01:05:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620735; bh=NTvLEMflAztKktqpjh6r18tuK30GE4lQZASY4qEqAXs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nMUkQmlt12wpi9HBofab2sgxsizK5uNll0fcpnyzp/Zpcuu3z9KmI8Uks2fDqepYT cpYakNo8vpju8nB3p5uhqLnpm2Z+7kHry6yxT3MegI2SwXym6JxTDPx3PZZzEplUMs XDgN2b1iRbuIovGysQKcdoSwGnLs3y1PGb9ra+KM= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75YfU011237 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:35 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:34 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:34 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7B050344; Tue, 22 Dec 2020 01:05:31 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel , Subject: [PATCH v2 02/14] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Date: Tue, 22 Dec 2020 12:35:08 +0530 Message-ID: <20201222070520.28132-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Invoke wiz_init() before configuring anything else in Sierra/Torrent (invoked as part of of_platform_device_create()). wiz_init() resets the SERDES device and any configuration done in the probe() of Sierra/Torrent will be lost. In order to prevent SERDES configuration from getting reset, invoke wiz_init() immediately before invoking of_platform_device_create(). Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I Cc: # v5.10 --- drivers/phy/ti/phy-j721e-wiz.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c9cfafe89cbf..a75433b459dd 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -947,27 +947,24 @@ static int wiz_probe(struct platform_device *pdev) goto err_get_sync; } + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_wiz_init; + } + serdes_pdev = of_platform_device_create(child_node, NULL, dev); if (!serdes_pdev) { dev_WARN(dev, "Unable to create SERDES platform device\n"); ret = -ENOMEM; - goto err_pdev_create; - } - wiz->serdes_pdev = serdes_pdev; - - ret = wiz_init(wiz); - if (ret) { - dev_err(dev, "WIZ initialization failed\n"); goto err_wiz_init; } + wiz->serdes_pdev = serdes_pdev; of_node_put(child_node); return 0; err_wiz_init: - of_platform_device_destroy(&serdes_pdev->dev, NULL); - -err_pdev_create: wiz_clock_cleanup(wiz, node); err_get_sync: From patchwork Tue Dec 22 07:05:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346608 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095778jai; Mon, 21 Dec 2020 23:07:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJz1AVZDdmMAJAN4Yp+bFzOKbPSC2xQGdBgDgvWSdFyrh15hz5VT0OfTYKzYxnsDybww3e0w X-Received: by 2002:a05:6402:d09:: with SMTP id eb9mr18932213edb.71.1608620874062; Mon, 21 Dec 2020 23:07:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620874; cv=none; d=google.com; s=arc-20160816; b=ge1YJthdmdwz6m8ppwo4ZmuUZB13RVNnaHuSzOlBVuckRNx0RX3kMuvXXbT0IYImwO IUB0T2ifJCkcI0EkM0SFmuzNNqNqsBE6zwMTaKQMnucBiDEiJT/uZv+vtgqc3AXD8u8g L/HaEQrtiX+pLXwql5MDnW6mPbrXWDBEP0bz6wj72nbo4fVgmqFFWYJbc9GylR4CFlPW CO8bVlu2ugzjHqWb9mOgG5ppKP5XvSbSxGgRbjePugCgrDWpsYWUT25i7oUT9Vf6VakM ymfuw11jil11+NvqEpGARYnGhA8+YlDtCN3CzDKQlXLSyH30iUOBA7TbWtG+/VHsi1IF tPBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; b=r27bfRcI7jQaCKGP4mTWVqXXEYX1M2H8Rtopm4FRjshv7g5CwAYypEKNw8d0fF+J77 BsBZrpYarmWHl3frcnfrkEcI5EMsUcs4Iqa788DxxHMUEciyTmcEYRgArhFwzGRqPLxH izaVXo1FLPNQAI/zs/QnTnZKDwY0RgZWjAbxHd61VMFyy9+5N2JTmCpp7VM7h6zJmefu DW7i1yoDkqZc75P3HankzfgimBFeq99Sp2um5eIMLVNbz80BkRWzRa0H/EhMLSpwd33d hcm9405Ug8y/rquyfXZNNUc4s5Qh7IjSKmZD1RI/pY+CPfY0rt0JdU0Dm6Cot4CCXECG 16TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wB3bd2Tq; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.07.53; Mon, 21 Dec 2020 23:07:54 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wB3bd2Tq; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726127AbgLVHG3 (ORCPT + 7 others); Tue, 22 Dec 2020 02:06:29 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59018 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726048AbgLVHG3 (ORCPT ); Tue, 22 Dec 2020 02:06:29 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75cS7034323; Tue, 22 Dec 2020 01:05:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620738; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wB3bd2TqqvmWQaiF/h98pJkdAfL6nLyi72skIqQJ5qpL4ivgPhA2H8+pF6zVC7Vsh iD5oqi/icPD+FFbG8zR9054lpO2wGmIsUTuNmugsvcGW7LByXvkfeWX10L8MXwcV5w cEclOT4L709MABhlXUv/HpT7CDVP2lSLdqaOSG3Q= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75c8J011299 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:38 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:37 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:38 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7C050344; Tue, 22 Dec 2020 01:05:34 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 03/14] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Date: Tue, 22 Dec 2020 12:35:09 +0530 Message-ID: <20201222070520.28132-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the PLLs within SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-sierra.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index d210843863df..f574b8ed358c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -49,12 +49,14 @@ properties: const: serdes clocks: - maxItems: 2 + maxItems: 4 clock-names: items: - const: cmn_refclk_dig_div - const: cmn_refclk1_dig_div + - const: pll_cmnlc + - const: pll_cmnlc1 cdns,autoconf: type: boolean @@ -107,6 +109,58 @@ patternProperties: additionalProperties: false + "^refrcv1?$": + type: object + description: | + Reference receivers that enables routing external clocks to the alternate + PLLCMNLC. + properties: + clocks: + maxItems: 1 + description: Phandle to clock nodes representing the input to the + reference receiver. + + clock-names: + items: + - const: pll_refclk + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^pll_cmnlc1?$": + type: object + description: | + SERDES node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + clock-names: + items: + - const: pll_refclk + - const: refrcv + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + required: - compatible - "#address-cells" @@ -130,10 +184,39 @@ examples: reg = <0x0 0xfd240000 0x0 0x40000>; resets = <&phyrst 0>, <&phyrst 1>; reset-names = "sierra_reset", "sierra_apb"; - clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>, <&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; #address-cells = <1>; #size-cells = <0>; + + serdes_refrcv: refrcv { + clocks = <&pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_refrcv1: refrcv1 { + clocks = <&pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_pll_cmnlc: pll_cmnlc { + clocks = <&pll0_refclk>, <&serdes_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc>; + assigned-clock-parents = <&pll0_refclk>; + }; + + serdes_pll_cmnlc1: pll_cmnlc1 { + clocks = <&pll1_refclk>, <&serdes_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc1>; + assigned-clock-parents = <&pll1_refclk>; + }; + pcie0_phy0: phy@0 { reg = <0>; resets = <&phyrst 2>; From patchwork Tue Dec 22 07:05:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346607 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095771jai; Mon, 21 Dec 2020 23:07:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJzv/pejwhGxl+daCtWq6QnAdDAjQx2l/bC/ZoUFvwhNH/RENxPsZ826GNOX8zQJsI35S54Y X-Received: by 2002:a17:907:6e6:: with SMTP id yh6mr18943676ejb.512.1608620873115; Mon, 21 Dec 2020 23:07:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620873; cv=none; d=google.com; s=arc-20160816; b=TAFWheBjuIHeJMyeW2YdcP7F3ax4qIngLXTeT8TlOXtlBqyewvQNoO6R68GxPo09kD +Xh/EPHBNcaGNNYL/6HfMpG5sueBkvVLiCrnZHsovZxM8Rn10o88oS4zmUZwRljUQlqW m2rUlVqetsYb/Ufk72fxlPOxl0TQBklxXGkBf/kTTXO+6F1u6E2LPlW4FHb9GtbuLChT AR9SjV7vWlUu/j6lXGHaw110AtKK1wMkMxCm6zCMs9RjoIPVplsNkrfb+rLYz/Oe88C3 ZImo/Vqx88/tMckrXIvVVhp9wA5M/fbNoDMHwzLBe/IFkuqsY2XM9raKszptw8dunKL8 cGvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FjCTHLq/sEj9KXmxRwSejCjWFaAdBEX/mJW7iTNR8qs=; b=sWg/RH2bAhThX2n/LNx0uyUpaUUf0M7pjyFmUi4ENhY0jBSOKBu7WME24Mgb0SxRI5 6EtkTef86VZtIYeWoegVp8zaU7ZUlh3tU4K0szGIaGCgXBQawVIQr8Ln7TbsNjq1kiGO sjw4GxTM9irquz/kwsp8oEFPzilcbdjqVDcuv0Mp8ayk7kbTGyvZAKWdxOTnHxJ5adta dn2H740DvWVcOQdPYvxrsWB3PdMP0FBjEL28+BwdI4hc350wmIsWwIB6MRHw6070g+R2 hUehpeM8UAS5rORT+hlpUhnUMUlrthDrYeZEM/czSIwGQDwsdjKZPeIlcX89RZ2Kv/fw qDcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kqL+3iEV; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index a75433b459dd..2a03191eac64 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -787,6 +787,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) u32 reg, num_lanes = 1, phy_type = PHY_NONE; int ret, i; + if (!(of_node_name_eq(subnode, "phy") || + of_node_name_eq(subnode, "link"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { dev_err(dev, From patchwork Tue Dec 22 07:05:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346605 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095750jai; Mon, 21 Dec 2020 23:07:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJyHAsd1Y4J4egmgbDwwLSP7Oo2agedE9z/Vfz0FsbZtofPYB1OXgeDYKSszxDIa7uVjouU1 X-Received: by 2002:a17:907:3312:: with SMTP id ym18mr18805246ejb.437.1608620870119; Mon, 21 Dec 2020 23:07:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620870; cv=none; d=google.com; s=arc-20160816; b=CNcSQzxOW820zruSNkLAabKkuJWAZjDZNrHfHL1TR/Ze2qONO3NMIwiQFjlRvJA4Sz tMRnMBK5mcWpWTRbBsXF0rqjPuCcebh+X7Hhirsm0ChJcOFwN/dgxeA1jCox4WNwOWxo TvRAxhBgx3j40kut4MyI4UYdMaUwlaU7W0JL2shPj2gSJv7D3JpXI6dhRF1mESTSfvuw N6Q96nCpkwW+JW6H/iIoPXAS/MPot7iwtfX0KJKGJ72EQqMQW1NuBaPmOVuvybc4XlB7 /Y4hmp85jebbYJl7ImJE0P4mbhEfKXs7IhboH9L5va8pwOc6X12MeGy3kGu0NbVKaytr ylpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=VxF8kGigCKqkh77tBFluIHDcpsujh9oOUvSPK2P6qiw=; b=MIcI2icEoLB8M+/JzJYhczAub7pwy0lfRUM6R86kK0fO7cyPuwtYwQDo4b9vBKS6WW EHQkQNK7KMNRjBJ6RcYVx6gt8XC+LN/bC1Zs7hHcnc5z/jxTJHJRiYoRd4/JPZceVa6D Uy+9NNGi5JqAX2+MZbIbUZF91HH5lK4wiSZ6Ki9qV9uMjdr6XILBbqoDy9jNW5nulRQw iySyJ24XgNmRJue+PYCppp1lfP5Rp2BWIpdvIm77RyiLoEE89EoERHR41iZHk3dEClEp kfXlKOvcjgO+slfg39lw6S5yH9hCMPSvsf3P64WyNNYEKDIAysGK362QF6uDTig9AnIJ SQ1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RLlwWNvR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.07.49; Mon, 21 Dec 2020 23:07:50 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RLlwWNvR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726204AbgLVHGc (ORCPT + 7 others); Tue, 22 Dec 2020 02:06:32 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53900 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726123AbgLVHGc (ORCPT ); Tue, 22 Dec 2020 02:06:32 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75j9t064152; Tue, 22 Dec 2020 01:05:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620745; bh=VxF8kGigCKqkh77tBFluIHDcpsujh9oOUvSPK2P6qiw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RLlwWNvRkf1IPPSBFf7xqnQZC1ZMudC+O9gjmx06EtgwguWYUsqUtOGiAPfxHo+JF fuMoOXCMLsMx7fOQ9OrXLiQv5rNnLgR0w9i+jRnOVooyj0M/JoG1a1dpGLQnRZJBBs 66wsbwZdSccm7V1vSRCIF2k2l4sKRaq6eigUZZvA= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75jZ3014866 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:45 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:44 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:44 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7E050344; Tue, 22 Dec 2020 01:05:41 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 05/14] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Date: Tue, 22 Dec 2020 12:35:11 +0530 Message-ID: <20201222070520.28132-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 19f32ae877b9..f7ba0ed416bc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -577,6 +577,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dn, child) { struct phy *gphy; + if (!(of_node_name_eq(child, "phy") || + of_node_name_eq(child, "link"))) + continue; + sp->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); From patchwork Tue Dec 22 07:05:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346615 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095913jai; Mon, 21 Dec 2020 23:08:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJxtZAloPWq4vA8Uat2UU+WPPF+6Qk4YOx95tOwEXpf21vOGHIpHU2OcBW2aDJCss6rUcZTd X-Received: by 2002:a17:906:ce23:: with SMTP id sd3mr18644702ejb.69.1608620884437; Mon, 21 Dec 2020 23:08:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620884; cv=none; d=google.com; s=arc-20160816; b=0S7EMIaDB/leuGdkcG2K7NWnNvDfmo0gEzw0RQvlj4RdYL9qlW3ALeW1N+NunGH22Y OPKGTVozIGFSKZ+WAT9RfmILnmZ8w2gIub1m4n5sWDS9yyB7zux/Qq+oJuUSfSheLbV2 o6rJkkeR+Zs/I52JGawf6xY+nj5rIp+Cn86XGPdgax4ihWBrZmfsILnb8lMl9IV6hCr+ VhLACYA4e3UH1bbQeNlSR0FMM7B3teSqlRwkz8kyHbFxXUkaEmOfS9MyycwHWUDI4Okm 3wQVfB2WAEDL1LYJSa2yDi1q5f8JBpM6L9xfI2GAcZHqVprweO6yHabgNn0H+IqKMXr7 EQHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1m1jaw1QKhWt1my5TiZgSyHmcvod41lJIai7xVZR3M8=; b=BqFQh9T7FAsmGKRfo6Ve4oL9i3CfT7AsZM5oYFCBEOkkIotAcpK7ZW/IPTV9H6MHv+ Ka+zMqxWiqh79fNzHu0LfPmyJSq91F2g+iI7ZAr5lDIel525HFlrRoq5MK2hRnCwRq8J Ti6Wk4Ou9i+8PyEyS4LpZn9P/EnSMke9cnjRdGc431Zbek36i7EmHlqTt31S0dvi5PQH xjsPlNlUfDRK7w8Zu7I1m/tItruLHm8SZDfjByVbcuraBk+DlOlAp1FRH7iGbwAXKjA/ PNhs6I1llh8Nrw/rPvBWh96BebvXPF6CaRGpSrpTKle/LgN8WlwmxP4+MP9IHFDcubNu IyJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="k2Lv/8JY"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.08.04; Mon, 21 Dec 2020 23:08:04 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="k2Lv/8JY"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726555AbgLVHHe (ORCPT + 7 others); Tue, 22 Dec 2020 02:07:34 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53952 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726475AbgLVHHd (ORCPT ); Tue, 22 Dec 2020 02:07:33 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75mCP064163; Tue, 22 Dec 2020 01:05:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620748; bh=1m1jaw1QKhWt1my5TiZgSyHmcvod41lJIai7xVZR3M8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k2Lv/8JY+DRFPatcb0Q0iwAJ7Z0JMHq5gizKtoD0pxszczmbmlqEPPt8iKmW+rg8E 5gEIglPMIe71MzlxKLEO2M/Y9ZnOYAhR7uNDQ7N9MI7u4rGLy2N7EoYKv5PsiP0Nnv 6MVh7voLFA6fnLrL2My2/AtO8xm7CYsWw8hywXQw= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75mth031994 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:48 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:47 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:47 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7F050344; Tue, 22 Dec 2020 01:05:45 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 06/14] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Date: Tue, 22 Dec 2020 12:35:12 +0530 Message-ID: <20201222070520.28132-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++--------- 1 file changed, 35 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index f7ba0ed416bc..7bf1b4c7774a 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -477,6 +477,38 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(clk); + } + sp->clk = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk_dig_div = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1_dig_div = clk; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -487,7 +519,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) unsigned int id_value; int i, ret, node = 0; void __iomem *base; - struct clk *clk; struct device_node *dn = dev->of_node, *child; if (of_get_child_count(dn) == 0) @@ -524,11 +555,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get_optional(dev, "phy_clk"); - if (IS_ERR(sp->clk)) { - dev_err(dev, "failed to get clock phy_clk\n"); - return PTR_ERR(sp->clk); - } + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + return ret; sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); if (IS_ERR(sp->phy_rst)) { @@ -542,22 +571,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->apb_rst); } - clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk_dig_div = clk; - - clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk1_dig_div = clk; - ret = clk_prepare_enable(sp->clk); if (ret) return ret; From patchwork Tue Dec 22 07:05:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346606 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095759jai; Mon, 21 Dec 2020 23:07:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJx78izOfJnBVWlk6XMNHFNXp6elUxwNMegRgEutDyXQqTsZs+mSfoqAPsXYtslARa7u7VYU X-Received: by 2002:a17:907:c29:: with SMTP id ga41mr11855676ejc.28.1608620871756; Mon, 21 Dec 2020 23:07:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620871; cv=none; d=google.com; s=arc-20160816; b=q9rOfi2I59JMLVKCUsNdCUPjMa3YFnWLaXVyQ3UROXJ4dWV37U4MF3BGezTBbbSfRz pSSttn64XA9ATJ5M5kUG+VHBWKFfBVIgZuZg7gNDFxB6KZmQxX8+F0t9pFbY/ze9e6Sb 87uuC6i8z4Niwdwp3osSFwvlfoM0ahqmN0Yy6Q/O8sr3ThHPlWTen7b3clkJc2+WKtvn 8ab7KM0IKDMYcwy1x35pUgWMig4s0tQKjDziAsT0N0OUdOEV74DZL8pNPGMHAlxGYwXT Fiby9r6innoVJ8h3whx72tzLsl4jwo8je8ESKEkH+uFQScDGD+MWx4cl51qv1o2m8NJ3 i2ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+nl8LicT//augqm13+dqzPO4Zt/8O9Pq6Zxz1AFAlx0=; b=Hh/o0c7iKSfhH1iC+IblA59qbSoVaFzxCHQ6tJDVfT7DCbGTl0v4ECwWTb6GbEFqX5 mVbhzOJ+L9UnJQDKaQtjP4gRuQIm42IPdtuEiDCn9tHDXZP+NBQTxGsEuOK8YD87lDgp 1skAVY3MIo2Cdm9qeg+k+rQ4s2VWgh2kDEA+zxezgBA/f4SF4eVRPgz8avEgTiZNMJDn NgSEuT42drezC36KtG6wvWyJMbmSxzmFKcOBVxHJh5ltVudG8aVvxNox3Kdv8+YL1ooa dLHg/gykFN2Bt8Uuc5L5LJw1rK5CTaHvhFpuYpFYACCNvjh4BCukjfVXDslgeJVqoj3s +9wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FCyNlspi; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.07.51; Mon, 21 Dec 2020 23:07:51 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FCyNlspi; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726274AbgLVHGk (ORCPT + 7 others); Tue, 22 Dec 2020 02:06:40 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53958 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726246AbgLVHGk (ORCPT ); Tue, 22 Dec 2020 02:06:40 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75q5b064209; Tue, 22 Dec 2020 01:05:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620752; bh=+nl8LicT//augqm13+dqzPO4Zt/8O9Pq6Zxz1AFAlx0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FCyNlspiaiecTPXXKhCqzUiTYG7F3pAupprbPJIGE8NiBpaaFn42DKOO7rZ2LzeKl yINXDv/qWE8EVv0O665zJqv1mCX0B1IBdWeTz8KJQrw5K73lLvCf+PV70gN7/nVBTw jxWgRzLjOJGF6EcKpgsi0+bdu4WIR5GVpFh/buCk= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75qUn011420 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:52 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:52 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:52 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7G050344; Tue, 22 Dec 2020 01:05:48 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 07/14] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function Date: Tue, 22 Dec 2020 12:35:13 +0530 Message-ID: <20201222070520.28132-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 36 ++++++++++++++++-------- 1 file changed, 25 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 7bf1b4c7774a..935f165404e4 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -509,6 +509,28 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct reset_control *rst; + + rst = devm_reset_control_get(dev, "sierra_reset"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(rst); + } + sp->phy_rst = rst; + + rst = devm_reset_control_get_optional(dev, "sierra_apb"); + if (IS_ERR(rst)) { + dev_err(dev, "failed to get apb reset\n"); + return PTR_ERR(rst); + } + sp->apb_rst = rst; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -559,17 +581,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); - if (IS_ERR(sp->phy_rst)) { - dev_err(dev, "failed to get reset\n"); - return PTR_ERR(sp->phy_rst); - } - - sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); - if (IS_ERR(sp->apb_rst)) { - dev_err(dev, "failed to get apb reset\n"); - return PTR_ERR(sp->apb_rst); - } + ret = cdns_sierra_phy_get_resets(sp, dev); + if (ret) + return ret; ret = clk_prepare_enable(sp->clk); if (ret) From patchwork Tue Dec 22 07:05:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346616 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095934jai; Mon, 21 Dec 2020 23:08:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJyRxC2uCnjxuGopRL9nvpH6TMqTaoAaHjAT20GCQy+FGb4YkbtBrvqPi0s7OyZTv2vu3jMP X-Received: by 2002:a17:906:3a98:: with SMTP id y24mr17903529ejd.436.1608620886567; Mon, 21 Dec 2020 23:08:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620886; cv=none; d=google.com; s=arc-20160816; b=SJqSdEvEWs2L4JTYTNPcLGy6dtKfE7jGHazPpEH00i7fVvt+Py57DE+iEIXIbjk/mD WlZvzm5OuUb8eYZtqv6/X+JfSEHQVArKhcoMLQCy5ZE7j4VJ7NqtdhyVl62LL5rjQe9z gk+qKPj3JiGAjKPeIisUcGxkZtFnzMRwRFUQEgP9OaVzJIzTpOZbBpTJ+3L71n3wvZem ubToJmtcxfc4FyfuR6Qnp2qq50JSxV2phBxBPsXyPq5k8vqfi50+L8CfS1S63ONV84U4 x/nk+wo5ieOFiMXm0o9EcqeXjvULV5B8fmIN/1OpeYh/ezZ/zIf/BJpvGk+PRwQBhQ0X RyUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=X8lkmYvm2LZftzAI7MPmXYXTlNDPCOiWt9wiFwCLMFg=; b=uyeuYEm/A9riv6Pfn5OFUvGEyKWNrgecw6lPXfIIoXS4Vvic8cht7INgK03jR7QE3q SHiAadpHPm0HIi5FPqYNFqdsV3cmLf/cF6yQGK+oETuYADQawvQvls4NH15ai5np6pxp hNjvuFLLldUtRtSLKvn1qB0YvCOekNQ9KS1hN/uMDIllBC25lAwrinGBIZ7d9hGwaK0A rq0UvK1RuBziNU7N4B6npdADWCyvLcQ/K/VvCWl2l85pWHaTuZUUfR4FyAyVWBwFTrY2 NeLb9GIgz2t1MDuZAdlkt3rVL33Z1iBuh0XJRvmeGJoFaf83FMvk85+JxBrYOf8htake /1kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fey6bN9G; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 935f165404e4..44c52a0842dc 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -514,14 +514,14 @@ static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, { struct reset_control *rst; - rst = devm_reset_control_get(dev, "sierra_reset"); + rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); if (IS_ERR(rst)) { dev_err(dev, "failed to get reset\n"); return PTR_ERR(rst); } sp->phy_rst = rst; - rst = devm_reset_control_get_optional(dev, "sierra_apb"); + rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); if (IS_ERR(rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(rst); From patchwork Tue Dec 22 07:05:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346610 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095848jai; Mon, 21 Dec 2020 23:07:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJxMSbo3Klah7TDcd0k1QEQVcwuMSL2J6EvX226xDZLSKCoFk4NLDfiDMVaZzHJYrEXBeAjz X-Received: by 2002:aa7:d593:: with SMTP id r19mr19341634edq.246.1608620879572; Mon, 21 Dec 2020 23:07:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620879; cv=none; d=google.com; s=arc-20160816; b=da0rvfBzmFKfQokt21VNovzGJ7P62irYXx0So9fN7WCRogS3VOjGcEl7IKY0i4WDn3 IWp3U+J8Anb3ogAuh1jygdVzxOjbZht63w1I7/KDdiaUNKxn6QnKIAn3YZZ91s2bgdgC CTGnc0Zj3xKfbK0uRoIO8cLGNav2Z17h2rtBkc41H1vM8KrYhQSfHJYKljE6VPwAQyc8 cLz0OHtyJ6AhV/onvqfgS8aXV2ln0uZ/l9NnXIMBX2O8u751GeITpdfVba8Q5BS1ytjP 5yGS+Zb0CgkAw3yWI3VVKtNwwvQIQBp+ZMx/csNU3HFd3CfAD9f5kAyzpUz7IsklUkC9 lsbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ctjrTLWGVtshZ8EF7r1WXZ19ZgPa6NCq5+743muOnQw=; b=JxNaJU37IgTzIBhNYvmxFBSi0akpgDkCisE9g9Mjliz0srZTQ6tWE4nKHE0IMu7vrf eOT1hmmn05Q+ecfUh2vWbdbwoJ3reZyI/UpsIimxM6g0OpLPiOUuDJhkkrNSFat0Yp7y AzWY27OlyOJxwJdDs1xeDZEsV2mVhxSqQZTtViKUxOKcMHK5N0t4QMWxddyTlhpovLxo NO6a9A5UwDDAnnoNsxHD994r0oltrkSyBD8w2sonLctE9RPoyvdBJcJ1ydS4szL0okbz LBREspYVNaQT/UL8Xb5uhSJyUAZunRFbrEl42pt4afaljCq5YUXi8mThxtqQNMiB1esV eTSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o9e9EBh4; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.07.59; Mon, 21 Dec 2020 23:07:59 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o9e9EBh4; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725899AbgLVHHB (ORCPT + 7 others); Tue, 22 Dec 2020 02:07:01 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59124 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726316AbgLVHHA (ORCPT ); Tue, 22 Dec 2020 02:07:00 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75x68034401; Tue, 22 Dec 2020 01:05:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620759; bh=ctjrTLWGVtshZ8EF7r1WXZ19ZgPa6NCq5+743muOnQw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o9e9EBh4MtMBddIKwbtHGh7hZ5HFPA2+gkvccs/E2qBzPawjcXU7y86oLvb+jRZ5x v8vpTEUJcrfLdJP5IOavGYSELN8n2CxcqrztX3+DsbrLxry5LD1W3D/qciBCu09IWG YpRedgf1ylCOEkMVGP3l6ctkVDolu1of2mI2/0mQ= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM75xuO015001 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:05:59 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:05:58 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:05:58 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7I050344; Tue, 22 Dec 2020 01:05:56 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 09/14] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Date: Tue, 22 Dec 2020 12:35:15 +0530 Message-ID: <20201222070520.28132-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to be able to seamlessly use any of the external reference clocks. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 391 ++++++++++++++++++++++- 1 file changed, 388 insertions(+), 3 deletions(-) -- 2.17.1 Reported-by: kernel test robot Reported-by: kernel test robot diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 44c52a0842dc..2a509be80c80 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,6 +7,7 @@ * */ #include +#include #include #include #include @@ -24,6 +25,7 @@ /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A @@ -31,6 +33,9 @@ #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 +#define SIERRA_CMN_REFRCV_PREG 0x98 +#define SIERRA_CMN_REFRCV1_PREG 0xB8 +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -151,6 +156,65 @@ static const struct reg_field phy_pll_cfg_1 = static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); +enum cdns_sierra_cmn_refrcv { + CMN_REFRCV, + CMN_REFRCV1, +}; + +#define SIERRA_NUM_REFRCV 0x2 + +static const struct reg_field cmn_refrcv_refclk_plllc1en_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), +}; + +static const struct reg_field cmn_refrcv_refclk_termen_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), +}; + +static char *refrcv_node_name[] = { "refrcv", "refrcv1" }; + +struct cdns_sierra_refrcv { + struct clk_hw hw; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_refrcv(_hw) \ + container_of(_hw, struct cdns_sierra_refrcv, hw) + +enum cdns_sierra_cmn_plllc { + CMN_PLLLC, + CMN_PLLLC1, +}; + +#define SIERRA_NUM_CMN_PLLC 0x2 + +static const struct reg_field cmn_plllc_pfdclk1_sel_preg[] = { + [CMN_PLLLC] = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), + [CMN_PLLLC1] = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), +}; + +static char *cmn_plllc_node_name[] = { "pll_cmnlc", "pll_cmnlc1" }; + +struct cdns_sierra_pll_mux { + struct clk_hw hw; + struct regmap_field *pfdclk_sel_preg; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_pll_mux(_hw) \ + container_of(_hw, struct cdns_sierra_pll_mux, hw) + +/* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ +static u32 cdns_sierra_pll_mux_table[] = { 0, 1 }; + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -197,6 +261,9 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; + struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -364,6 +431,278 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops cdns_sierra_pll_mux_ops = { + .set_parent = cdns_sierra_pll_mux_set_parent, + .get_parent = cdns_sierra_pll_mux_get_parent, +}; + +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *field) +{ + struct cdns_sierra_pll_mux *mux; + struct device *dev = sp->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &cdns_sierra_pll_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->pfdclk_sel_preg = field; + mux->table = cdns_sierra_pll_mux_table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Fail to add pll mux clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_pll_mux_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *pfdclk1_sel_field; + struct device_node *of_node = NULL; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(node, cmn_plllc_node_name[i]); + if (!of_node) + return 0; + + pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; + ret = cdns_sierra_pll_mux_register(sp, of_node, + pfdclk1_sel_field); + if (ret) { + dev_err(dev, "Fail to register cmn plllc mux %s\n", + cmn_plllc_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_pll_mux_unregister(sp, node); + + return 0; +} + +static int cdns_sierra_refrcv_enable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 1); + regmap_field_write(termen_field, 1); + + return 0; +} + +static void cdns_sierra_refrcv_disable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 0); + regmap_field_write(termen_field, 0); +} + +static int cdns_sierra_refrcv_is_enabled(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + int val; + + regmap_field_read(plllc1en_field, &val); + + return !!val; +} + +static const struct clk_ops cdns_sierra_refrcv_ops = { + .enable = cdns_sierra_refrcv_enable, + .disable = cdns_sierra_refrcv_disable, + .is_enabled = cdns_sierra_refrcv_is_enabled, +}; + +static int cdns_sierra_refrcv_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *plllc1en_field, + struct regmap_field *termen_field) +{ + struct cdns_sierra_refrcv *refrcv; + struct device *dev = sp->dev; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + char clk_name[100]; + struct clk *clk; + int ret; + + refrcv = devm_kzalloc(dev, sizeof(*refrcv), GFP_KERNEL); + if (!refrcv) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &refrcv->clk_data; + + init->ops = &cdns_sierra_refrcv_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + refrcv->plllc1en_field = plllc1en_field; + refrcv->termen_field = termen_field; + refrcv->hw.init = init; + + clk = devm_clk_register(dev, &refrcv->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add refrcv clock provider: %s\n", + clk_name); + + return ret; +} + +static void cdns_sierra_refrcv_unregister(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct device_node *of_node; + int i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return; + + of_clk_del_provider(of_node); + of_node_put(of_node); + } +} + +static int cdns_sierra_phy_register_refrcv(struct cdns_sierra_phy *sp, + struct device_node *node) +{ + struct regmap_field *plllc1en_field; + struct device_node *of_node = NULL; + struct regmap_field *termen_field; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(node, refrcv_node_name[i]); + if (!of_node) + return 0; + + plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; + termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; + + ret = cdns_sierra_refrcv_register(sp, of_node, plllc1en_field, + termen_field); + if (ret) { + dev_err(dev, "Fail to register reference receiver %s\n", + refrcv_node_name[i]); + of_node_put(of_node); + goto err; + } + + of_node_put(of_node); + } + + return 0; + +err: + cdns_sierra_refrcv_unregister(sp, node); + + return ret; +} + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -402,6 +741,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) { struct device *dev = sp->dev; struct regmap_field *field; + struct reg_field reg_field; struct regmap *regmap; int i; @@ -413,6 +753,34 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->macro_id_type = field; + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + reg_field = cmn_refrcv_refclk_plllc1en_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; + + reg_field = cmn_refrcv_refclk_termen_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_termen_preg[i] = field; + } + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + reg_field = cmn_plllc_pfdclk1_sel_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); + return PTR_ERR(field); + } + sp->cmn_plllc_pfdclk1_sel_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -577,17 +945,25 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - ret = cdns_sierra_phy_get_clocks(sp, dev); + ret = cdns_sierra_phy_register_refrcv(sp, dn); if (ret) return ret; + ret = cdns_sierra_phy_register_pll_mux(sp, dn); + if (ret) + goto unregister_refrcv; + + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + goto unregister_pll_mux; + ret = cdns_sierra_phy_get_resets(sp, dev); if (ret) - return ret; + goto unregister_pll_mux; ret = clk_prepare_enable(sp->clk); if (ret) - return ret; + goto unregister_pll_mux; /* Enable APB */ reset_control_deassert(sp->apb_rst); @@ -664,12 +1040,19 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) clk_disable: clk_disable_unprepare(sp->clk); reset_control_assert(sp->apb_rst); +unregister_pll_mux: + cdns_sierra_pll_mux_unregister(sp, dn); +unregister_refrcv: + cdns_sierra_refrcv_unregister(sp, dn); + return ret; } static int cdns_sierra_phy_remove(struct platform_device *pdev) { struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct device_node *dn = dev->of_node; int i; reset_control_assert(phy->phy_rst); @@ -684,6 +1067,8 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) reset_control_assert(phy->phys[i].lnk_rst); reset_control_put(phy->phys[i].lnk_rst); } + cdns_sierra_pll_mux_unregister(phy, dn); + cdns_sierra_refrcv_unregister(phy, dn); return 0; } From patchwork Tue Dec 22 07:05:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346611 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095858jai; Mon, 21 Dec 2020 23:08:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJzQff2PnGoP3JnPr5ldR8aU3UuG+1zhrBhSzula04QxUykL99KX85KfSzMQ1tNyh8BpVPV0 X-Received: by 2002:a05:6402:17a3:: with SMTP id j3mr19117613edy.333.1608620880294; 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This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 56 +++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 2a509be80c80..553971683f2d 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -267,6 +267,8 @@ struct cdns_sierra_phy { struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; + struct clk *pll_cmnlc; + struct clk *pll_cmnlc1; int nsubnodes; u32 num_lanes; bool autoconf; @@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, } sp->cmn_refclk1_dig_div = clk; + clk = devm_clk_get_optional(dev, "pll_cmnlc"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc = clk; + + clk = devm_clk_get_optional(dev, "pll_cmnlc1"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc1 clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc1 = clk; + return 0; } +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->pll_cmnlc); + if (ret) + goto err_pll_cmnlc; + + ret = clk_prepare_enable(sp->pll_cmnlc1); + if (ret) + goto err_pll_cmnlc1; + + return 0; + +err_pll_cmnlc: + clk_disable_unprepare(sp->clk); + +err_pll_cmnlc1: + clk_disable_unprepare(sp->pll_cmnlc); + + return 0; +} + +static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) +{ + clk_disable_unprepare(sp->pll_cmnlc1); + clk_disable_unprepare(sp->pll_cmnlc); + clk_disable_unprepare(sp->clk); +} + static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { @@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) goto unregister_pll_mux; - ret = clk_prepare_enable(sp->clk); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) goto unregister_pll_mux; @@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) reset_control_put(sp->phys[i].lnk_rst); of_node_put(child); clk_disable: - clk_disable_unprepare(sp->clk); + cdns_sierra_phy_disable_clocks(sp); reset_control_assert(sp->apb_rst); unregister_pll_mux: cdns_sierra_pll_mux_unregister(sp, dn); From patchwork Tue Dec 22 07:05:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346613 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095898jai; Mon, 21 Dec 2020 23:08:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJy/ZnrQgnzeHjzoNNgcZ2Gqkr+v9ui6EHuoaFYq6jwQQd7caG+xHqcyUXjrm/O3EFtfhLJF X-Received: by 2002:a50:8a90:: with SMTP id j16mr18745136edj.334.1608620883014; Mon, 21 Dec 2020 23:08:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620883; cv=none; d=google.com; s=arc-20160816; b=EZDduBcjxWM/jVS6+LfQG5LxtCeVEa9/foeu9Ot85XaZsgRssPm1gYm2RQHP4TwgU7 9Gy0BNZY6Nzf1bo6eEyCfrMFAk4UZCzXfWrbef1gsjqzpz2uHmRye5hlJi2tDf0IFsip u2G9f0bG8UvzqfuDe2HRuH8n00igbwD10GbilFdTnbRgAa0nSNYOPdmf4yj6T5yIN/VF 2mCxsY3StXjVAYrU36WA4Yk1pKauv6aww1NndydgkzvjrIWBnhLstQRcIQDhM+6mYaZ/ 5QyWeUb5BosSC1IqC+WE/QXnMGwVugTlgX4/QibryGnwb+GjpSjtuIMqoq5ksv42rL75 XFtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QTzzUhajMm8IhBdGfHPyShrRRd86TMVhnsXp4t435rE=; b=pJ61rQhxjGXrqVKHoxuFduXaw6YR8E1DtEzAwkiyxE+zmSjOFbqYLQTKyU0G0m4giZ ttzQPLi5xNX07atwxAEQqmLhYakJHenFt6Efz1J8NhBYpU3hImuXcVtPCePvBNclS3oB ULjTG7Rnw8x3l5DPD4RP03nfx9o47aZVb1MFchaP7Jp0kP7wcIPlmkGLyMeUV/tItYl/ p5ayvgMlDJtDh3CB230bycr8WHoGUwZrnJprjPkIubuOzHvReEfcaV4PS/bOAYKZGiYA GcuW77Plo7tXLgCwt74XJwkst9YoJUl+0EuQzZ7YClOW3CSJtZ4Xb870yYEBN3mlrb1A /CEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="RbMVg0/W"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++-- 1 file changed, 120 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b32df591c766..00d2d51689f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -432,8 +432,36 @@ #size-cells = <0>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes0_refrcv: refrcv { + clocks = <&wiz0_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_refrcv1: refrcv1 { + clocks = <&wiz0_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes0_pll_cmnlc: pll_cmnlc { + clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&wiz0_pll0_refclk>; + }; + + serdes0_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes0_pll_cmnlc1>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + }; }; }; @@ -489,8 +517,36 @@ #size-cells = <0>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes1_refrcv: refrcv { + clocks = <&wiz1_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_refrcv1: refrcv1 { + clocks = <&wiz1_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes1_pll_cmnlc: pll_cmnlc { + clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&wiz1_pll0_refclk>; + }; + + serdes1_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes1_pll_cmnlc1>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + }; }; }; @@ -546,8 +602,36 @@ #size-cells = <0>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes2_refrcv: refrcv { + clocks = <&wiz2_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_refrcv1: refrcv1 { + clocks = <&wiz2_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes2_pll_cmnlc: pll_cmnlc { + clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&wiz2_pll0_refclk>; + }; + + serdes2_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes2_pll_cmnlc1>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + }; }; }; @@ -603,8 +687,36 @@ #size-cells = <0>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; + + serdes3_refrcv: refrcv { + clocks = <&wiz3_pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_refrcv1: refrcv1 { + clocks = <&wiz3_pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes3_pll_cmnlc: pll_cmnlc { + clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc>; + assigned-clock-parents = <&wiz3_pll0_refclk>; + }; + + serdes3_pll_cmnlc1: pll_cmnlc1 { + clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes3_pll_cmnlc1>; + assigned-clock-parents = <&wiz3_pll1_refclk>; + }; }; }; From patchwork Tue Dec 22 07:05:18 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.08.06; Mon, 21 Dec 2020 23:08:06 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mrToRifz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726434AbgLVHHS (ORCPT + 7 others); Tue, 22 Dec 2020 02:07:18 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59180 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725854AbgLVHHS (ORCPT ); Tue, 22 Dec 2020 02:07:18 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM769H7034478; Tue, 22 Dec 2020 01:06:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620769; bh=dIek6URgqOZ3zjIDXTQ8bUFq9LLCCzipOJGbMgsIows=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mrToRifzN7mbyZtG32/D1illQk3+Qik7EbyTk9JPSwmuE/DGNVaAy36mr0LpQhjWc tgrZOfdpasbxCZ04N8at+QfNolwWVV3Myw0NezSIfkv3/AVqPX//PiLX4jK6rNtdss NAM/jhHNrYMtK+EZj0Kquj4p8Vuvi9VC5l59U38c= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM769A7011917 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:06:09 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:06:09 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:06:09 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7L050344; Tue, 22 Dec 2020 01:06:06 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 12/14] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Date: Tue, 22 Dec 2020 12:35:18 +0530 Message-ID: <20201222070520.28132-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename the external refclk inputs to the SERDES from dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1 respectively. Also move the external refclk DT nodes outside the cbass_main DT node. Since in j721e common processor board, only the cmn_refclk1 is connected to 100MHz clock, fix the clock frequency. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 4 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++++++++++--------- 2 files changed, 34 insertions(+), 28 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22b..86f7ab511ee8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -635,6 +635,10 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 00d2d51689f1..361abff9f469 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include #include +/ { + cmn_refclk: cmn-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: cmn-refclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -368,24 +382,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -394,21 +396,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -470,7 +472,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -479,21 +481,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -555,7 +557,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -564,21 +566,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -640,7 +642,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -649,21 +651,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; From patchwork Tue Dec 22 07:05:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346617 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095946jai; Mon, 21 Dec 2020 23:08:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJyUd0ZBaGfN7tNBZkD+FUIInf3jn4CBfX+GJcF0za65R3yxAxcc/hJexjIF2RkpOaGnlH1P X-Received: by 2002:a17:906:a008:: with SMTP id p8mr5680772ejy.117.1608620887428; Mon, 21 Dec 2020 23:08:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620887; 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This will make the same clock used by the local SERDES as well as the clock provided to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 86f7ab511ee8..788126daf91c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -639,6 +639,51 @@ clock-frequency = <100000000>; }; +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes0_pll_cmnlc { + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&serdes0_refrcv1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes1_pll_cmnlc { + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&serdes1_refrcv1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes2_pll_cmnlc { + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&serdes2_refrcv1>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; From patchwork Tue Dec 22 07:05:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346614 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095923jai; Mon, 21 Dec 2020 23:08:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJxRrZjL3aiogxNFoFHSYHqmqCjICdZ8jqB259R34pFtyvypisr1rAk4f3SXsADsID1AVdsY X-Received: by 2002:a05:6402:d09:: with SMTP id eb9mr18932715edb.71.1608620884875; Mon, 21 Dec 2020 23:08:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620884; cv=none; d=google.com; s=arc-20160816; b=pvGluXHDKo3yH1x5ppo10QunWftRS23rZMav4hhbRQe9CSRcQpoTLQZYHOoudSuA+a a7VP2Jlh8yh7I7rw6xHaQD/dpcdpQzGrnvoDPWFy6Wl29y4dEJFq0nQxQe4+8FpqtOon EDJT0lW6UuJOc2k3OnxiJuMCl8KLRcAC9giDZsqi1ZS5eiXLrXF7dSG78ljUDJXe20aL O9gWblGzVWA9Uf+X8AMnlLuOXdp5WUxlNFolxqSIgigy4yDD0HHYCeTUFMAK4p1hTqGR 3COrjHQwZL6sJGswjChIj1/FFW949Z3iSQxkAYgxqIU28jcoYT3/IoTU8+WCH/RoQAzj QIhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JZPshwWVVHYyyVCfjW7JfaXlQvyXib/1joMtQSq41ig=; b=H5AlcuQHBEl/uDxInE7YUHav4+cgQrooItwecOrwhsrAKQyz+QEIqBxAlaBVTfgZ1t 0hCJ8aMO5kjFJBLyClRtUz50WQ6vZR9+1VGSi651uvewipGeQviQyjxcjM+9psOgEIhQ s1HjIX2BDWh7ENlUx1LPzWvD93Pw/WwIguvkAXFYbr5WC32vJ/2qGQfRirqyHJuEu9Hq r7HXyd1gHwRGcvRe/T1V73Yl81yQP9VrHzVVdKPODK1bf2ojnEJEfbg6h7nASI70cr2K 6iufeKten0Jur0K/HmI5HLi0EIFtQNCW6p3NSWRJYp++75jduIPRUPOW9uxH2PB6uF7Q YL+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iH6ItnEw; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Re-name subnodes of serdes in J721E to 'phy'. [1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 788126daf91c..13ae0d89caf2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -358,7 +358,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -685,7 +685,7 @@ }; &serdes0 { - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -695,7 +695,7 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -705,7 +705,7 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>;