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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/23] tcg: Use tcg_out_dupi_vec from temp_load Date: Thu, 17 Dec 2020 08:51:53 -0600 Message-Id: <20201217145215.534637-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having dupi pass though movi is confusing and arguably wrong. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++- tcg/aarch64/tcg-target.c.inc | 7 ---- tcg/i386/tcg-target.c.inc | 63 ++++++++++++++++++++++++------------ tcg/ppc/tcg-target.c.inc | 6 ---- 4 files changed, 47 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 43c6cf8f52..ef55c23c20 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3333,7 +3333,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, case TEMP_VAL_CONST: reg = tcg_reg_alloc(s, desired_regs, allocated_regs, preferred_regs, ts->indirect_base); - tcg_out_movi(s, ts->type, reg, ts->val); + if (ts->type <= TCG_TYPE_I64) { + tcg_out_movi(s, ts->type, reg, ts->val); + } else { + tcg_out_dupi_vec(s, ts->type, reg, ts->val); + } ts->mem_coherent = 0; break; case TEMP_VAL_MEM: diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..695f53b125 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1007,13 +1007,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, case TCG_TYPE_I64: tcg_debug_assert(rd < 32); break; - - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(rd >= 32); - tcg_out_dupi_vec(s, type, rd, value); - return; - default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..e2852cbb09 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -966,30 +966,32 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } } -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_vec(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + if (arg == 0) { + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); + return; + } + if (arg == -1) { + tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); + return; + } + + int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); + tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); + } else { + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + } +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) { tcg_target_long diff; - switch (type) { - case TCG_TYPE_I32: -#if TCG_TARGET_REG_BITS == 64 - case TCG_TYPE_I64: -#endif - if (ret < 16) { - break; - } - /* fallthru */ - case TCG_TYPE_V64: - case TCG_TYPE_V128: - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16); - tcg_out_dupi_vec(s, type, ret, arg); - return; - default: - g_assert_not_reached(); - } - if (arg == 0) { tgen_arithr(s, ARITH_XOR, ret, ret); return; @@ -1018,6 +1020,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out64(s, arg); } +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: +#if TCG_TARGET_REG_BITS == 64 + case TCG_TYPE_I64: +#endif + if (ret < 16) { + tcg_out_movi_int(s, type, ret, arg); + } else { + tcg_out_movi_vec(s, type, ret, arg); + } + break; + default: + g_assert_not_reached(); + } +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val == (int8_t)val) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..df18d694f3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -983,12 +983,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_out_movi_int(s, type, ret, arg, false); break; - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(ret >= TCG_REG_V0); - tcg_out_dupi_vec(s, type, ret, arg); - break; - default: g_assert_not_reached(); } From patchwork Thu Dec 17 14:51:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344936 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1289356ejs; Thu, 17 Dec 2020 06:56:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJzq0YprLdZfZ3uLk9FDOtr8KJo51FIwYWCN24gkKlmMKt3DonQ/srujyP1bNWZhTvk3UXyB X-Received: by 2002:a25:b804:: with SMTP id v4mr61420239ybj.371.1608216992767; Thu, 17 Dec 2020 06:56:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608216992; cv=none; d=google.com; s=arc-20160816; b=qup31Vvbt5GEROwp0CJfO+10OpzXduvzsGrtxbxM7z1ZwzIiYAuRwCW1o548i3QbPN ptozvDpJ0KrtY37N8pezWKP4TdK1TcEAwsXDq68BZFiarwOup9cNfDh7O5p3gf6+vkeB oHIx2jN/vBrTcwd42IVw7H/GJWk6HFE7J0wjdCENTMqkSZ5qYeZPlPqnwzOttZeUdJUz jbFKNcA9LlSnrjpq5tpaTEtbKOZlDrFKK42h8fLK0TURUNUn3vC/V7fZcT25Ifw28XID V4z6+0EKvUr83GQBrQQFYFxMMZW2S/J5WeCJSlqyBRD6bR5JCukourOVfT69hdcppDxk dMdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BN996J7U0Obk/NuvmIQte+lnV+dtpzifIKeaJMGxzjc=; b=Mp2W/3+wQaAmoVsbbsQqKRZDHjSNkzKC8vX9oQTMGlBWTlyE7CuREMGzNOKPrwmmoV VJteXgitZee/qDCmUpst4yuKrekyLwXtDbO9CvEPxRF7miiZNp4J4YXnKGUfzstqiYwO 7P0vOz/1CyPwRQ/V8F/1TqtNaRhhhCCwwca6m0kFK51h0JkpYw0SXdS1mnbuenABxRPI UMAHfVZ11KYiTQiWmq0w9YCvfYL6gMZJNDZOSXOfocKhaaZAKzsZ+y8ECfMQYY1RYMg4 nCl1RxfWXiQvPpOQGr9jXAzp/YXthI5QqTi1tbI7Sfrq+pRn6X6icuaDGwIBWPFWI05X a5LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V8wi757A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/23] tcg: Increase tcg_out_dupi_vec immediate to int64_t Date: Thu, 17 Dec 2020 08:51:54 -0600 Message-Id: <20201217145215.534637-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Also pass along the minimal vece that may be said to apply to the constant. This allows some simplification in the various backends. Signed-off-by: Richard Henderson --- tcg/tcg.c | 31 +++++++++++++++++++++++++----- tcg/aarch64/tcg-target.c.inc | 12 ++++++------ tcg/i386/tcg-target.c.inc | 22 ++++++++++++--------- tcg/ppc/tcg-target.c.inc | 37 +++++++++++++++++++++++------------- 4 files changed, 69 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index ef55c23c20..2326e61b51 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,8 +116,8 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg dst, tcg_target_long arg); +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args); @@ -132,8 +132,8 @@ static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, { g_assert_not_reached(); } -static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg dst, tcg_target_long arg) +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg) { g_assert_not_reached(); } @@ -3336,7 +3336,28 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, if (ts->type <= TCG_TYPE_I64) { tcg_out_movi(s, ts->type, reg, ts->val); } else { - tcg_out_dupi_vec(s, ts->type, reg, ts->val); + uint64_t val = ts->val; + MemOp vece = MO_64; + + /* + * Find the minimal vector element that matches the constant. + * The targets will, in general, have to do this search anyway, + * do this generically. + */ + if (TCG_TARGET_REG_BITS == 32) { + val = dup_const(MO_32, val); + vece = MO_32; + } + if (val == dup_const(MO_8, val)) { + vece = MO_8; + } else if (val == dup_const(MO_16, val)) { + vece = MO_16; + } else if (TCG_TARGET_REG_BITS == 64 && + val == dup_const(MO_32, val)) { + vece = MO_32; + } + + tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); } ts->mem_coherent = 0; break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 695f53b125..56056be74b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -853,14 +853,14 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, tcg_target_long v64) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, int64_t v64) { bool q = type == TCG_TYPE_V128; int cmode, imm8, i; /* Test all bytes equal first. */ - if (v64 == dup_const(MO_8, v64)) { + if (vece == MO_8) { imm8 = (uint8_t)v64; tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); return; @@ -887,7 +887,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, * cannot find an expansion there's no point checking a larger * width because we already know by replication it cannot match. */ - if (v64 == dup_const(MO_16, v64)) { + if (vece == MO_16) { uint16_t v16 = v64; if (is_shimm16(v16, &cmode, &imm8)) { @@ -906,7 +906,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); return; - } else if (v64 == dup_const(MO_32, v64)) { + } else if (vece == MO_32) { uint32_t v32 = v64; uint32_t n32 = ~v32; @@ -2430,7 +2430,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); break; } - tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0); + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); a2 = TCG_VEC_TMP; } insn = cmp_insn[cond]; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e2852cbb09..6b7cbaa47a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -933,8 +933,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, return true; } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg ret, int64_t arg) { int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); @@ -947,7 +947,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, return; } - if (TCG_TARGET_REG_BITS == 64) { + if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { + if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + } + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + } else { if (type == TCG_TYPE_V64) { tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); } else if (have_avx2) { @@ -955,14 +962,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } else { tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); } - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else { - if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } else { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); } - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); } } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index df18d694f3..2428faeabd 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -908,31 +908,41 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } } -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long val) +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg ret, int64_t val) { uint32_t load_insn; int rel, low; intptr_t add; - low = (int8_t)val; - if (low >= -16 && low < 16) { - if (val == (tcg_target_long)dup_const(MO_8, low)) { + switch (vece) { + case MO_8: + low = (int8_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); return; } - if (val == (tcg_target_long)dup_const(MO_16, low)) { + if (have_isa_3_00) { + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); + return; + } + break; + + case MO_16: + low = (int16_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); return; } - if (val == (tcg_target_long)dup_const(MO_32, low)) { + break; + + case MO_32: + low = (int32_t)val; + if (low >= -16 && low < 16) { tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); return; } - } - if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) { - tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); - return; + break; } /* @@ -952,14 +962,15 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, if (TCG_TARGET_REG_BITS == 64) { new_pool_label(s, val, rel, s->code_ptr, add); } else { - new_pool_l2(s, rel, s->code_ptr, add, val, val); + new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); } } else { load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); if (TCG_TARGET_REG_BITS == 64) { new_pool_l2(s, rel, s->code_ptr, add, val, val); } else { - new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + new_pool_l4(s, rel, s->code_ptr, add, + val >> 32, val, val >> 32, val); } } From patchwork Thu Dec 17 14:51:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344943 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1295627ejs; Thu, 17 Dec 2020 07:03:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzCjDZG7MYGt70zfbstjQ7LlsAK2Xqx2UrA7NP+5Btt43T3dfVa1uTUsVf46MwqEX1uGg3w X-Received: by 2002:a25:75c3:: with SMTP id q186mr57412577ybc.460.1608217423879; Thu, 17 Dec 2020 07:03:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217423; cv=none; d=google.com; s=arc-20160816; b=O+bDLRneJKdmSW7AjLuO0Q8OMpFJ6ssQMJtbExAFYAB1lbTC+xIGV/UB4gsPYxBtwW hZMGlFNiyLkDkE8s8l8hG/5HUv4W0y+EirfFHwkEYByTswNzviEUaiUlMUPeawo8OWBl tpikLxvddprcocakkFr3ed2loDa5TChiv5HVw5XJUyZVIvyO1NZehuFipn4P/Qlnmfyd vBxwdClMhIAXGMvSy2oP2yk7TTBO2ZfJKqNviL+vAKM+exAZ4e6VZ2rg74a+Iqi3MpHA cVHlVMcJP+QUKqX4MZOwcWtRl36r0SCdzltzTOGEsw/H78OVBP9PS88PYkM7IQDVyMk6 hlow== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/23] tcg: Consolidate 3 bits into enum TCGTempKind Date: Thu, 17 Dec 2020 08:51:55 -0600 Message-Id: <20201217145215.534637-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The temp_fixed, temp_global, temp_local bits are all related. Combine them into a single enumeration. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 20 +++++--- tcg/optimize.c | 8 +-- tcg/tcg.c | 126 ++++++++++++++++++++++++++++------------------ 3 files changed, 92 insertions(+), 62 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8ff9dad4ef..30bd525d83 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -483,23 +483,27 @@ typedef enum TCGTempVal { TEMP_VAL_CONST, } TCGTempVal; +typedef enum TCGTempKind { + /* Temp is dead at the end of all basic blocks. */ + TEMP_NORMAL, + /* Temp is saved across basic blocks but dead at the end of TBs. */ + TEMP_LOCAL, + /* Temp is saved across both basic blocks and translation blocks. */ + TEMP_GLOBAL, + /* Temp is in a fixed register. */ + TEMP_FIXED, +} TCGTempKind; + typedef struct TCGTemp { TCGReg reg:8; TCGTempVal val_type:8; TCGType base_type:8; TCGType type:8; - unsigned int fixed_reg:1; + TCGTempKind kind:3; unsigned int indirect_reg:1; unsigned int indirect_base:1; unsigned int mem_coherent:1; unsigned int mem_allocated:1; - /* If true, the temp is saved across both basic blocks and - translation blocks. */ - unsigned int temp_global:1; - /* If true, the temp is saved across basic blocks but dead - at the end of translation blocks. If false, the temp is - dead at the end of basic blocks. */ - unsigned int temp_local:1; unsigned int temp_allocated:1; tcg_target_long val; diff --git a/tcg/optimize.c b/tcg/optimize.c index 220f4601d5..3cffd941bd 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -116,21 +116,21 @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) TCGTemp *i; /* If this is already a global, we can't do better. */ - if (ts->temp_global) { + if (ts->kind >= TEMP_GLOBAL) { return ts; } /* Search for a global first. */ for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->temp_global) { + if (i->kind >= TEMP_GLOBAL) { return i; } } /* If it is a temp, search for a temp local. */ - if (!ts->temp_local) { + if (ts->kind == TEMP_NORMAL) { for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (ts->temp_local) { + if (i->kind >= TEMP_LOCAL) { return i; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 2326e61b51..07a25e59b6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1161,7 +1161,7 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s) tcg_debug_assert(s->nb_globals == s->nb_temps); s->nb_globals++; ts = tcg_temp_alloc(s); - ts->temp_global = 1; + ts->kind = TEMP_GLOBAL; return ts; } @@ -1178,7 +1178,7 @@ static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, ts = tcg_global_alloc(s); ts->base_type = type; ts->type = type; - ts->fixed_reg = 1; + ts->kind = TEMP_FIXED; ts->reg = reg; ts->name = name; tcg_regset_set_reg(s->reserved_regs, reg); @@ -1205,7 +1205,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, bigendian = 1; #endif - if (!base_ts->fixed_reg) { + if (base_ts->kind != TEMP_FIXED) { /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base = 1; @@ -1253,6 +1253,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) { TCGContext *s = tcg_ctx; + TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL; TCGTemp *ts; int idx, k; @@ -1265,7 +1266,7 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) ts = &s->temps[idx]; ts->temp_allocated = 1; tcg_debug_assert(ts->base_type == type); - tcg_debug_assert(ts->temp_local == temp_local); + tcg_debug_assert(ts->kind == kind); } else { ts = tcg_temp_alloc(s); if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { @@ -1274,18 +1275,18 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) ts->base_type = type; ts->type = TCG_TYPE_I32; ts->temp_allocated = 1; - ts->temp_local = temp_local; + ts->kind = kind; tcg_debug_assert(ts2 == ts + 1); ts2->base_type = TCG_TYPE_I64; ts2->type = TCG_TYPE_I32; ts2->temp_allocated = 1; - ts2->temp_local = temp_local; + ts2->kind = kind; } else { ts->base_type = type; ts->type = type; ts->temp_allocated = 1; - ts->temp_local = temp_local; + ts->kind = kind; } } @@ -1342,12 +1343,12 @@ void tcg_temp_free_internal(TCGTemp *ts) } #endif - tcg_debug_assert(ts->temp_global == 0); + tcg_debug_assert(ts->kind < TEMP_GLOBAL); tcg_debug_assert(ts->temp_allocated != 0); ts->temp_allocated = 0; idx = temp_idx(ts); - k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); + k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT); set_bit(idx, s->free_temps[k].l); } @@ -1877,17 +1878,27 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) static void tcg_reg_alloc_start(TCGContext *s) { int i, n; - TCGTemp *ts; - for (i = 0, n = s->nb_globals; i < n; i++) { - ts = &s->temps[i]; - ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); - } - for (n = s->nb_temps; i < n; i++) { - ts = &s->temps[i]; - ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); - ts->mem_allocated = 0; - ts->fixed_reg = 0; + for (i = 0, n = s->nb_temps; i < n; i++) { + TCGTemp *ts = &s->temps[i]; + TCGTempVal val = TEMP_VAL_MEM; + + switch (ts->kind) { + case TEMP_FIXED: + val = TEMP_VAL_REG; + break; + case TEMP_GLOBAL: + break; + case TEMP_NORMAL: + val = TEMP_VAL_DEAD; + /* fall through */ + case TEMP_LOCAL: + ts->mem_allocated = 0; + break; + default: + g_assert_not_reached(); + } + ts->val_type = val; } memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); @@ -1898,12 +1909,17 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, { int idx = temp_idx(ts); - if (ts->temp_global) { + switch (ts->kind) { + case TEMP_FIXED: + case TEMP_GLOBAL: pstrcpy(buf, buf_size, ts->name); - } else if (ts->temp_local) { + break; + case TEMP_LOCAL: snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); - } else { + break; + case TEMP_NORMAL: snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); + break; } return buf; } @@ -2493,15 +2509,24 @@ static void la_bb_end(TCGContext *s, int ng, int nt) { int i; - for (i = 0; i < ng; ++i) { - s->temps[i].state = TS_DEAD | TS_MEM; - la_reset_pref(&s->temps[i]); - } - for (i = ng; i < nt; ++i) { - s->temps[i].state = (s->temps[i].temp_local - ? TS_DEAD | TS_MEM - : TS_DEAD); - la_reset_pref(&s->temps[i]); + for (i = 0; i < nt; ++i) { + TCGTemp *ts = &s->temps[i]; + int state; + + switch (ts->kind) { + case TEMP_FIXED: + case TEMP_GLOBAL: + case TEMP_LOCAL: + state = TS_DEAD | TS_MEM; + break; + case TEMP_NORMAL: + state = TS_DEAD; + break; + default: + g_assert_not_reached(); + } + ts->state = state; + la_reset_pref(ts); } } @@ -2529,7 +2554,7 @@ static void la_bb_sync(TCGContext *s, int ng, int nt) la_global_sync(s, ng); for (int i = ng; i < nt; ++i) { - if (s->temps[i].temp_local) { + if (s->temps[i].kind == TEMP_LOCAL) { int state = s->temps[i].state; s->temps[i].state = state | TS_MEM; if (state != TS_DEAD) { @@ -3137,7 +3162,8 @@ static void check_regs(TCGContext *s) } for (k = 0; k < s->nb_temps; k++) { ts = &s->temps[k]; - if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg + if (ts->val_type == TEMP_VAL_REG + && ts->kind != TEMP_FIXED && s->reg_to_temp[ts->reg] != ts) { printf("Inconsistency for temp %s:\n", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); @@ -3174,15 +3200,14 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { return; } if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = NULL; } ts->val_type = (free_or_dead < 0 - || ts->temp_local - || ts->temp_global + || ts->kind != TEMP_NORMAL ? TEMP_VAL_MEM : TEMP_VAL_DEAD); } @@ -3199,7 +3224,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { return; } if (!ts->mem_coherent) { @@ -3382,7 +3407,8 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) { /* The liveness analysis already ensures that globals are back in memory. Keep an tcg_debug_assert for safety. */ - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM + || ts->kind == TEMP_FIXED); } /* save globals to their canonical location and assume they can be @@ -3407,7 +3433,7 @@ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) for (i = 0, n = s->nb_globals; i < n; i++) { TCGTemp *ts = &s->temps[i]; tcg_debug_assert(ts->val_type != TEMP_VAL_REG - || ts->fixed_reg + || ts->kind == TEMP_FIXED || ts->mem_coherent); } } @@ -3420,7 +3446,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) for (i = s->nb_globals; i < s->nb_temps; i++) { TCGTemp *ts = &s->temps[i]; - if (ts->temp_local) { + if (ts->kind == TEMP_LOCAL) { temp_save(s, ts, allocated_regs); } else { /* The liveness analysis already ensures that temps are dead. @@ -3446,7 +3472,7 @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) * The liveness analysis already ensures that temps are dead. * Keep tcg_debug_asserts for safety. */ - if (ts->temp_local) { + if (ts->kind == TEMP_LOCAL) { tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); } else { tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); @@ -3462,7 +3488,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, TCGRegSet preferred_regs) { /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); /* The movi is not explicitly generated here. */ if (ots->val_type == TEMP_VAL_REG) { @@ -3502,7 +3528,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); /* Note that otype != itype for no-op truncation. */ otype = ots->type; @@ -3541,7 +3567,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } temp_dead(s, ots); } else { - if (IS_DEAD_ARG(1) && !ts->fixed_reg) { + if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { /* the mov can be suppressed */ if (ots->val_type == TEMP_VAL_REG) { s->reg_to_temp[ots->reg] = NULL; @@ -3563,7 +3589,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) * Store the source register into the destination slot * and leave the destination temp as TEMP_VAL_MEM. */ - assert(!ots->fixed_reg); + assert(ots->kind != TEMP_FIXED); if (!ts->mem_allocated) { temp_allocate_frame(s, ots); } @@ -3600,7 +3626,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) its = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(!ots->fixed_reg); + tcg_debug_assert(ots->kind != TEMP_FIXED); itype = its->type; vece = TCGOP_VECE(op); @@ -3740,7 +3766,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) i_preferred_regs = o_preferred_regs = 0; if (arg_ct->ialias) { o_preferred_regs = op->output_pref[arg_ct->alias_index]; - if (ts->fixed_reg) { + if (ts->kind == TEMP_FIXED) { /* if fixed register, we must allocate a new register if the alias is not the same register */ if (arg != op->args[arg_ct->alias_index]) { @@ -3832,7 +3858,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; @@ -3873,7 +3899,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[i]); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); @@ -4005,7 +4031,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(!ts->fixed_reg); + tcg_debug_assert(ts->kind != TEMP_FIXED); reg = tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] == NULL); From patchwork Thu Dec 17 14:51:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344947 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1300295ejs; Thu, 17 Dec 2020 07:08:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJxmCNVVwq3C6SoXO7cfc0eTbVxF6pmUy3djyGGKPrTndMcBUjZ3xTF3OBsIFREk0/QY10Ku X-Received: by 2002:a25:ae14:: with SMTP id a20mr27566019ybj.410.1608217707855; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/23] tcg: Add temp_readonly Date: Thu, 17 Dec 2020 08:51:56 -0600 Message-Id: <20201217145215.534637-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 +++++ tcg/tcg.c | 21 ++++++++++----------- 2 files changed, 15 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 30bd525d83..9a9ced3b15 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -681,6 +681,11 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; +static inline bool temp_readonly(TCGTemp *ts) +{ + return ts->kind == TEMP_FIXED; +} + extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern TCGv_env cpu_env; diff --git a/tcg/tcg.c b/tcg/tcg.c index 07a25e59b6..54619c1cbc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3200,7 +3200,7 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (ts->kind == TEMP_FIXED) { + if (temp_readonly(ts)) { return; } if (ts->val_type == TEMP_VAL_REG) { @@ -3224,7 +3224,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (ts->kind == TEMP_FIXED) { + if (temp_readonly(ts)) { return; } if (!ts->mem_coherent) { @@ -3407,8 +3407,7 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) { /* The liveness analysis already ensures that globals are back in memory. Keep an tcg_debug_assert for safety. */ - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM - || ts->kind == TEMP_FIXED); + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); } /* save globals to their canonical location and assume they can be @@ -3488,7 +3487,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, TCGRegSet preferred_regs) { /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); /* The movi is not explicitly generated here. */ if (ots->val_type == TEMP_VAL_REG) { @@ -3528,7 +3527,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); /* Note that otype != itype for no-op truncation. */ otype = ots->type; @@ -3589,7 +3588,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) * Store the source register into the destination slot * and leave the destination temp as TEMP_VAL_MEM. */ - assert(ots->kind != TEMP_FIXED); + assert(!temp_readonly(ots)); if (!ts->mem_allocated) { temp_allocate_frame(s, ots); } @@ -3626,7 +3625,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) its = arg_temp(op->args[1]); /* ENV should not be modified. */ - tcg_debug_assert(ots->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ots)); itype = its->type; vece = TCGOP_VECE(op); @@ -3858,7 +3857,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg = new_args[arg_ct->alias_index]; @@ -3899,7 +3898,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) ts = arg_temp(op->args[i]); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); @@ -4031,7 +4030,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) ts = arg_temp(arg); /* ENV should not be modified. */ - tcg_debug_assert(ts->kind != TEMP_FIXED); + tcg_debug_assert(!temp_readonly(ts)); reg = tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] == NULL); From patchwork Thu Dec 17 14:51:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344945 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1296383ejs; Thu, 17 Dec 2020 07:04:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxozaDTvooMG6deHagSTfRBm7xv9kag8W7CylX5LayEbIN1M49jH+WCy5WCnrs57NT5C6HB X-Received: by 2002:a25:bec4:: with SMTP id k4mr54466431ybm.496.1608217471531; Thu, 17 Dec 2020 07:04:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217471; cv=none; d=google.com; s=arc-20160816; b=iVodTu+bnq6Nf5yeGff1x0YSqXyCXhR9X8nt9VpQWfxcKhPB9F9KNVF9fnYfuNBRqb iUUgbRcvRSlsaGXB00Kfy5NYoltTxSVDRtuPZ14pG18Z7jqJyMQkKgN+lk391RMofrsr 7Evo7Vlq+gKylVAOBr1LVXMDRknDThOEfLaIu3v57OzL6U9pWYPohmTl3vHqyNI1OZUf Z+qS+Nph3Gjrx7TEwXZDEo+7CZPkFdv9grmyjcrBCiEbjfZPuOx5kllXN4G7pnFIClpf E/+a0ldCzHbAM+dFrF/6t1vM4rcwTvh78C8HVt/seZR4dfgUS/Rff2s3hC5ihpIATvmw sNiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VSoOWcRdYXM6FZg9StjdneQwIVnMWszqCmEN1WyYVtk=; b=0ad3+CFb06avmHLJ3C/H6EiFTi+uuNgiH2c0o8GNjN9rrvtcwyU0btIMG57J1g9cxm btIRbsDwmXF7ocIDILR+w8FawhFEkZxlibTi7I5O4vN75xyFmOtkaD3//3+47A7XehTI 3fvqpByqRlEb7xFPS+D09CZGnoMRVV9BZtbcrAmX74F0jGpBeJpGhZIeYqUyBNTUYu5a IRfjya4yULdPwb72UfMJuGF9R4VUi4PMlcMdHYo03y5+ELXY17iyD/ZrHomQf0UOT/2K Z2tHFaCt6JFZjkxBwuxm6QonF43+hc4svqnBSQq55rLh1UkuGT4caj0jsEJnM84bxBrO gqGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C9+m/pRa"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/23] tcg: Expand TCGTemp.val to 64-bits Date: Thu, 17 Dec 2020 08:51:57 -0600 Message-Id: <20201217145215.534637-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will reduce the differences between 32-bit and 64-bit hosts, allowing full 64-bit constants to be created with the same interface. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9a9ced3b15..84491b5cf0 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -506,7 +506,7 @@ typedef struct TCGTemp { unsigned int mem_allocated:1; unsigned int temp_allocated:1; - tcg_target_long val; + int64_t val; struct TCGTemp *mem_base; intptr_t mem_offset; const char *name; diff --git a/tcg/tcg.c b/tcg/tcg.c index 54619c1cbc..69f748082d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3122,7 +3122,7 @@ static void dump_regs(TCGContext *s) tcg_target_reg_names[ts->mem_base->reg]); break; case TEMP_VAL_CONST: - printf("$0x%" TCG_PRIlx, ts->val); + printf("$0x%" PRIx64, ts->val); break; case TEMP_VAL_DEAD: printf("D"); From patchwork Thu Dec 17 14:51:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344940 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1290894ejs; Thu, 17 Dec 2020 06:58:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJzvaPd4ne5Rm4UAbNWaL4zVk/KVhhnLMhMgMhhQpOo+D1QHs4hLQLFy48sHUKzn1Ehzdng0 X-Received: by 2002:a25:4b42:: with SMTP id y63mr53523031yba.10.1608217130909; Thu, 17 Dec 2020 06:58:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217130; cv=none; d=google.com; s=arc-20160816; b=dmkn4MeMCOen/tClEtFuyzXPnuLC/QerLuhZC+Oe8PfdLV4IeA+S0D5rmpOR5WSG+R alMVd/SqDYlqSuBBDUXzRdamh3kUUwJVAkczS+wEqo1EJopDQGsrTwiJSnnBPDRLO3YD Xs9yjyTMvlcOp2RMNxlG5KEAknM3RXUciVkLZ6esd52gOvgRkH4UkUrIxEzfLoHP975a SqIiSqi+8xcyUN1w/bAO4wS+/PI2tl5/Fo1R0toIgdCt2cmoEDvcnvZzPybGFZF6g1m2 B/R789esJcs0JqnBWQgFJEpekrxiKKT+g24B22NOlKlrm71UMUl1Tid7C6bMa7OU5rfj PhBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bBAAD2EsIW/155GIjaU48r4O2esHCcXs+AbT7vfXmho=; b=vV45b8LiQa8hwyvanYCqC14GfOfHDBvXfLoIuedhVeDHZA+He8FDEoG2qx/Yyj1QxU k+x+WfAR6xOFDH1lfB4AaII8iHO+QbQPIvJrnct1UvF/1ygSPQcHNt18sR4FxOx5hjmu RTFEKCOnGMrE0dt3hZcMISQLv1nXyt8VcNgpWDaACxldo4cio0BuWXDNApA4u53NKknj +kisqPkvSkL+JDTi+PPKeRLLd0GdxqWEDj370DPcyT6cZYsFr+Qt5RFRM6yDHCJ+yl1N Po6yiM/jKeRgpBtbvIw1Rj5DlXpOMWnLhxRrBHzJHFJZNX8BQIYnXYfEE4VNfUEJ29+z 6wrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O/+k+KSr"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/23] tcg: Rename struct tcg_temp_info to TempOptInfo Date: Thu, 17 Dec 2020 08:51:58 -0600 Message-Id: <20201217145215.534637-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fix this name vs our coding style. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 3cffd941bd..81faf7cf10 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -35,20 +35,20 @@ glue(glue(case INDEX_op_, x), _i64): \ glue(glue(case INDEX_op_, x), _vec) -struct tcg_temp_info { +typedef struct TempOptInfo { bool is_const; TCGTemp *prev_copy; TCGTemp *next_copy; tcg_target_ulong val; tcg_target_ulong mask; -}; +} TempOptInfo; -static inline struct tcg_temp_info *ts_info(TCGTemp *ts) +static inline TempOptInfo *ts_info(TCGTemp *ts) { return ts->state_ptr; } -static inline struct tcg_temp_info *arg_info(TCGArg arg) +static inline TempOptInfo *arg_info(TCGArg arg) { return ts_info(arg_temp(arg)); } @@ -71,9 +71,9 @@ static inline bool ts_is_copy(TCGTemp *ts) /* Reset TEMP's state, possibly removing the temp for the list of copies. */ static void reset_ts(TCGTemp *ts) { - struct tcg_temp_info *ti = ts_info(ts); - struct tcg_temp_info *pi = ts_info(ti->prev_copy); - struct tcg_temp_info *ni = ts_info(ti->next_copy); + TempOptInfo *ti = ts_info(ts); + TempOptInfo *pi = ts_info(ti->prev_copy); + TempOptInfo *ni = ts_info(ti->next_copy); ni->prev_copy = ti->prev_copy; pi->next_copy = ti->next_copy; @@ -89,12 +89,12 @@ static void reset_temp(TCGArg arg) } /* Initialize and activate a temporary. */ -static void init_ts_info(struct tcg_temp_info *infos, +static void init_ts_info(TempOptInfo *infos, TCGTempSet *temps_used, TCGTemp *ts) { size_t idx = temp_idx(ts); if (!test_bit(idx, temps_used->l)) { - struct tcg_temp_info *ti = &infos[idx]; + TempOptInfo *ti = &infos[idx]; ts->state_ptr = ti; ti->next_copy = ts; @@ -105,7 +105,7 @@ static void init_ts_info(struct tcg_temp_info *infos, } } -static void init_arg_info(struct tcg_temp_info *infos, +static void init_arg_info(TempOptInfo *infos, TCGTempSet *temps_used, TCGArg arg) { init_ts_info(infos, temps_used, arg_temp(arg)); @@ -171,7 +171,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) const TCGOpDef *def; TCGOpcode new_op; tcg_target_ulong mask; - struct tcg_temp_info *di = arg_info(dst); + TempOptInfo *di = arg_info(dst); def = &tcg_op_defs[op->opc]; if (def->flags & TCG_OPF_VECTOR) { @@ -202,8 +202,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); const TCGOpDef *def; - struct tcg_temp_info *di; - struct tcg_temp_info *si; + TempOptInfo *di; + TempOptInfo *si; tcg_target_ulong mask; TCGOpcode new_op; @@ -236,7 +236,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) di->mask = mask; if (src_ts->type == dst_ts->type) { - struct tcg_temp_info *ni = ts_info(si->next_copy); + TempOptInfo *ni = ts_info(si->next_copy); di->next_copy = si->next_copy; di->prev_copy = src_ts; @@ -599,7 +599,7 @@ void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals; TCGOp *op, *op_next, *prev_mb = NULL; - struct tcg_temp_info *infos; + TempOptInfo *infos; TCGTempSet temps_used; /* Array VALS has an element for each temp. @@ -610,7 +610,7 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; bitmap_zero(temps_used.l, nb_temps); - infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); + infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { tcg_target_ulong mask, partmask, affected; From patchwork Thu Dec 17 14:51:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344954 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1310567ejs; Thu, 17 Dec 2020 07:20:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJyvoy7RdhywgE7vaJvlUu1R3eMieaKg9QtPIfoatxZMWizf/qYXWfe5uNC9D59haEM3QeZq X-Received: by 2002:a25:d788:: with SMTP id o130mr59375968ybg.245.1608218400773; Thu, 17 Dec 2020 07:20:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608218400; cv=none; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/23] tcg: Expand TempOptInfo to 64-bits Date: Thu, 17 Dec 2020 08:51:59 -0600 Message-Id: <20201217145215.534637-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This propagates the extended value of TCGTemp.val that we did before. In addition, it will be required for vector constants. Signed-off-by: Richard Henderson --- tcg/optimize.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 81faf7cf10..33d1fc8f87 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -39,8 +39,8 @@ typedef struct TempOptInfo { bool is_const; TCGTemp *prev_copy; TCGTemp *next_copy; - tcg_target_ulong val; - tcg_target_ulong mask; + uint64_t val; + uint64_t mask; } TempOptInfo; static inline TempOptInfo *ts_info(TCGTemp *ts) @@ -166,11 +166,11 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) { const TCGOpDef *def; TCGOpcode new_op; - tcg_target_ulong mask; + uint64_t mask; TempOptInfo *di = arg_info(dst); def = &tcg_op_defs[op->opc]; @@ -204,7 +204,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) const TCGOpDef *def; TempOptInfo *di; TempOptInfo *si; - tcg_target_ulong mask; + uint64_t mask; TCGOpcode new_op; if (ts_are_copies(dst_ts, src_ts)) { @@ -247,7 +247,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } -static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) +static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) { uint64_t l64, h64; @@ -410,10 +410,10 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) } } -static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) +static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) { const TCGOpDef *def = &tcg_op_defs[op]; - TCGArg res = do_constant_folding_2(op, x, y); + uint64_t res = do_constant_folding_2(op, x, y); if (!(def->flags & TCG_OPF_64BIT)) { res = (int32_t)res; } @@ -501,8 +501,9 @@ static bool do_constant_folding_cond_eq(TCGCond c) static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, TCGArg y, TCGCond c) { - tcg_target_ulong xv = arg_info(x)->val; - tcg_target_ulong yv = arg_info(y)->val; + uint64_t xv = arg_info(x)->val; + uint64_t yv = arg_info(y)->val; + if (arg_is_const(x) && arg_is_const(y)) { const TCGOpDef *def = &tcg_op_defs[op]; tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); @@ -613,9 +614,8 @@ void tcg_optimize(TCGContext *s) infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { - tcg_target_ulong mask, partmask, affected; + uint64_t mask, partmask, affected, tmp; int nb_oargs, nb_iargs, i; - TCGArg tmp; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -1221,14 +1221,15 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(extract2): if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - TCGArg v1 = arg_info(op->args[1])->val; - TCGArg v2 = arg_info(op->args[2])->val; + uint64_t v1 = arg_info(op->args[1])->val; + uint64_t v2 = arg_info(op->args[2])->val; + int shr = op->args[3]; if (opc == INDEX_op_extract2_i64) { - tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3])); + tmp = (v1 >> shr) | (v2 << (64 - shr)); } else { - tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) | - ((uint32_t)v2 << (32 - op->args[3]))); + tmp = (int32_t)(((uint32_t)v1 >> shr) | + ((uint32_t)v2 << (32 - shr))); } tcg_opt_gen_movi(s, op, op->args[0], tmp); break; @@ -1267,9 +1268,10 @@ void tcg_optimize(TCGContext *s) break; } if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { - tcg_target_ulong tv = arg_info(op->args[3])->val; - tcg_target_ulong fv = arg_info(op->args[4])->val; + uint64_t tv = arg_info(op->args[3])->val; + uint64_t fv = arg_info(op->args[4])->val; TCGCond cond = op->args[5]; + if (fv == 1 && tv == 0) { cond = tcg_invert_cond(cond); } else if (!(tv == 1 && fv == 0)) { From patchwork Thu Dec 17 14:52:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344951 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1306156ejs; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/23] tcg: Introduce TYPE_CONST temporaries Date: Thu, 17 Dec 2020 08:52:00 -0600 Message-Id: <20201217145215.534637-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 24 ++++- tcg/optimize.c | 13 ++- tcg/tcg.c | 224 ++++++++++++++++++++++++++++++++++++---------- 3 files changed, 211 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 84491b5cf0..995db20d02 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -492,6 +492,8 @@ typedef enum TCGTempKind { TEMP_GLOBAL, /* Temp is in a fixed register. */ TEMP_FIXED, + /* Temp is a fixed constant. */ + TEMP_CONST, } TCGTempKind; typedef struct TCGTemp { @@ -667,6 +669,7 @@ struct TCGContext { QSIMPLEQ_HEAD(, TCGOp) plugin_ops; #endif + GHashTable *const_table[TCG_TYPE_COUNT]; TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ @@ -683,7 +686,7 @@ struct TCGContext { static inline bool temp_readonly(TCGTemp *ts) { - return ts->kind == TEMP_FIXED; + return ts->kind >= TEMP_FIXED; } extern TCGContext tcg_init_ctx; @@ -1053,6 +1056,7 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); void tcg_optimize(TCGContext *s); +/* Allocate a new temporary and initialize it with a constant. */ TCGv_i32 tcg_const_i32(int32_t val); TCGv_i64 tcg_const_i64(int64_t val); TCGv_i32 tcg_const_local_i32(int32_t val); @@ -1062,6 +1066,24 @@ TCGv_vec tcg_const_ones_vec(TCGType); TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); +/* + * Locate or create a read-only temporary that is a constant. + * This kind of temporary need not and should not be freed. + */ +TCGTemp *tcg_constant_internal(TCGType type, int64_t val); + +static inline TCGv_i32 tcg_constant_i32(int32_t val) +{ + return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); +} + +static inline TCGv_i64 tcg_constant_i64(int64_t val) +{ + return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); +} + +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); + #if UINTPTR_MAX == UINT32_MAX # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) diff --git a/tcg/optimize.c b/tcg/optimize.c index 33d1fc8f87..c0fd65d2e4 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -99,8 +99,17 @@ static void init_ts_info(TempOptInfo *infos, ts->state_ptr = ti; ti->next_copy = ts; ti->prev_copy = ts; - ti->is_const = false; - ti->mask = -1; + if (ts->kind == TEMP_CONST) { + ti->is_const = true; + ti->val = ti->mask = ts->val; + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { + /* High bits of a 32-bit quantity are garbage. */ + ti->mask |= ~0xffffffffull; + } + } else { + ti->is_const = false; + ti->mask = -1; + } set_bit(idx, temps_used->l); } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 69f748082d..93f525ea3f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1134,6 +1134,13 @@ void tcg_func_start(TCGContext *s) /* No temps have been previously allocated for size or locality. */ memset(s->free_temps, 0, sizeof(s->free_temps)); + /* No constant temps have been previously allocated. */ + for (int i = 0; i < TCG_TYPE_COUNT; ++i) { + if (s->const_table[i]) { + g_hash_table_remove_all(s->const_table[i]); + } + } + s->nb_ops = 0; s->nb_labels = 0; s->current_frame_offset = s->frame_start; @@ -1205,13 +1212,19 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, bigendian = 1; #endif - if (base_ts->kind != TEMP_FIXED) { + switch (base_ts->kind) { + case TEMP_FIXED: + break; + case TEMP_GLOBAL: /* We do not support double-indirect registers. */ tcg_debug_assert(!base_ts->indirect_reg); base_ts->indirect_base = 1; s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 ? 2 : 1); indirect_reg = 1; + break; + default: + g_assert_not_reached(); } if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { @@ -1336,6 +1349,11 @@ void tcg_temp_free_internal(TCGTemp *ts) TCGContext *s = tcg_ctx; int k, idx; + /* In order to simplify users of tcg_constant_*, silently ignore free. */ + if (ts->kind == TEMP_CONST) { + return; + } + #if defined(CONFIG_DEBUG_TCG) s->temps_in_use--; if (s->temps_in_use < 0) { @@ -1352,6 +1370,60 @@ void tcg_temp_free_internal(TCGTemp *ts) set_bit(idx, s->free_temps[k].l); } +TCGTemp *tcg_constant_internal(TCGType type, int64_t val) +{ + TCGContext *s = tcg_ctx; + GHashTable *h = s->const_table[type]; + TCGTemp *ts; + + if (h == NULL) { + h = g_hash_table_new(g_int64_hash, g_int64_equal); + s->const_table[type] = h; + } + + ts = g_hash_table_lookup(h, &val); + if (ts == NULL) { + ts = tcg_temp_alloc(s); + + if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { + TCGTemp *ts2 = tcg_temp_alloc(s); + + ts->base_type = TCG_TYPE_I64; + ts->type = TCG_TYPE_I32; + ts->kind = TEMP_CONST; + ts->temp_allocated = 1; + /* + * Retain the full value of the 64-bit constant in the low + * part, so that the hash table works. Actual uses will + * truncate the value to the low part. + */ + ts->val = val; + + tcg_debug_assert(ts2 == ts + 1); + ts2->base_type = TCG_TYPE_I64; + ts2->type = TCG_TYPE_I32; + ts2->kind = TEMP_CONST; + ts2->temp_allocated = 1; + ts2->val = val >> 32; + } else { + ts->base_type = type; + ts->type = type; + ts->kind = TEMP_CONST; + ts->temp_allocated = 1; + ts->val = val; + } + g_hash_table_insert(h, &ts->val, ts); + } + + return ts; +} + +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) +{ + val = dup_const(vece, val); + return temp_tcgv_vec(tcg_constant_internal(type, val)); +} + TCGv_i32 tcg_const_i32(int32_t val) { TCGv_i32 t0; @@ -1884,6 +1956,9 @@ static void tcg_reg_alloc_start(TCGContext *s) TCGTempVal val = TEMP_VAL_MEM; switch (ts->kind) { + case TEMP_CONST: + val = TEMP_VAL_CONST; + break; case TEMP_FIXED: val = TEMP_VAL_REG; break; @@ -1920,6 +1995,26 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, case TEMP_NORMAL: snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); break; + case TEMP_CONST: + switch (ts->type) { + case TCG_TYPE_I32: + snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); + break; +#if TCG_TARGET_REG_BITS > 32 + case TCG_TYPE_I64: + snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); + break; +#endif + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + snprintf(buf, buf_size, "v%d$0x%" PRIx64, + 64 << (ts->type - TCG_TYPE_V64), ts->val); + break; + default: + g_assert_not_reached(); + } + break; } return buf; } @@ -2520,6 +2615,7 @@ static void la_bb_end(TCGContext *s, int ng, int nt) state = TS_DEAD | TS_MEM; break; case TEMP_NORMAL: + case TEMP_CONST: state = TS_DEAD; break; default: @@ -2554,14 +2650,24 @@ static void la_bb_sync(TCGContext *s, int ng, int nt) la_global_sync(s, ng); for (int i = ng; i < nt; ++i) { - if (s->temps[i].kind == TEMP_LOCAL) { - int state = s->temps[i].state; - s->temps[i].state = state | TS_MEM; + TCGTemp *ts = &s->temps[i]; + int state; + + switch (ts->kind) { + case TEMP_LOCAL: + state = ts->state; + ts->state = state | TS_MEM; if (state != TS_DEAD) { continue; } - } else { + break; + case TEMP_NORMAL: s->temps[i].state = TS_DEAD; + break; + case TEMP_CONST: + continue; + default: + g_assert_not_reached(); } la_reset_pref(&s->temps[i]); } @@ -3200,15 +3306,28 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); mark it free; otherwise mark it dead. */ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) { - if (temp_readonly(ts)) { + TCGTempVal new_type; + + switch (ts->kind) { + case TEMP_FIXED: return; + case TEMP_GLOBAL: + case TEMP_LOCAL: + new_type = TEMP_VAL_MEM; + break; + case TEMP_NORMAL: + new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; + break; + case TEMP_CONST: + new_type = TEMP_VAL_CONST; + break; + default: + g_assert_not_reached(); } if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = NULL; } - ts->val_type = (free_or_dead < 0 - || ts->kind != TEMP_NORMAL - ? TEMP_VAL_MEM : TEMP_VAL_DEAD); + ts->val_type = new_type; } /* Mark a temporary as dead. */ @@ -3224,10 +3343,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, TCGRegSet preferred_regs, int free_or_dead) { - if (temp_readonly(ts)) { - return; - } - if (!ts->mem_coherent) { + if (!temp_readonly(ts) && !ts->mem_coherent) { if (!ts->mem_allocated) { temp_allocate_frame(s, ts); } @@ -3445,12 +3561,22 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) for (i = s->nb_globals; i < s->nb_temps; i++) { TCGTemp *ts = &s->temps[i]; - if (ts->kind == TEMP_LOCAL) { + + switch (ts->kind) { + case TEMP_LOCAL: temp_save(s, ts, allocated_regs); - } else { + break; + case TEMP_NORMAL: /* The liveness analysis already ensures that temps are dead. Keep an tcg_debug_assert for safety. */ tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); + break; + case TEMP_CONST: + /* Similarly, we should have freed any allocated register. */ + tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); + break; + default: + g_assert_not_reached(); } } @@ -3471,10 +3597,17 @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) * The liveness analysis already ensures that temps are dead. * Keep tcg_debug_asserts for safety. */ - if (ts->kind == TEMP_LOCAL) { + switch (ts->kind) { + case TEMP_LOCAL: tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); - } else { + break; + case TEMP_NORMAL: tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); + break; + case TEMP_CONST: + break; + default: + g_assert_not_reached(); } } } @@ -3765,45 +3898,42 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) i_preferred_regs = o_preferred_regs = 0; if (arg_ct->ialias) { o_preferred_regs = op->output_pref[arg_ct->alias_index]; - if (ts->kind == TEMP_FIXED) { - /* if fixed register, we must allocate a new register - if the alias is not the same register */ - if (arg != op->args[arg_ct->alias_index]) { - goto allocate_in_reg; - } - } else { - /* if the input is aliased to an output and if it is - not dead after the instruction, we must allocate - a new register and move it */ - if (!IS_DEAD_ARG(i)) { - goto allocate_in_reg; - } - /* check if the current register has already been allocated - for another input aliased to an output */ - if (ts->val_type == TEMP_VAL_REG) { - int k2, i2; - reg = ts->reg; - for (k2 = 0 ; k2 < k ; k2++) { - i2 = def->args_ct[nb_oargs + k2].sort_index; - if (def->args_ct[i2].ialias && reg == new_args[i2]) { - goto allocate_in_reg; - } + /* + * If the input is readonly, then it cannot also be an + * output and aliased to itself. If the input is not + * dead after the instruction, we must allocate a new + * register and move it. + */ + if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { + goto allocate_in_reg; + } + + /* + * Check if the current register has already been allocated + * for another input aliased to an output. + */ + if (ts->val_type == TEMP_VAL_REG) { + reg = ts->reg; + for (int k2 = 0; k2 < k; k2++) { + int i2 = def->args_ct[nb_oargs + k2].sort_index; + if (def->args_ct[i2].ialias && reg == new_args[i2]) { + goto allocate_in_reg; } } - i_preferred_regs = o_preferred_regs; } + i_preferred_regs = o_preferred_regs; } temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); reg = ts->reg; - if (tcg_regset_test_reg(arg_ct->regs, reg)) { - /* nothing to do : the constraint is satisfied */ - } else { - allocate_in_reg: - /* allocate a new register matching the constraint - and move the temporary register into it */ + if (!tcg_regset_test_reg(arg_ct->regs, reg)) { + allocate_in_reg: + /* + * Allocate a new register matching the constraint + * and move the temporary register into it. + */ temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, From patchwork Thu Dec 17 14:52:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344948 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1303097ejs; Thu, 17 Dec 2020 07:11:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJy+XJhqd/Ug9BI2uK4ZuqmYh8EB/q2glR9/zomVM9NfJA4afwYcbuAyOmNnWXRyU+NcZdfT X-Received: by 2002:a25:7e03:: with SMTP id z3mr58268962ybc.251.1608217900881; Thu, 17 Dec 2020 07:11:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217900; cv=none; d=google.com; s=arc-20160816; b=jrasCcafz8Nct3UQwllExmfkaFYUozuO4SP0pwMN+CeFPsfQbcoou3l34USKg+yaMd lD314evAkiqcwWNanGusb38tftlL67U1QgxQLUcn13F8teGds+4IFKNhGoPZwzCGxYp+ b3ZwAPfi8xaD4glRpkUwK/5gygaBSZMvTET4SDK3Jhnenfla8AqS7JLXzOErnZtcGNiL DDVyUP5JQzNcQUyvMOKniD3x4Pd2+FehqwreAEyC5GuNPRl94zs4AUXllszuQThXE4Xg 6BZar3/icfGHVAS8OIsHRLH71U0J8Nh2ZfEgqhJuRxVI/9d5c92R4LB7igilLOnrCAvV J1rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=x+s9W4S8X9df0AJnC/pFDE7SPPgT3/tOf2XSzgDEzSo=; b=r9RYiFGQHVsnTdky7wMyhYvnpEpT+Boqh4/LfVqu7XyBCL8nPntZxDbV066vB7XmX4 AUZ0iWDSbcuOOyHOiBVNC7htDwUan78tWdfAw2wca3C1IWT4PhlaWYvS4BYJN71Db2+2 NXOqZEu/4UwK+JXhxWcUAOB9KG9F9JNf/kU/hI/CBAAqrO9mSTQpT3/akr/Pow2bLCO5 pSRJTu8WTZ7GcOsMmMNm3DCxxSFvABj4Xs8kjX3kLvi4fDyPSGt4fE3ATesvhlS1YCR/ 4a20tY6S8TsegsFJsndS5wFFOLGiNN9swQ6v88ULGICqSTFaBYfWMOYFcZ4iV8ek+Hc3 +bIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Y45N7SZ/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/23] tcg/optimize: Improve find_better_copy Date: Thu, 17 Dec 2020 08:52:01 -0600 Message-Id: <20201217145215.534637-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Prefer TEMP_CONST over anything else. Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index c0fd65d2e4..bf2c2a3ce5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -122,31 +122,28 @@ static void init_arg_info(TempOptInfo *infos, static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) { - TCGTemp *i; + TCGTemp *i, *g, *l; - /* If this is already a global, we can't do better. */ - if (ts->kind >= TEMP_GLOBAL) { + /* If this is already readonly, we can't do better. */ + if (temp_readonly(ts)) { return ts; } - /* Search for a global first. */ + g = l = NULL; for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->kind >= TEMP_GLOBAL) { + if (temp_readonly(i)) { return i; - } - } - - /* If it is a temp, search for a temp local. */ - if (ts->kind == TEMP_NORMAL) { - for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { - if (i->kind >= TEMP_LOCAL) { - return i; + } else if (i->kind > ts->kind) { + if (i->kind == TEMP_GLOBAL) { + g = i; + } else if (i->kind == TEMP_LOCAL) { + l = i; } } } - /* Failure to find a better representation, return the same temp. */ - return ts; + /* If we didn't find a better representation, return the same temp. */ + return g ? g : l ? l : ts; } static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) From patchwork Thu Dec 17 14:52:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344935 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1287898ejs; Thu, 17 Dec 2020 06:54:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJzE68Yk4ouVaTxjkd2TgOG5vUMFNmIlrS0IsXFTGRxjRy3bhRqqkvw5CSmykYasbxNYqmfk X-Received: by 2002:a5b:c0b:: with SMTP id f11mr55076680ybq.158.1608216863084; Thu, 17 Dec 2020 06:54:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608216863; cv=none; d=google.com; s=arc-20160816; b=T/2MNJL2XbcONRKcI34QRmckV/oDpLbbwir7CjsnymHPe5GJmCzRW1NHEDMdaQgqmr CCrJrOHBLFWeAJPOEFj5wg31YF7SJAVExtHtyYC4HxA240CpTTmePi5K/TD1STEpk5F+ jUJUj8vFBy/4R5o5BauWiNUdi8QbiQvgeZlBCPHb8e0gSM5AEAN7PeUwzMXKwR2Z2vkF O9c8D5hwxQ7KUKkrgMWWU+2Ts5GxwtKYvZUKn4zseO5FTRvd6oVLYhvJOpdoTMhM+gTY N/fpPYujKbTteEWLbKRVfq8zJYzRBId4wtQUJ0KyyFUcjly2wzAYJXMIl65nYzjc5/Ti ulTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1NhNPEIDsGzd2+XZQVnWFC0k3zKAB+Awk5/hTm4NEwE=; b=iXfo7rxoFrTmpYYMJPBWE4YUdl10Aa2Qfc/ZE3Ak+U9U9r6YT0BEOy+gX+gX6Klt79 GlAWptbKfc0QJ/29GzQrHZQN+MoFdrrlHpuSrjyHldG7jeRe0BvxhCX1SxhbjBDPL83U 2XUtt6vrrJV6MCFmPzQdWasasfNYF8KSBnb0IO3tZNuUj7swdK/EESXhaaLh/mr/bNv5 motH4oViu/oHWm5j3xdl2D7siEn4FIObwUpOI51jgfDbpngFWTVLJmYGERqX09lYXG7L pts6K494H1dAgsUDgEgkyrOBhEkOCEUSVLuxK3xSX5Q79NU52PiyGs5Im8NGCurSy4Vb oOKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RBCr7+n/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/23] tcg/optimize: Adjust TempOptInfo allocation Date: Thu, 17 Dec 2020 08:52:02 -0600 Message-Id: <20201217145215.534637-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 ++++++++++++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index bf2c2a3ce5..e269962932 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -89,35 +89,41 @@ static void reset_temp(TCGArg arg) } /* Initialize and activate a temporary. */ -static void init_ts_info(TempOptInfo *infos, - TCGTempSet *temps_used, TCGTemp *ts) +static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) { size_t idx = temp_idx(ts); - if (!test_bit(idx, temps_used->l)) { - TempOptInfo *ti = &infos[idx]; + TempOptInfo *ti; + if (test_bit(idx, temps_used->l)) { + return; + } + set_bit(idx, temps_used->l); + + ti = ts->state_ptr; + if (ti == NULL) { + ti = tcg_malloc(sizeof(TempOptInfo)); ts->state_ptr = ti; - ti->next_copy = ts; - ti->prev_copy = ts; - if (ts->kind == TEMP_CONST) { - ti->is_const = true; - ti->val = ti->mask = ts->val; - if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { - /* High bits of a 32-bit quantity are garbage. */ - ti->mask |= ~0xffffffffull; - } - } else { - ti->is_const = false; - ti->mask = -1; + } + + ti->next_copy = ts; + ti->prev_copy = ts; + if (ts->kind == TEMP_CONST) { + ti->is_const = true; + ti->val = ts->val; + ti->mask = ts->val; + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { + /* High bits of a 32-bit quantity are garbage. */ + ti->mask |= ~0xffffffffull; } - set_bit(idx, temps_used->l); + } else { + ti->is_const = false; + ti->mask = -1; } } -static void init_arg_info(TempOptInfo *infos, - TCGTempSet *temps_used, TCGArg arg) +static void init_arg_info(TCGTempSet *temps_used, TCGArg arg) { - init_ts_info(infos, temps_used, arg_temp(arg)); + init_ts_info(temps_used, arg_temp(arg)); } static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) @@ -604,9 +610,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { - int nb_temps, nb_globals; + int nb_temps, nb_globals, i; TCGOp *op, *op_next, *prev_mb = NULL; - TempOptInfo *infos; TCGTempSet temps_used; /* Array VALS has an element for each temp. @@ -616,12 +621,15 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; + bitmap_zero(temps_used.l, nb_temps); - infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); + for (i = 0; i < nb_temps; ++i) { + s->temps[i].state_ptr = NULL; + } QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { uint64_t mask, partmask, affected, tmp; - int nb_oargs, nb_iargs, i; + int nb_oargs, nb_iargs; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -633,14 +641,14 @@ void tcg_optimize(TCGContext *s) for (i = 0; i < nb_oargs + nb_iargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); if (ts) { - init_ts_info(infos, &temps_used, ts); + init_ts_info(&temps_used, ts); } } } else { nb_oargs = def->nb_oargs; nb_iargs = def->nb_iargs; for (i = 0; i < nb_oargs + nb_iargs; i++) { - init_arg_info(infos, &temps_used, op->args[i]); + init_arg_info(&temps_used, op->args[i]); } } From patchwork Thu Dec 17 14:52:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344956 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1267512jai; Thu, 17 Dec 2020 07:24:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJwrr5Uw5DihmbY+mvmYo83xVpBt7M4vr6v/i5T6XhrTiKOq/CBAiFtpbO3ba1gotbJd+QnS X-Received: by 2002:a5b:44d:: with SMTP id s13mr53611694ybp.300.1608218668780; Thu, 17 Dec 2020 07:24:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608218668; cv=none; d=google.com; s=arc-20160816; b=pqi/pZLRFdtYg0BK0k+SZ9FoOrCiVMAXkTRShom1j3SBXM2/buxL+F5Bm9LaJ/vJ43 aShbNaxhMW53ZpyuczWjUIFFaRul7edU9gpvuIU8CJHg42KAdi58YTw2g8gho1zRjUO9 ux951xUZwp5uwiHblhDgWluGN7KXKJuWtBoIL/RGcQQWP3NX1SQ5gW/Dt1fdt5tgeh4K NtpN3XemkanW1EUW/doMgYZ2ykb0zDRHo4zZKnmMoj0yX4L2ZMi3RQrxddBd1ay7Drit Pe9lcs4jLBPOqfX1gmKmgi0MMORhPHrNbmEphqD5iUlW/RWWmW1dUH5VtUeIPFwrfL1Z axNw== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/23] tcg/optimize: Use tcg_constant_internal with constant folding Date: Thu, 17 Dec 2020 08:52:03 -0600 Message-Id: <20201217145215.534637-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 108 ++++++++++++++++++++++--------------------------- 1 file changed, 49 insertions(+), 59 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index e269962932..1eda7dc419 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -178,37 +178,6 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) -{ - const TCGOpDef *def; - TCGOpcode new_op; - uint64_t mask; - TempOptInfo *di = arg_info(dst); - - def = &tcg_op_defs[op->opc]; - if (def->flags & TCG_OPF_VECTOR) { - new_op = INDEX_op_dupi_vec; - } else if (def->flags & TCG_OPF_64BIT) { - new_op = INDEX_op_movi_i64; - } else { - new_op = INDEX_op_movi_i32; - } - op->opc = new_op; - /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ - op->args[0] = dst; - op->args[1] = val; - - reset_temp(dst); - di->is_const = true; - di->val = val; - mask = val; - if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) { - /* High bits of the destination are now garbage. */ - mask |= ~0xffffffffull; - } - di->mask = mask; -} - static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); @@ -259,6 +228,27 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } +static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used, + TCGOp *op, TCGArg dst, uint64_t val) +{ + const TCGOpDef *def = &tcg_op_defs[op->opc]; + TCGType type; + TCGTemp *tv; + + if (def->flags & TCG_OPF_VECTOR) { + type = TCGOP_VECL(op) + TCG_TYPE_V64; + } else if (def->flags & TCG_OPF_64BIT) { + type = TCG_TYPE_I64; + } else { + type = TCG_TYPE_I32; + } + + /* Convert movi to mov with constant temp. */ + tv = tcg_constant_internal(type, val); + init_ts_info(temps_used, tv); + tcg_opt_gen_mov(s, op, dst, temp_arg(tv)); +} + static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) { uint64_t l64, h64; @@ -622,7 +612,7 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); for (i = 0; i < nb_temps; ++i) { s->temps[i].state_ptr = NULL; } @@ -727,7 +717,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(rotr): if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1050,7 +1040,7 @@ void tcg_optimize(TCGContext *s) if (partmask == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } if (affected == 0) { @@ -1067,7 +1057,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mulsh): if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1094,7 +1084,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): CASE_OP_32_64_VEC(xor): if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_movi(s, op, op->args[0], 0); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); continue; } break; @@ -1111,14 +1101,14 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(movi): case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { tmp = arg_info(op->args[1])->val; tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1128,7 +1118,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = arg_info(op->args[1])->val; if (tmp == arg_info(op->args[2])->val) { - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } } else if (args_are_copies(op->args[1], op->args[2])) { @@ -1156,7 +1146,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1186,7 +1176,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1197,7 +1187,7 @@ void tcg_optimize(TCGContext *s) TCGArg v = arg_info(op->args[1])->val; if (v != 0) { tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); } else { tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); } @@ -1210,7 +1200,7 @@ void tcg_optimize(TCGContext *s) tmp = deposit64(arg_info(op->args[1])->val, op->args[3], op->args[4], arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1219,7 +1209,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1228,7 +1218,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1245,7 +1235,7 @@ void tcg_optimize(TCGContext *s) tmp = (int32_t)(((uint32_t)v1 >> shr) | ((uint32_t)v2 << (32 - shr))); } - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1254,7 +1244,7 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); if (tmp != 2) { - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); break; } goto do_default; @@ -1264,7 +1254,7 @@ void tcg_optimize(TCGContext *s) op->args[1], op->args[2]); if (tmp != 2) { if (tmp) { - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[3]; } else { @@ -1310,7 +1300,7 @@ void tcg_optimize(TCGContext *s) uint64_t a = ((uint64_t)ah << 32) | al; uint64_t b = ((uint64_t)bh << 32) | bl; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); if (opc == INDEX_op_add2_i32) { a += b; @@ -1320,8 +1310,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a); + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32)); break; } goto do_default; @@ -1332,12 +1322,12 @@ void tcg_optimize(TCGContext *s) uint32_t b = arg_info(op->args[3])->val; uint64_t r = (uint64_t)a * b; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, op, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r); + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32)); break; } goto do_default; @@ -1348,7 +1338,7 @@ void tcg_optimize(TCGContext *s) if (tmp != 2) { if (tmp) { do_brcond_true: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[5]; } else { @@ -1364,7 +1354,7 @@ void tcg_optimize(TCGContext *s) /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_brcond_i32; op->args[0] = op->args[1]; op->args[1] = op->args[3]; @@ -1390,7 +1380,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); op->opc = INDEX_op_brcond_i32; op->args[1] = op->args[2]; op->args[2] = op->args[4]; @@ -1425,7 +1415,7 @@ void tcg_optimize(TCGContext *s) op->args[5]); if (tmp != 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); } else if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) && arg_is_const(op->args[3]) @@ -1510,7 +1500,7 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - bitmap_zero(temps_used.l, nb_temps); + memset(&temps_used, 0, sizeof(temps_used)); } else { do_reset_output: for (i = 0; i < nb_oargs; i++) { From patchwork Thu Dec 17 14:52:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344934 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1287792ejs; Thu, 17 Dec 2020 06:54:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJw5pvbdRb71zF6mlJvgAH68hTCEZ71fC1yfRFh+rTJKTo6CpWD1v+r/LCgVkDZBRTb6jPT5 X-Received: by 2002:a25:d44:: with SMTP id 65mr58004512ybn.260.1608216855015; Thu, 17 Dec 2020 06:54:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608216855; cv=none; d=google.com; s=arc-20160816; b=cDoI9+mm/b8H+fGYt2oQ1R2OwBpoYOR/nB3msqkV9qp992bOHW1hNOLiQEef0sFBy4 +ptCoprJ7L90az2xf1hK+AGISGWA61DQ8NJl3KuELSCJNacgDmrJ3bklgv4l9HwU9hha h7nFkwQGBOUVwR2csRdDHa/A1pwby3Wxf2qbnGWw/87FN4sgU9l6F2Xs9a311m9hHI53 ZwV3ZynQk2hiOwjxN9emvo4XFTXiVa6hMPBlI5OTVUNmG1te/jylvD+3OvvFjauS+AvR D8tnqZVlDPXcAwXckbpTO01V+Q9U2CEln2tgWv+GOC+aGqhZ3l/e3mpN1JX8F85IYRus cRAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v7Fq+nWbx6XhMoBO6EO91HUGM4GfBbdLJgZ/TQ6xfhk=; b=CP3wSgcA2HRQqACs/3W7AYBKEQOVDj8NNk4tCr2rHUS4D9MkgHW+9+fveTrrYI6PpZ TDJL/yHUGDlUDB7SNXE7PbNenn+/4oW4dKltqlqFLqJOG3zFy2n+nbAnqKwu29k7Ju+l szwDAt+PqnCruC2+jgOa5nKlXUy9p3fsMGcy6i37xD0qvsWddDROIxv+CzDD3NM9lfqL MUnHC3CyRsJlzbdvvosWTf+JySB9QWicHadcpL4U7FJx5GFxo+ag+wB3WFbNAZd1W2fK PU1W1wo3zbyo/jlNu7Ml/dOAhMIQXAMSw18o2S6ItxOGmGQCSCWUzQ6u0bvrX+piyIrB O02A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O/YZcRp7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/23] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Date: Thu, 17 Dec 2020 08:52:04 -0600 Message-Id: <20201217145215.534637-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because we now store uint64_t in TCGTemp, we can now always store the full 64-bit duplicate immediate. So remove the difference between 32- and 64-bit hosts. Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++++----- tcg/tcg-op-vec.c | 39 ++++++++++----------------------------- tcg/tcg.c | 7 +------ 3 files changed, 15 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 1eda7dc419..af07c6f628 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1116,11 +1116,10 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS == 32); if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = arg_info(op->args[1])->val; - if (tmp == arg_info(op->args[2])->val) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); - break; - } + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], + deposit64(arg_info(op->args[1])->val, 32, 32, + arg_info(op->args[2])->val)); + break; } else if (args_are_copies(op->args[1], op->args[2])) { op->opc = INDEX_op_dup_vec; TCGOP_VECE(op) = MO_32; diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cdbf11c573..9fbed1366c 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -216,25 +216,17 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a) } } -#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32) - -static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a) -{ - TCGTemp *rt = tcgv_vec_temp(r); - vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a); -} - TCGv_vec tcg_const_zeros_vec(TCGType type) { TCGv_vec ret = tcg_temp_new_vec(type); - do_dupi_vec(ret, MO_REG, 0); + tcg_gen_dupi_vec(MO_64, ret, 0); return ret; } TCGv_vec tcg_const_ones_vec(TCGType type) { TCGv_vec ret = tcg_temp_new_vec(type); - do_dupi_vec(ret, MO_REG, -1); + tcg_gen_dupi_vec(MO_64, ret, -1); return ret; } @@ -252,39 +244,28 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) { - if (TCG_TARGET_REG_BITS == 64) { - do_dupi_vec(r, MO_64, a); - } else if (a == dup_const(MO_32, a)) { - do_dupi_vec(r, MO_32, a); - } else { - TCGv_i64 c = tcg_const_i64(a); - tcg_gen_dup_i64_vec(MO_64, r, c); - tcg_temp_free_i64(c); - } + tcg_gen_dupi_vec(MO_64, r, a); } void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_32, a)); + tcg_gen_dupi_vec(MO_32, r, a); } void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_16, a)); + tcg_gen_dupi_vec(MO_16, r, a); } void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) { - do_dupi_vec(r, MO_REG, dup_const(MO_8, a)); + tcg_gen_dupi_vec(MO_8, r, a); } void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { - if (vece == MO_64) { - tcg_gen_dup64i_vec(r, a); - } else { - do_dupi_vec(r, MO_REG, dup_const(vece, a)); - } + TCGTemp *rt = tcgv_vec_temp(r); + tcg_gen_mov_vec(r, tcg_constant_vec(rt->base_type, vece, a)); } void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) @@ -489,8 +470,8 @@ void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); } else { - do_dupi_vec(t, MO_REG, 0); - tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t); + tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, + tcg_constant_vec(type, vece, 0)); } tcg_gen_xor_vec(vece, r, a, t); tcg_gen_sub_vec(vece, r, r, t); diff --git a/tcg/tcg.c b/tcg/tcg.c index 93f525ea3f..500663e3f5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3485,16 +3485,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, * The targets will, in general, have to do this search anyway, * do this generically. */ - if (TCG_TARGET_REG_BITS == 32) { - val = dup_const(MO_32, val); - vece = MO_32; - } if (val == dup_const(MO_8, val)) { vece = MO_8; } else if (val == dup_const(MO_16, val)) { vece = MO_16; - } else if (TCG_TARGET_REG_BITS == 64 && - val == dup_const(MO_32, val)) { + } else if (val == dup_const(MO_32, val)) { vece = MO_32; } From patchwork Thu Dec 17 14:52:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344955 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1266338jai; Thu, 17 Dec 2020 07:23:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJx1lqIAcyy/uBGUUhavNjG/4YsmynjQv1dkSJXSztr0Q7eQyt+iW2QpZV0O+ClsmB7pf/r8 X-Received: by 2002:a25:5f49:: with SMTP id h9mr55550883ybm.99.1608218586617; Thu, 17 Dec 2020 07:23:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608218586; cv=none; d=google.com; s=arc-20160816; b=QtsmxXa6hcASC3MWloh2ZkzgN2zbQzE7gZWUKEeLBjf3ICIidEbQVM+bHai/ktvC8w CCov6Hl6MCPHXQC/F7vlTfqT1IdQIjhvJ1RcK8GQUxXhrcTuHcieMVhFXOmoLoO5N9Jq Gh35rpfRjla/zcEA8wU+Nkn+054VEb0Q8pZ36TewwL0V4ohhXNr3WqOPx3LRnfHJ2wu6 QHbzpEdFmuSI0WRuM16gjcfXf/5ZLm/veimRQCLdzxoWuHcWncmA7nsLDqa+hOga1lcg ufLC9c0YSZXDd+ixAoh8y7qNA7DWqYp29lstNr12j8Cs/CEoSuOneu+ndDXX1HCbCxOR ZBng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mEMZJyAsz2pya7wCS7q3Y/mkN8EK0RWNbiEA9tVJa2o=; b=Ri33U6BYKaLsWB4CqYM7wHZ8S+Qq+Ofq9BulXgwNpXJUchIpNdntmNVtkePedPIWZL VctqoW/JTLz4E7aNA9lNZ/nB+mZ2DAKar6UQ/PSh1k44Vu0U3MOvKEepyGS9a60l1Ga8 fHAF6A2B7IZpuWVgoGsZKaTXU/XU69wVzJzX8EBVPJFUvGHjA8YSZWvHRDhEyITqnQcF +A9pCoWvdMNvLNw10YEJjuHQFA5ymv1AGzfF9Nq+NR96RpvSpykwIwnFz6drVPfWa5Ys CiXT6obIMLKpk24JCNerNoLWMhoHan52H21x+fGEiIu6feLNHG6DPdwHurPZMyBt9Tvl 00ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F3hKtjar; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/23] tcg: Use tcg_constant_i32 with icount expander Date: Thu, 17 Dec 2020 08:52:05 -0600 Message-Id: <20201217145215.534637-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must do this before we adjust tcg_out_movi_i32, lest the under-the-hood poking that we do for icount be broken. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 822c43cfd3..404732518a 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -34,7 +34,7 @@ static inline void gen_io_end(void) static inline void gen_tb_start(TranslationBlock *tb) { - TCGv_i32 count, imm; + TCGv_i32 count; tcg_ctx->exitreq_label = gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -48,15 +48,13 @@ static inline void gen_tb_start(TranslationBlock *tb) offsetof(ArchCPU, env)); if (tb_cflags(tb) & CF_USE_ICOUNT) { - imm = tcg_temp_new_i32(); - /* We emit a movi with a dummy immediate argument. Keep the insn index - * of the movi so that we later (when we know the actual insn count) - * can update the immediate argument with the actual insn count. */ - tcg_gen_movi_i32(imm, 0xdeadbeef); + /* + * We emit a sub with a dummy immediate argument. Keep the insn index + * of the sub so that we later (when we know the actual insn count) + * can update the argument with the actual insn count. + */ + tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); icount_start_insn = tcg_last_op(); - - tcg_gen_sub_i32(count, count, imm); - tcg_temp_free_i32(imm); } tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); @@ -74,9 +72,12 @@ static inline void gen_tb_start(TranslationBlock *tb) static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* Update the num_insn immediate parameter now that we know - * the actual insn count. */ - tcg_set_insn_param(icount_start_insn, 1, num_insns); + /* + * Update the num_insn immediate parameter now that we know + * the actual insn count. + */ + tcg_set_insn_param(icount_start_insn, 2, + tcgv_i32_arg(tcg_constant_i32(num_insns))); } gen_set_label(tcg_ctx->exitreq_label); From patchwork Thu Dec 17 14:52:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344946 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1298305ejs; Thu, 17 Dec 2020 07:06:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJwKstUIN6YyL6pCnFrSeh0SUVV8M9FOdbaodSS/kVtgItS01ZK3/sbMYv5pg1kjeH5BEly7 X-Received: by 2002:a25:ac25:: with SMTP id w37mr53950955ybi.522.1608217591021; Thu, 17 Dec 2020 07:06:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217591; cv=none; d=google.com; s=arc-20160816; b=bQocN8TiXJ4y0Cix5bbiDSh02kPXiPHsAjGkj8xvIaSh3k3BeNapGpxJI2rIDS2Bi7 It4odmm0cJIU8v1xZ14tO0YLg0Ezjdmarjkyy6XqEHXFZ8eX5GhI2C4UYrvOIdHEkeP5 58iIJZ124MUVvPMOKO+abgWHVelP/yR5kyrvQBGgfMK2zQ2gxMrLaPvr0zg4T7jsUUyp QUc15C7kDGF2hzUnFV223Z0x7ppcGTskZO5alIFvEpIi9GGQMfBOcjUl7+VKYUocWKKS mppLmUNM8Luv7Oq3FTBBYSl91y4NQrp++jxly40zHrF4/NRp4Vd4i/cfVs9vWt0KvPFO EMgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aEQok0/L5FX5jAQIApgNcuA+gqvYfIDMod+uDV+LrZA=; b=GAkiNdqvWTJQjeIQAMrVcZWs1TS1fnRFSbw0NGQCtLWYLWhDanEJHPoJTwvj3MxU9+ fu/ruTLD7hoXQExvg2tAgZa1m8350pIl5E0/zq8I4qHQMWh4LarWEFj7cElzvgRdn+ZI veVU9YR1zWk+6fnPwAxMa0AXMyK/KH4fDuKoeqA8c/BYRtIDwTzKKWhZwI7XNl5YD2Si j5Cuc0tksuw6F/XNxZGbdbJU3e8Lo2OsawuZXKwxxgtF5RRjwOtmNmzwOFIo3T+xSd8Z 1l8nXp3beVBtmJRlHNVayfJBEb6uaJ81TubXsQBUVrN91y5lbGxXIx80DUTT/7PtrqIA SyiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="M0/zEyDM"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/23] tcg: Use tcg_constant_{i32, i64} with tcg int expanders Date: Thu, 17 Dec 2020 08:52:06 -0600 Message-Id: <20201217145215.534637-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 13 +-- tcg/tcg-op.c | 227 ++++++++++++++++++++----------------------- 2 files changed, 109 insertions(+), 131 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5abf17fecc..b4fba35e87 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -271,6 +271,7 @@ void tcg_gen_mb(TCGBar); /* 32 bit ops */ +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -349,11 +350,6 @@ static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) } } -static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) -{ - tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); -} - static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { @@ -467,6 +463,7 @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) /* 64 bit ops */ +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); @@ -550,11 +547,6 @@ static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) } } -static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) -{ - tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); -} - static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { @@ -698,7 +690,6 @@ static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) void tcg_gen_discard_i64(TCGv_i64 arg); void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4b8a473fad..e2d8ae3234 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -104,15 +104,18 @@ void tcg_gen_mb(TCGBar mb_type) /* 32 bit ops */ +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) +{ + tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); +} + void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_add_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -122,9 +125,7 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) /* Don't recurse with tcg_gen_neg_i32. */ tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2); } else { - TCGv_i32 t0 = tcg_const_i32(arg1); - tcg_gen_sub_i32(ret, t0, arg2); - tcg_temp_free_i32(t0); + tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); } } @@ -134,15 +135,12 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_sub_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_sub_i32(ret, arg1, tcg_constant_i32(arg2)); } } void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - TCGv_i32 t0; /* Some cases can be optimized here. */ switch (arg2) { case 0: @@ -165,9 +163,8 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } break; } - t0 = tcg_const_i32(arg2); - tcg_gen_and_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + + tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -178,9 +175,7 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_or_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -193,9 +188,7 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) /* Don't recurse with tcg_gen_not_i32. */ tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_xor_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -205,9 +198,7 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_shl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -217,9 +208,7 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_shr_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -229,9 +218,7 @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_sar_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -250,9 +237,7 @@ void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_brcond_i32(cond, arg1, t0, l); - tcg_temp_free_i32(t0); + tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l); } } @@ -271,9 +256,7 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_setcond_i32(cond, ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -283,9 +266,7 @@ void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } else if (is_power_of_2(arg2)) { tcg_gen_shli_i32(ret, arg1, ctz32(arg2)); } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_mul_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -433,9 +414,7 @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { - TCGv_i32 t = tcg_const_i32(arg2); - tcg_gen_clz_i32(ret, arg1, t); - tcg_temp_free_i32(t); + tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); } void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -468,10 +447,9 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) tcg_gen_clzi_i32(t, t, 32); tcg_gen_xori_i32(t, t, 31); } - z = tcg_const_i32(0); + z = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); tcg_temp_free_i32(t); - tcg_temp_free_i32(z); } else { gen_helper_ctz_i32(ret, arg1, arg2); } @@ -487,9 +465,7 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) tcg_gen_ctpop_i32(ret, t); tcg_temp_free_i32(t); } else { - TCGv_i32 t = tcg_const_i32(arg2); - tcg_gen_ctz_i32(ret, arg1, t); - tcg_temp_free_i32(t); + tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2)); } } @@ -547,9 +523,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else if (TCG_TARGET_HAS_rot_i32) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_rotl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2)); } else { TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -653,9 +627,8 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_andi_i32(ret, arg, (1u << len) - 1); } else if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { - TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 zero = tcg_constant_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - tcg_temp_free_i32(zero); } else { /* To help two-operand hosts we prefer to zero-extend first, which allows ARG to stay live. */ @@ -1052,7 +1025,7 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_const_i32(0x00ff00ff); + TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff); /* arg = abcd */ tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ @@ -1067,7 +1040,6 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } } @@ -1114,8 +1086,15 @@ void tcg_gen_discard_i64(TCGv_i64 arg) void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); + TCGTemp *ts = tcgv_i64_temp(arg); + + /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */ + if (ts->kind == TEMP_CONST) { + tcg_gen_movi_i64(ret, ts->val); + } else { + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); + } } void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) @@ -1237,6 +1216,14 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t0); tcg_temp_free_i32(t1); } + +#else + +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) +{ + tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); +} + #endif /* TCG_TARGET_REG_SIZE == 32 */ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1244,10 +1231,12 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_add_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); } } @@ -1256,10 +1245,12 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { /* Don't recurse with tcg_gen_neg_i64. */ tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); } else { - TCGv_i64 t0 = tcg_const_i64(arg1); - tcg_gen_sub_i64(ret, t0, arg2); - tcg_temp_free_i64(t0); + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32), + TCGV_LOW(arg2), TCGV_HIGH(arg2)); } } @@ -1268,17 +1259,17 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* some cases can be optimized here */ if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); + } else if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_sub_i64(ret, arg1, tcg_constant_i64(arg2)); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_sub_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); } } void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0; - if (TCG_TARGET_REG_BITS == 32) { tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); @@ -1313,9 +1304,8 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } break; } - t0 = tcg_const_i64(arg2); - tcg_gen_and_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + + tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2)); } void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1331,9 +1321,7 @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_or_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1351,9 +1339,7 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) /* Don't recurse with tcg_gen_not_i64. */ tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_xor_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1415,9 +1401,7 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_shl_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1429,9 +1413,7 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_shr_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1443,9 +1425,7 @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } else if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_sar_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2)); } } @@ -1468,12 +1448,17 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) { - if (cond == TCG_COND_ALWAYS) { + if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); + } else if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_brcond_i64(cond, arg1, t0, l); - tcg_temp_free_i64(t0); + l->refs++; + tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), + tcg_constant_i32(arg2 >> 32), + cond, label_arg(l)); } } @@ -1499,9 +1484,19 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_setcond_i64(cond, ret, arg1, t0); - tcg_temp_free_i64(t0); + if (TCG_TARGET_REG_BITS == 64) { + tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); + } else if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i64(ret, 1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i64(ret, 0); + } else { + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + tcg_constant_i32(arg2), + tcg_constant_i32(arg2 >> 32), cond); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); + } } void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) @@ -1690,7 +1685,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) } else { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_const_i64(0x00ff00ff); + TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff); /* arg = ....abcd */ tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ @@ -1706,7 +1701,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } } @@ -1850,16 +1844,16 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_clz_i32 && arg2 <= 0xffffffffu) { - TCGv_i32 t = tcg_const_i32((uint32_t)arg2 - 32); - tcg_gen_clz_i32(t, TCGV_LOW(arg1), t); + TCGv_i32 t = tcg_temp_new_i32(); + tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32); tcg_gen_addi_i32(t, t, 32); tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); tcg_temp_free_i32(t); } else { - TCGv_i64 t = tcg_const_i64(arg2); - tcg_gen_clz_i64(ret, arg1, t); - tcg_temp_free_i64(t); + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_clz_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); } } @@ -1881,7 +1875,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_gen_clzi_i64(t, t, 64); tcg_gen_xori_i64(t, t, 63); } - z = tcg_const_i64(0); + z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t); tcg_temp_free_i64(t); tcg_temp_free_i64(z); @@ -1895,8 +1889,8 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctz_i32 && arg2 <= 0xffffffffu) { - TCGv_i32 t32 = tcg_const_i32((uint32_t)arg2 - 32); - tcg_gen_ctz_i32(t32, TCGV_HIGH(arg1), t32); + TCGv_i32 t32 = tcg_temp_new_i32(); + tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); tcg_gen_addi_i32(t32, t32, 32); tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); @@ -1911,9 +1905,9 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) tcg_gen_ctpop_i64(ret, t); tcg_temp_free_i64(t); } else { - TCGv_i64 t64 = tcg_const_i64(arg2); - tcg_gen_ctz_i64(ret, arg1, t64); - tcg_temp_free_i64(t64); + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_ctz_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); } } @@ -1969,9 +1963,7 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else if (TCG_TARGET_HAS_rot_i64) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_rotl_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2)); } else { TCGv_i64 t0, t1; t0 = tcg_temp_new_i64(); @@ -2089,9 +2081,8 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); } else if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); - tcg_temp_free_i64(zero); } else { if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { @@ -3102,9 +3093,8 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(retv, cpu_env, addr, cmpv, newv, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); } #else gen(retv, cpu_env, addr, cmpv, newv); @@ -3147,9 +3137,8 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, cpu_env, addr, cmpv, newv, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); } #else gen(retv, cpu_env, addr, cmpv, newv); @@ -3211,9 +3200,8 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, cpu_env, addr, val, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); } #else gen(ret, cpu_env, addr, val); @@ -3257,9 +3245,8 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, cpu_env, addr, val, oi); - tcg_temp_free_i32(oi); + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); } #else gen(ret, cpu_env, addr, val); From patchwork Thu Dec 17 14:52:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344957 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1271812jai; Thu, 17 Dec 2020 07:30:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJwd01OMkQlQ9pdobHPEj/If56j21dVeqJsr7O7jPmVBm0XRtrHtkXf/GzotXKQmPPmOEdgG X-Received: by 2002:a25:4b42:: with SMTP id y63mr53722372yba.10.1608219017396; Thu, 17 Dec 2020 07:30:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608219017; cv=none; d=google.com; s=arc-20160816; b=ltb51zGJEYVuk4+UfBsQuxblgBCVuNr4CO1ZuL+wfp05AV7bNtibHhrWZDHtUbffP+ V7U5Wek2dWDBlDjFfgsiN+kmWc1jUiQRD/uV8QY0n+dF5v9uOPQRy1QjLQTDUjWfYTkW 0uzgHLV4bmAuRIWaRwNI24SQ7ej/xA8HgEnQLsjNdZCMvekkPEDPiWh8bfGZWCuHCzdi n5DECR3PSHZPPrU545yD6kYgsE7TgUrHdY8qlY7z0GjqSa/f8Tx6QUspSOTlVsjCYlXg nAv64WJYYZt+hyiA8RpeSfLA2nquqZyuf7agr2CwVZm0V1O3LL4Zck2VcBDdl666Loqt nllw== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/23] tcg: Use tcg_constant_{i32,i64} with tcg plugins Date: Thu, 17 Dec 2020 08:52:07 -0600 Message-Id: <20201217145215.534637-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 49 +++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 51580d51a0..e5dc9d0ca9 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -284,8 +284,8 @@ static TCGOp *copy_extu_i32_i64(TCGOp **begin_op, TCGOp *op) if (TCG_TARGET_REG_BITS == 32) { /* mov_i32 */ op = copy_op(begin_op, op, INDEX_op_mov_i32); - /* movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); + /* mov_i32 w/ $0 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); } else { /* extu_i32_i64 */ op = copy_op(begin_op, op, INDEX_op_extu_i32_i64); @@ -306,39 +306,34 @@ static TCGOp *copy_mov_i64(TCGOp **begin_op, TCGOp *op) return op; } -static TCGOp *copy_movi_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) -{ - if (TCG_TARGET_REG_BITS == 32) { - /* 2x movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = v; - - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = v >> 32; - } else { - /* movi_i64 */ - op = copy_op(begin_op, op, INDEX_op_movi_i64); - op->args[1] = v; - } - return op; -} - static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp *op, void *ptr) { if (UINTPTR_MAX == UINT32_MAX) { - /* movi_i32 */ - op = copy_op(begin_op, op, INDEX_op_movi_i32); - op->args[1] = (uintptr_t)ptr; + /* mov_i32 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32((uintptr_t)ptr)); } else { - /* movi_i64 */ - op = copy_movi_i64(begin_op, op, (uint64_t)(uintptr_t)ptr); + /* mov_i64 */ + op = copy_op(begin_op, op, INDEX_op_mov_i64); + op->args[1] = tcgv_i64_arg(tcg_constant_i64((uintptr_t)ptr)); } return op; } static TCGOp *copy_const_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) { - return copy_movi_i64(begin_op, op, v); + if (TCG_TARGET_REG_BITS == 32) { + /* 2x mov_i32 */ + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v)); + op = copy_op(begin_op, op, INDEX_op_mov_i32); + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v >> 32)); + } else { + /* mov_i64 */ + op = copy_op(begin_op, op, INDEX_op_mov_i64); + op->args[1] = tcgv_i64_arg(tcg_constant_i64(v)); + } + return op; } static TCGOp *copy_extu_tl_i64(TCGOp **begin_op, TCGOp *op) @@ -486,8 +481,8 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb, tcg_debug_assert(type == PLUGIN_GEN_CB_MEM); - /* const_i32 == movi_i32 ("info", so it remains as is) */ - op = copy_op(&begin_op, op, INDEX_op_movi_i32); + /* const_i32 == mov_i32 ("info", so it remains as is) */ + op = copy_op(&begin_op, op, INDEX_op_mov_i32); /* const_ptr */ op = copy_const_ptr(&begin_op, op, cb->userp); From patchwork Thu Dec 17 14:52:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344949 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1303528ejs; Thu, 17 Dec 2020 07:12:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJwFZDVE4ncp25PVG+vXZrhEHvK9j7j0tHx31mJ3QljBKJ8ylGPfbnuS2vsMs7usTxf28rKr X-Received: by 2002:a25:4e0b:: with SMTP id c11mr58273945ybb.255.1608217926391; Thu, 17 Dec 2020 07:12:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217926; cv=none; d=google.com; s=arc-20160816; b=iONqFPzrZBW934SFxkzKIeBDaHxtYEfYLF3yKxctS0ig9ycVdOb1lRvvoJAtwuM2sI jPrPzqLwbiNpNm4oXkkXD41KESXfEeafARtVAaF0R7b15yUq9wDmNsnCl9MTrILeC+dl NVmG0smLsjWM7cQHGN5a06rtFW06WycmDehchs2Ibt3XB99cpzcohO7VA9H4EXlf8e/j QOc6I/y7zK/yRcbndfVDcOmxpTTpUbQjQgs3r/H0+1BwdGbiVu0NC+qlln87PRtuT0ye ZUgjEeQwnAUkYgR1GiZgZQDJBtGyiA29/dTDddoU16QJY76hnjTUJXgMilIUiFyeU1wW QRyQ== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/23] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Date: Thu, 17 Dec 2020 08:52:08 -0600 Message-Id: <20201217145215.534637-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tcg-op-gvec.c | 125 ++++++++++++++++++---------------------------- tcg/tcg.c | 8 +++ 3 files changed, 58 insertions(+), 76 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 995db20d02..5a5413f0d4 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1083,6 +1083,7 @@ static inline TCGv_i64 tcg_constant_i64(int64_t val) } TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); #if UINTPTR_MAX == UINT32_MAX # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index ddbe06b71a..80eb53c770 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -115,7 +115,7 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, gen_helper_gvec_2 *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -127,7 +127,6 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with two vector operands @@ -137,7 +136,7 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, gen_helper_gvec_2i *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -149,7 +148,6 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands. */ @@ -158,7 +156,7 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_3 *fn) { TCGv_ptr a0, a1, a2; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -173,7 +171,6 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with four vector operands. */ @@ -182,7 +179,7 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, int32_t data, gen_helper_gvec_4 *fn) { TCGv_ptr a0, a1, a2, a3; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -200,7 +197,6 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with five vector operands. */ @@ -209,7 +205,7 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn) { TCGv_ptr a0, a1, a2, a3, a4; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -230,7 +226,6 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); tcg_temp_free_ptr(a4); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands @@ -240,7 +235,7 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, int32_t data, gen_helper_gvec_2_ptr *fn) { TCGv_ptr a0, a1; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -252,7 +247,6 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with three vector operands @@ -262,7 +256,7 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, int32_t data, gen_helper_gvec_3_ptr *fn) { TCGv_ptr a0, a1, a2; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -277,7 +271,6 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a0); tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with four vector operands @@ -288,7 +281,7 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_4_ptr *fn) { TCGv_ptr a0, a1, a2, a3; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -306,7 +299,6 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a1); tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); - tcg_temp_free_i32(desc); } /* Generate a call to a gvec-style helper with five vector operands @@ -317,7 +309,7 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, gen_helper_gvec_5_ptr *fn) { TCGv_ptr a0, a1, a2, a3, a4; - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); a0 = tcg_temp_new_ptr(); a1 = tcg_temp_new_ptr(); @@ -338,7 +330,6 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_temp_free_ptr(a2); tcg_temp_free_ptr(a3); tcg_temp_free_ptr(a4); - tcg_temp_free_i32(desc); } /* Return true if we want to implement something of OPRSZ bytes @@ -602,9 +593,9 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, || (TCG_TARGET_REG_BITS == 64 && (in_c == 0 || in_c == -1 || !check_size_impl(oprsz, 4)))) { - t_64 = tcg_const_i64(in_c); + t_64 = tcg_constant_i64(in_c); } else { - t_32 = tcg_const_i32(in_c); + t_32 = tcg_constant_i32(in_c); } } @@ -628,15 +619,14 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, /* Otherwise implement out of line. */ t_ptr = tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); - t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0)); + t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0)); if (vece == MO_64) { if (in_64) { gen_helper_gvec_dup64(t_ptr, t_desc, in_64); } else { - t_64 = tcg_const_i64(in_c); + t_64 = tcg_constant_i64(in_c); gen_helper_gvec_dup64(t_ptr, t_desc, t_64); - tcg_temp_free_i64(t_64); } } else { typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32); @@ -648,24 +638,23 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, if (in_32) { fns[vece](t_ptr, t_desc, in_32); - } else { + } else if (in_64) { t_32 = tcg_temp_new_i32(); - if (in_64) { - tcg_gen_extrl_i64_i32(t_32, in_64); - } else if (vece == MO_8) { - tcg_gen_movi_i32(t_32, in_c & 0xff); - } else if (vece == MO_16) { - tcg_gen_movi_i32(t_32, in_c & 0xffff); - } else { - tcg_gen_movi_i32(t_32, in_c); - } + tcg_gen_extrl_i64_i32(t_32, in_64); fns[vece](t_ptr, t_desc, t_32); tcg_temp_free_i32(t_32); + } else { + if (vece == MO_8) { + in_c &= 0xff; + } else if (vece == MO_16) { + in_c &= 0xffff; + } + t_32 = tcg_constant_i32(in_c); + fns[vece](t_ptr, t_desc, t_32); } } tcg_temp_free_ptr(t_ptr); - tcg_temp_free_i32(t_desc); return; done: @@ -1215,10 +1204,9 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, if (g->fno) { tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); } else { - TCGv_i64 tcg_c = tcg_const_i64(c); + TCGv_i64 tcg_c = tcg_constant_i64(c); tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, maxsz, c, g->fnoi); - tcg_temp_free_i64(tcg_c); } oprsz = maxsz; } @@ -1712,16 +1700,14 @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_addv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_addv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1805,9 +1791,8 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(c); + TCGv_i64 tmp = tcg_constant_i64(c); tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); } static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 }; @@ -1865,16 +1850,14 @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_subv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_subv_mask(d, a, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1985,9 +1968,8 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(c); + TCGv_i64 tmp = tcg_constant_i64(c); tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); } void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2044,18 +2026,16 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { - TCGv_i32 max = tcg_const_i32(-1); + TCGv_i32 max = tcg_constant_i32(-1); tcg_gen_add_i32(d, a, b); tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); - tcg_temp_free_i32(max); } static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 max = tcg_const_i64(-1); + TCGv_i64 max = tcg_constant_i64(-1); tcg_gen_add_i64(d, a, b); tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); - tcg_temp_free_i64(max); } void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2088,18 +2068,16 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { - TCGv_i32 min = tcg_const_i32(0); + TCGv_i32 min = tcg_constant_i32(0); tcg_gen_sub_i32(d, a, b); tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); - tcg_temp_free_i32(min); } static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - TCGv_i64 min = tcg_const_i64(0); + TCGv_i64 min = tcg_constant_i64(0); tcg_gen_sub_i64(d, a, b); tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); - tcg_temp_free_i64(min); } void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2260,16 +2238,14 @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); gen_negv_mask(d, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b) { - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); gen_negv_mask(d, b, m); - tcg_temp_free_i64(m); } void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) @@ -2538,9 +2514,8 @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); - tcg_temp_free_i64(tmp); } static const GVecGen2s gop_xors = { @@ -2563,9 +2538,8 @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); - tcg_temp_free_i64(tmp); } static const GVecGen2s gop_ors = { @@ -2588,9 +2562,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) { - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); - tcg_temp_free_i64(tmp); } void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) @@ -3078,9 +3051,9 @@ static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_shlv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3141,9 +3114,9 @@ static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_shrv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3204,9 +3177,9 @@ static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_sarv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3267,9 +3240,9 @@ static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_rotlv_vec(vece, d, a, t); tcg_temp_free_vec(t); } @@ -3326,9 +3299,9 @@ static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) { TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); - tcg_gen_and_vec(vece, t, t, b); + tcg_gen_and_vec(vece, t, b, m); tcg_gen_rotrv_vec(vece, d, a, t); tcg_temp_free_vec(t); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 500663e3f5..231d1950ed 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1424,6 +1424,14 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) return temp_tcgv_vec(tcg_constant_internal(type, val)); } +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) +{ + TCGTemp *t = tcgv_vec_temp(match); + + tcg_debug_assert(t->temp_allocated != 0); + return tcg_constant_vec(t->base_type, vece, val); +} + TCGv_i32 tcg_const_i32(int32_t val) { TCGv_i32 t0; From patchwork Thu Dec 17 14:52:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344939 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1289942ejs; Thu, 17 Dec 2020 06:57:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJxXZDfMgqqn6K7oFPr52QopsXjdGY4yWQ73HSK/ehY0O5fbOTcEtezHQL0rxjksrYJvasms X-Received: by 2002:a5b:2cf:: with SMTP id h15mr58544616ybp.475.1608217049911; Thu, 17 Dec 2020 06:57:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217049; cv=none; d=google.com; s=arc-20160816; b=yva+laMfB/6H6hNaop0f0hD2bHbGDt9VLsqICO3rqQdk06DeC/JaNCjX/pGk4rAIwL ljns9UBVVKOtHJ2Q8BSMU7Aiz/h86tNyB7vSOS465lSpXCkEQI4/21i6k4nmKYb215Ti WmPu4NvdoG6cDzCgbT9VqN0AxXZg63XyQYvEAZjeyIxvK2/7yX4UxUgiVXDFfUYS6jFk sk/CMxycwe0mPMn2zQSL0tJAJZ8BXEYx/GI+Tlrw0CoTyz5ojbSNyTvRzoxC6DqYbk14 93q6y5q23pAnyWhCQDjSh2BR5/ZiTQL7LzmWjw2s3KBJsLQAbMyT+nJ1an9Q1slOV7JY gIPA== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/23] tcg/tci: Add special tci_movi_{i32,i64} opcodes Date: Thu, 17 Dec 2020 08:52:09 -0600 Message-Id: <20201217145215.534637-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 8 ++++++++ tcg/tci.c | 4 ++-- tcg/tci/tcg-target.c.inc | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 67092e82c6..314455b386 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -273,6 +273,14 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #include "tcg-target.opc.h" #endif +#ifdef TCG_TARGET_INTERPRETER +/* These opcodes are only for use between the tci generator and interpreter. */ +DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) +#if TCG_TARGET_REG_BITS == 64 +DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +#endif +#endif + #undef TLADDR_ARGS #undef DATA64_ARGS #undef IMPL diff --git a/tcg/tci.c b/tcg/tci.c index 82039fd163..52b34bd70f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -576,7 +576,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t1 = tci_read_r32(regs, &tb_ptr); tci_write_reg32(regs, t0, t1); break; - case INDEX_op_movi_i32: + case INDEX_op_tci_movi_i32: t0 = *tb_ptr++; t1 = tci_read_i32(&tb_ptr); tci_write_reg32(regs, t0, t1); @@ -847,7 +847,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t1 = tci_read_r64(regs, &tb_ptr); tci_write_reg64(regs, t0, t1); break; - case INDEX_op_movi_i64: + case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); tci_write_reg64(regs, t0, t1); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..c8c8386a72 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -529,13 +529,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, uint8_t *old_code_ptr = s->code_ptr; uint32_t arg32 = arg; if (type == TCG_TYPE_I32 || arg == arg32) { - tcg_out_op_t(s, INDEX_op_movi_i32); + tcg_out_op_t(s, INDEX_op_tci_movi_i32); tcg_out_r(s, t0); tcg_out32(s, arg32); } else { tcg_debug_assert(type == TCG_TYPE_I64); #if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_movi_i64); + tcg_out_op_t(s, INDEX_op_tci_movi_i64); tcg_out_r(s, t0); tcg_out64(s, arg); #else From patchwork Thu Dec 17 14:52:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344941 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1291444ejs; Thu, 17 Dec 2020 06:59:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJzST0X4PJ6O5E1UJy49uzqx5OcRGJf/kPYiikffKcI+3PqrMT9L4sfL2HpJVsGYTCAbdzsK X-Received: by 2002:a25:9c83:: with SMTP id y3mr1570463ybo.307.1608217174449; Thu, 17 Dec 2020 06:59:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217174; cv=none; d=google.com; s=arc-20160816; b=QWFH7loM1iEWxAzVtliAurscif6o0SdaT6o6W4WDK2XKLwI/mSVwYytHnHJF3QezW5 6LjVIjb5RBXukPVVIbutylnFe7FPJfuZoUNA+YyphLDpq+bLssLfUBo4FANcmfiUGnM1 kOcM6VJl9kSUvaPIKh6mDF8d797JLqg+YLpG+SKU9Hblql+BeIzbkh3t+qWXVYmVe5pl FHwaph1ULxefwcRtso7S9E+uME+cGbzKJu9Mr8qAfTgFjt/EQmi19chH91qMd9cpID98 FQ9tdOyp/H7thOGfoFn/gfpPCOtjcGTduJ5ow9scnruRfobqwDyhQm0GsvAYSfWO3L8F 9V9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T6zl2uASh6CoYxMghgzJy0NJ+a9C4k9ZiM/l/5q4INQ=; b=J51rnPIG4OlT2dEFBdBFCJxhfsmmvd4bHBbEM6qnfXinm0Twpn1syezmBZA9zK9zxR UEvpILgeE/lzcOvT7pvPEKcsjPs4kiU/gpdaPrq75Wwtv5MWgqUy5+P0tkLwDT5g8xf3 b/e+kt+FiKshlpeipP/K3f8wPCtDptrXBnZuZJLCqYslef3vbKO6TQwRrqByedaNU5dn IL+0FRf+vhxIzLA4GOLhcKWzbWqy/x/Q5Do/Ea96E92r1MdFV2kcV3OiCYcJyfwy613Q mFgJatheBO/28b46SSE0zrN7X/4kpETtXVOFIGkvN/jjVN7nY7WLpA1AaT5sNUHldubn UKwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="se/fnTbu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 18/23] tcg: Remove movi and dupi opcodes Date: Thu, 17 Dec 2020 08:52:10 -0600 Message-Id: <20201217145215.534637-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Markovic , =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée Reviewed-by: Aleksandar Markovic Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 --- tcg/optimize.c | 4 ---- tcg/tcg-op-vec.c | 1 - tcg/tcg.c | 18 +----------------- tcg/aarch64/tcg-target.c.inc | 3 --- tcg/arm/tcg-target.c.inc | 1 - tcg/i386/tcg-target.c.inc | 3 --- tcg/mips/tcg-target.c.inc | 2 -- tcg/ppc/tcg-target.c.inc | 3 --- tcg/riscv/tcg-target.c.inc | 2 -- tcg/s390/tcg-target.c.inc | 2 -- tcg/sparc/tcg-target.c.inc | 2 -- tcg/tci/tcg-target.c.inc | 2 -- 13 files changed, 1 insertion(+), 45 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 314455b386..2e5860a057 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -45,7 +45,6 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) -DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) /* load/store */ @@ -111,7 +110,6 @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) -DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) /* load/store */ @@ -216,7 +214,6 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) -DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) diff --git a/tcg/optimize.c b/tcg/optimize.c index af07c6f628..1a94e9a41b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1099,10 +1099,6 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(mov): tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); break; - CASE_OP_32_64(movi): - case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); - break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 9fbed1366c..ce0d2f6e0e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -83,7 +83,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_xor_vec: case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: diff --git a/tcg/tcg.c b/tcg/tcg.c index 231d1950ed..8def2f99e6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1511,7 +1511,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_goto_ptr; case INDEX_op_mov_i32: - case INDEX_op_movi_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: case INDEX_op_ld8u_i32: @@ -1605,7 +1604,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_REG_BITS == 32; case INDEX_op_mov_i64: - case INDEX_op_movi_i64: case INDEX_op_setcond_i64: case INDEX_op_brcond_i64: case INDEX_op_ld8u_i64: @@ -1711,7 +1709,6 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dupm_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: @@ -3616,7 +3613,7 @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) } /* - * Specialized code generation for INDEX_op_movi_*. + * Specialized code generation for INDEX_op_mov_* with a constant. */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_life, @@ -3639,14 +3636,6 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, } } -static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) -{ - TCGTemp *ots = arg_temp(op->args[0]); - tcg_target_ulong val = op->args[1]; - - tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); -} - /* * Specialized code generation for INDEX_op_mov_*. */ @@ -4422,11 +4411,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; - case INDEX_op_movi_i32: - case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: - tcg_reg_alloc_movi(s, op); - break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 56056be74b..a6c2d54c4d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2252,8 +2252,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); @@ -2461,7 +2459,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..30d30874c7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2065,7 +2065,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6b7cbaa47a..819ee25cff 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2692,8 +2692,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -2979,7 +2977,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..39e7bc3f8d 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2152,8 +2152,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 2428faeabd..163a5bb32c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2973,8 +2973,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -3322,7 +3320,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, return; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..aaef1c5eed 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1602,8 +1602,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..824a07aa7a 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2306,8 +2306,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..79e1a96aac 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1586,8 +1586,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c8c8386a72..25ed868505 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -814,8 +814,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 19/23] tcg: Add tcg_reg_alloc_dup2 Date: Thu, 17 Dec 2020 08:52:11 -0600 Message-Id: <20201217145215.534637-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 8def2f99e6..09a82d444f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4030,6 +4030,98 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } } +static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life = op->life; + TCGTemp *ots, *itsl, *itsh; + TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; + + /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_debug_assert(TCGOP_VECE(op) == MO_64); + + ots = arg_temp(op->args[0]); + itsl = arg_temp(op->args[1]); + itsh = arg_temp(op->args[2]); + + /* ENV should not be modified. */ + tcg_debug_assert(!temp_readonly(ots)); + + /* Allocate the output register now. */ + if (ots->val_type != TEMP_VAL_REG) { + TCGRegSet allocated_regs = s->reserved_regs; + TCGRegSet dup_out_regs = + tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + + /* Make sure to not spill the input registers. */ + if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsl->reg); + } + if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsh->reg); + } + + ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type = TEMP_VAL_REG; + ots->mem_coherent = 0; + s->reg_to_temp[ots->reg] = ots; + } + + /* Promote dup2 of immediates to dupi_vec. */ + if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { + uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); + MemOp vece = MO_64; + + if (val == dup_const(MO_8, val)) { + vece = MO_8; + } else if (val == dup_const(MO_16, val)) { + vece = MO_16; + } else if (val == dup_const(MO_32, val)) { + vece = MO_32; + } + + tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); + goto done; + } + + /* If the two inputs form one 64-bit value, try dupm_vec. */ + if (itsl + 1 == itsh && itsl->base_type == TCG_TYPE_I64) { + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } + if (!itsh->mem_coherent) { + temp_sync(s, itsh, s->reserved_regs, 0, 0); + } +#ifdef HOST_WORDS_BIGENDIAN + TCGTemp *its = itsh; +#else + TCGTemp *its = itsl; +#endif + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, + its->mem_base->reg, its->mem_offset)) { + goto done; + } + } + + /* Fall back to generic expansion. */ + return false; + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, itsl); + } + if (IS_DEAD_ARG(2)) { + temp_dead(s, itsh); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); + } else if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } + return true; +} + #ifdef TCG_TARGET_STACK_GROWSUP #define STACK_DIR(x) (-(x)) #else @@ -4442,6 +4534,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_call: tcg_reg_alloc_call(s, op); break; + case INDEX_op_dup2_vec: + if (tcg_reg_alloc_dup2(s, op)) { + break; + } + /* fall through */ default: /* Sanity check that we've not introduced any unhandled opcodes. */ tcg_debug_assert(tcg_op_supported(opc)); From patchwork Thu Dec 17 14:52:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344952 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1306998ejs; Thu, 17 Dec 2020 07:16:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJwKcI/ps58hql/ijfG3folw3TbiENquX/kgvv4oBzKfowEMO9awJwev0qnq5gaghYZyShrm X-Received: by 2002:a25:34cf:: with SMTP id b198mr58149525yba.283.1608218166901; Thu, 17 Dec 2020 07:16:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608218166; cv=none; d=google.com; s=arc-20160816; b=U14OmvZiwyeNows3woMVHThUeznJbUnPjRA6fLxX1+WKV6zXzDgA7r5DmHKxlIqAHV WgZUmyrtSp/aw5aQyvcS/cE8lLjBWbEgSkZwEUbJ5CNunlXpV6bqNfVMXfx31oCfvbsP hE+BiTrJfDBcA/4eA/5m8KePt2HQLYhFJqJErF9cSf9qHfHDfmycuuhmGVs6qbptAeEt Af2TN0iPfARbg+7RMfEzMfn0jeeBbA60OlL9HktkKlaQjvZPerG5aLAHU58d4nyLogC6 NddvFDjOQoba69hN2P3Jx2pZnOwQJNkzcfAur6eUXOPS6dbZ0aCsWwA69bolq6E59TUW DCUA== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 20/23] tcg/i386: Use tcg_constant_vec with tcg vec expanders Date: Thu, 17 Dec 2020 08:52:12 -0600 Message-Id: <20201217145215.534637-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 819ee25cff..36a90e7ef3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3508,7 +3508,7 @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { - TCGv_vec t1, t2, t3, t4; + TCGv_vec t1, t2, t3, t4, zero; tcg_debug_assert(vece == MO_8); @@ -3526,11 +3526,11 @@ static void expand_vec_mul(TCGType type, unsigned vece, case TCG_TYPE_V64: t1 = tcg_temp_new_vec(TCG_TYPE_V128); t2 = tcg_temp_new_vec(TCG_TYPE_V128); - tcg_gen_dup16i_vec(t2, 0); + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); tcg_gen_mul_vec(MO_16, t1, t1, t2); tcg_gen_shri_vec(MO_16, t1, t1, 8); vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, @@ -3545,15 +3545,15 @@ static void expand_vec_mul(TCGType type, unsigned vece, t2 = tcg_temp_new_vec(type); t3 = tcg_temp_new_vec(type); t4 = tcg_temp_new_vec(type); - tcg_gen_dup16i_vec(t4, 0); + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); tcg_gen_mul_vec(MO_16, t1, t1, t2); tcg_gen_mul_vec(MO_16, t3, t3, t4); tcg_gen_shri_vec(MO_16, t1, t1, 8); @@ -3581,7 +3581,7 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, NEED_UMIN = 8, NEED_UMAX = 16, }; - TCGv_vec t1, t2; + TCGv_vec t1, t2, t3; uint8_t fixup; switch (cond) { @@ -3652,9 +3652,9 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, } else if (fixup & NEED_BIAS) { t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); - tcg_gen_sub_vec(vece, t1, v1, t2); - tcg_gen_sub_vec(vece, t2, v2, t2); + t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); + tcg_gen_sub_vec(vece, t1, v1, t3); + tcg_gen_sub_vec(vece, t2, v2, t3); v1 = t1; v2 = t2; cond = tcg_signed_cond(cond); From patchwork Thu Dec 17 14:52:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344944 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1296054ejs; Thu, 17 Dec 2020 07:04:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJwL+goNvkDzNS3fuGmx03S2/tx3icU8P8M0SAlzYc6Jm2IYmPT7cDujv3p4rfW68t723tzq X-Received: by 2002:a5b:3c8:: with SMTP id t8mr9640937ybp.19.1608217449975; Thu, 17 Dec 2020 07:04:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608217449; cv=none; d=google.com; s=arc-20160816; b=N22XOpE070KzimOK+ZquO1p2khVo3s8o0o0Xc7QIlN7g73XBjT9nUOGQYaEUp2DH5S p02FVheRPj+5XR2xftoyZwq/0yIY3D052txRalPMCY70HuraLzdj7c/LRsKfl30mFEfm If2c1EVpgjICFPaaj78m7AWGpNUXBzgmKkhJAsmAwLEJGmvHLY1mAZKmyc4RgWOhBpVJ mFDOB6Geix4ucW0nRdFHcY2KZKRQKcNq6sv2gF1Fdu221dwz8GMwplnbEP9gY0NURoi6 BrQM9q8qAEXU/dTHJKmmQo3Hej4Rjbnc68sU4CBR7/smuZkx4oRfG5YCw3kamfXYg4OW d0LA== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 21/23] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Date: Thu, 17 Dec 2020 08:52:13 -0600 Message-Id: <20201217145215.534637-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ---- tcg/tcg-op-vec.c | 20 -------------------- 2 files changed, 24 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index b4fba35e87..d0319692ec 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -959,10 +959,6 @@ void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); -void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); -void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index ce0d2f6e0e..d19aa7373e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -241,26 +241,6 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) return tcg_const_ones_vec(t->base_type); } -void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) -{ - tcg_gen_dupi_vec(MO_64, r, a); -} - -void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_32, r, a); -} - -void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_16, r, a); -} - -void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) -{ - tcg_gen_dupi_vec(MO_8, r, a); -} - void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) { TCGTemp *rt = tcgv_vec_temp(r); From patchwork Thu Dec 17 14:52:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344958 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1273490jai; Thu, 17 Dec 2020 07:32:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJyqaTuWW19shJWxVb3gdlkqR177UrAfvwbkhqkQqRPKxL9vBRf104xVdwCLdQO7vg/Yetp3 X-Received: by 2002:a25:3587:: with SMTP id c129mr25264779yba.223.1608219136577; Thu, 17 Dec 2020 07:32:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608219136; cv=none; d=google.com; s=arc-20160816; b=z2GdwDnUJyd0TPIbuygALjp4Rps9wUEr1ZzCQIztWbfizOAiwXb/Tz6dU60Bf9jzal WPI8zKY3xWLlt8JkpFiT3mP6nO0Imcse+Mtj0EgiObwJP+SiZrdCHnon1iQ5BKVi+gGm 3sbRjDz31DXO4w6Rhr4E827mdyXA+M8bv7pEKo5whOw/MNd29/wmP0zZDWuJcXhnYEN6 jRxdbIareu6mcN+SnrzmgTWccGp2AnLuUzVdBEIfDIQK7kEn8lfGM+XmeOZNDQfpmat0 smv993LqUxyasE4oLXA8XcJvy+L38WwWpov7jka+v+nUGa0hIx1LZeY7Y3r+P56xhbri tdzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WiJrIjKcAYzAf+icIPzlY9kRfNkMth80Cycr47tfyJ4=; b=yaop9K+Z3x6rEqfD8s14ie0Mhy8UhcogrjZkxQtY2u6CsM4LrxytmnET70TBoUJqo+ PJXk1UEMHoSdDcUcG6yx9G3gen/zbU/spq3/Hq7Ppm3ldRGC9JhSLhtwk+ANHAQbi8pE RhK7lEwFqYn1PqfjxkGNP3GSt4qLwiB8F02dIyToGDwOAqp3mo27bQUmvbQSIkydiqQi sdRjyq7VxZ/Hk09ABv/0yDXg2yqfQq58Zgk4AkntbO+Gh8EW0qTufsPRHSxDcmJQT9Ms lNAHguWbQRHlcN53iTIf6KjtvYudLT7LUbvC+tkRETdrGqKA2yXTT2gh8oZxlSwUyWiA YF5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oBJGHur6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/23] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Date: Thu, 17 Dec 2020 08:52:14 -0600 Message-Id: <20201217145215.534637-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Improve expand_vec_shi to use sign-extraction for MO_32. This allows a single VSPLTISB instruction to load all of the valid shift constants. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 44 ++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 163a5bb32c..8778f729de 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3332,13 +3332,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGArg imm, TCGOpcode opci) { - TCGv_vec t1 = tcg_temp_new_vec(type); + TCGv_vec t1; - /* Splat w/bytes for xxspltib. */ - tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + if (vece == MO_32) { + /* + * Only 5 bits are significant, and VSPLTISB can represent -16..15. + * So using negative numbers gets us the 4th bit easily. + */ + imm = sextract32(imm, 0, 5); + } else { + imm &= (8 << vece) - 1; + } + + /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ + t1 = tcg_constant_vec(type, MO_8, imm); vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); } static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, @@ -3396,7 +3405,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, { TCGv_vec t1 = tcg_temp_new_vec(type); TCGv_vec t2 = tcg_temp_new_vec(type); - TCGv_vec t3, t4; + TCGv_vec c0, c16; switch (vece) { case MO_8: @@ -3415,21 +3424,22 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, case MO_32: tcg_debug_assert(!have_isa_2_07); - t3 = tcg_temp_new_vec(type); - t4 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(MO_8, t4, -16); + /* + * Only 5 bits are significant, and VSPLTISB can represent -16..15. + * So using -16 is a quick way to represent 16. + */ + c16 = tcg_constant_vec(type, MO_8, -16); + c0 = tcg_constant_vec(type, MO_8, 0); + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), - tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + tcgv_vec_arg(v2), tcgv_vec_arg(c16)); vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - tcg_gen_dupi_vec(MO_8, t3, 0); - vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), - tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); - vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), - tcgv_vec_arg(t3), tcgv_vec_arg(t4)); - tcg_gen_add_vec(MO_32, v0, t2, t3); - tcg_temp_free_vec(t3); - tcg_temp_free_vec(t4); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(c16)); + tcg_gen_add_vec(MO_32, v0, t1, t2); break; default: From patchwork Thu Dec 17 14:52:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 344953 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp1310072ejs; Thu, 17 Dec 2020 07:19:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJzocQSEcQ1Kcdr94B0FRCUyUwPvskuhq1Qje6CcZmArVHONvRLpjsOQQtc9p9DPI7X67afQ X-Received: by 2002:a25:be87:: with SMTP id i7mr56807406ybk.332.1608218365581; Thu, 17 Dec 2020 07:19:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608218365; cv=none; d=google.com; s=arc-20160816; b=SVhr3306lXR4Fw0dbp1Stp1cd+JgoD9VwaLycg1Y+/yBH/E/3MEWqCOyl5WzR+EzXb ye+GR8kKa3g9zqd1g0eY961iCBKxOoDtR0bVwxDyQCUR7LO0pk/zQxKNXG9YSEysud7L 4ElH9ljcIyXwTloPRaj9eytbiIv7N3Vd8VZ993HeusXyh5x+9Rar/z66oyTrUTcKhCLb +57ojRQ5U4MaWvElrYvVCrxid/yHutDerTLPDGdKQp1GJXPdRVgT8DPR4lIUoQJH5y7G QhyVSGaSbQwV06EwJM/BKQn0Ab+Snlv7BJQ3KCwFkIS8hPQCfpkHFoJk7/fNa9CQq42G Ar6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lzQwpKw8YyVUpw0ONL4kM5TrE9yjiczje0Eh4uLUkAs=; b=XGiBfEaOkpOyLpS2jx/ezyXgvCVKwMiTzUWCfBw1DeN08w3Bfe7Y/R3z76H32ed/k+ 0Hh/bFp+yJ1XcS952uYwg708BRr5iQmLzGPMxegXwb6z8vOhGXWHgNmg8Z7bH1B3OX5f p+08aX7MfV5ylvl5F7QBbmZkIM9ZXQMu9iIczDCi6PcsGiosnv5BpIZEf0wvo2GKoaLZ a3WUwgRr00LAN9+49S152jNWu/3AoMHYUqIkqAFgeQxyMDmS2axUaEWKFOfMWI2czDvF uLbZjfhgfbjTkuF/MB0PHkc5khl3AbtUqKwIT/8FDaOgi/s5jXVQlNrdSuIhbVCQR+Xw Z3ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ocVaL31o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id x130sm1136342oif.3.2020.12.17.06.52.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Dec 2020 06:52:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 23/23] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders Date: Thu, 17 Dec 2020 08:52:15 -0600 Message-Id: <20201217145215.534637-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201217145215.534637-1-richard.henderson@linaro.org> References: <20201217145215.534637-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index a6c2d54c4d..c78e809de8 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2511,7 +2511,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t1, t2; + TCGv_vec v0, v1, v2, t1, t2, c1; TCGArg a2; va_start(va, a0); @@ -2543,8 +2543,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotlv_vec: t1 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t1, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, t1); + c1 = tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, c1); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1)); @@ -2557,9 +2557,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, case INDEX_op_rotrv_vec: t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); + c1 = tcg_constant_vec(type, vece, 8 << vece); tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_dupi_vec(vece, t2, 8 << vece); - tcg_gen_add_vec(vece, t2, t1, t2); + tcg_gen_sub_vec(vece, t2, c1, v2); /* Right shifts are negative left shifts for AArch64. */ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t1));