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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id k4-v6si386626pls.182.2018.02.08.11.30.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:30:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HlpvUuhF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CAA5B222DE155; Thu, 8 Feb 2018 11:24:41 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 18718222DE133 for ; Thu, 8 Feb 2018 11:24:39 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id v71so12088688wmv.2 for ; Thu, 08 Feb 2018 11:30:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=/zhUUGqqH8vCOKLcRHFN+YFR2mB0A4O7SUVzUbesihA=; b=HlpvUuhFzcUmmDlGHynRmu5MHi3gSHNDfqrAXPxUso5RWw4uRW6x7N+l2rtWu01SMq uo8ADsOOpX5n5CjHIELmXhWvORrIfb6YttwcUtJzmJ532zYXREpq0cSlpbxVWOw2twc9 toK5KL+/O8GeubhCQ4RpPZvFAlN0o3+JIds0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/zhUUGqqH8vCOKLcRHFN+YFR2mB0A4O7SUVzUbesihA=; b=c3JbgRl7t9YkYD4aoea1z1nNZfgukw/cVFqYao0qBmuEOHoKo76WCfyjc68KL7Ul/D jUrefesYDw2hprRUe7c4ePw7wRUrqXT6VFZWsM9as8VaFVtW/0hPZlAln4/TZEfc9NX/ GwuNBt1kdVQYhUkCVliKXzFCr4NgAON46E6NqE/A5ZQM2Otn3WGFw0Srnicc1ccQAJTS 8LNFm4Fiooii9d3z0rymgRXuehAj7/U22KU9E4wW5TxbfZHxJ+lQUbSxhMY4QrEaJK0o 8woou5dAi1+XyBYFsuH6j1bwmVwA0+wj/6p4w98Po8NQem+Xsci1kj7jbfp09agoGezq n39A== X-Gm-Message-State: APf1xPAhjeBOfEI991JrEjWBliUgK9z2BJcK0gf0jkZRxKskZ/Uy6SS7 ov5/si7ICUexJrnxDq8wHInle0NHcI0= X-Received: by 10.28.46.88 with SMTP id u85mr116506wmu.12.1518118223405; Thu, 08 Feb 2018 11:30:23 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc92316-cmbg19-2-0-cust118.5-4.cable.virginm.net. [82.12.0.119]) by smtp.gmail.com with ESMTPSA id s9sm805758wra.4.2018.02.08.11.30.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:30:22 -0800 (PST) From: Leif Lindholm To: edk2-devel@lists.01.org Date: Thu, 8 Feb 2018 19:30:19 +0000 Message-Id: <20180208193021.24524-1-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms 1/3] Platform/(AMD|LeMaker|SoftIron), Silicon/AMD: drop unused PcdCacheEnabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ard.biesheuvel@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PcdCacheEnabled was never useful for these platforms, but they copied it over from other platforms used as templates. Delete it here to keep the platforms building once the Pcd is removed from EmbeddedPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 3 --- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 3 --- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 3 --- Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf | 3 --- Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf | 3 --- Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c | 6 +----- 6 files changed, 1 insertion(+), 20 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Ard Biesheuvel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 21edcc8798..48018abc69 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -282,9 +282,6 @@ [BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,Buil ################################################################################ [PcdsFeatureFlag.common] - # All pages are cached by default - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE - # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index cf3df86514..2468583c0d 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -270,9 +270,6 @@ [BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,Buil ################################################################################ [PcdsFeatureFlag.common] - # All pages are cached by default - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE - # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 0abec8120a..f0a7e97941 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -272,9 +272,6 @@ [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] ################################################################################ [PcdsFeatureFlag.common] - # All pages are cached by default - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE - # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf index 6b7481ec6d..3a38f294eb 100644 --- a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf @@ -53,9 +53,6 @@ [Guids] [Ppis] gArmMpCoreInfoPpiGuid -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf index b313d4baad..b24ffd469a 100644 --- a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf @@ -49,9 +49,6 @@ [Sources.AARCH64] [Guids] gAmdStyxMpCoreInfoGuid ## CONSUMER -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c index 3b82132d08..479a40627d 100644 --- a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c @@ -78,11 +78,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = DDR_ATTRIBUTES_CACHED; DEBUG ((EFI_D_ERROR, " Memory Map\n------------------------------------------------------------------------\n")); DEBUG ((EFI_D_ERROR, "Description : START - END [ SIZE ] { ATTR }\n")); From patchwork Thu Feb 8 19:30:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leif Lindholm X-Patchwork-Id: 127742 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1798136ljc; Thu, 8 Feb 2018 11:30:29 -0800 (PST) X-Google-Smtp-Source: AH8x227huqsGXeWivrAATcqgzy+xNiSpQF44q7hR2zrw2GEeQtxXs9ZkhN5z2s97w+vG2e50mZds X-Received: by 10.98.66.86 with SMTP id p83mr116605pfa.229.1518118229229; Thu, 08 Feb 2018 11:30:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518118229; cv=none; d=google.com; s=arc-20160816; b=RcnqFNochdi6Hce8pM5yAnZDZF9PLbWus2YuZoq2KAsXhVKc7t1MWC0Nij6QWvWrZ8 eCU2DCNffq+PN5McxTveAE+1mhtsMH+ZrzeIOrFUkbUETYvx6RTnpYB5LQjvSGoKnmDK 4DK6XW5qTozRu5I52sn6hAqKbiz0//amMBnCXUHM1qIkw1KdyS05RK5DImvRJKmr7np7 Yk4qv0bzP+JmwnNmhUwzw6FxM4ahJTdwxNqz1951vBYxCZ7nAyU1U1lclbi5IjYlSAZM MQeDwtcCib9G6dkqYlKkx58l9YYU/JYnJuo8zJLiXl4bEM5ZE0J4bq3zsZx00W/+4Fa3 Xj9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=SBdhIyOofd2Q3Kuc4T0gilPbzIoRQFAN+2hfVvysTXY=; b=mwcjPeV7AvLlM0/MmnLxaUiAnsvA8R/VVgVZOyeLC7ZHh7WrVltA5KM0YXkbZS7vu/ Oj8ILRDldYAEday3PpvW2PqOQtG+BbD4BgilcezfCrSSrVh6zys40mGHUWc0FP+SiZBg DpDKgZ9cUQcmjjQZAsVY0kgpZARB8c66aUQKrBX5swn6D06sh0MKSSZZsm57WvVyafEy Fcup+fM6E7Z9IzcmJUJEtHZnHIwCpBjQWXo9/JIoTiixFBI0xEndjcz95+8LC8/909Qj kmjQuVuKtwDV+HvihhlWuKD412hSdh2mfRcPnKJ9jq/VOQEOzO05nrP9ixwCzVKDIUIY /gIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MVpyg10B; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[82.12.0.119]) by smtp.gmail.com with ESMTPSA id s9sm805758wra.4.2018.02.08.11.30.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:30:23 -0800 (PST) From: Leif Lindholm To: edk2-devel@lists.01.org Date: Thu, 8 Feb 2018 19:30:20 +0000 Message-Id: <20180208193021.24524-2-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208193021.24524-1-leif.lindholm@linaro.org> References: <20180208193021.24524-1-leif.lindholm@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/3] Platform/ARM: drop use of PcdCacheEnabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ard.biesheuvel@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PcdCacheEnabled does nothing useful for these platforms. Delete all uses of it here to keep the platforms building once the Pcd is removed from EmbeddedPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf | 3 --- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c | 6 +----- .../VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf | 3 --- .../ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c | 6 +----- .../ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | 3 --- .../VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf | 3 --- Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 4 +--- 7 files changed, 3 insertions(+), 25 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf index 2dd384daba..d3fc9b6cc7 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf @@ -43,9 +43,6 @@ [Sources.AARCH64] [Sources.ARM] Arm/ArmJunoHelper.S | GCC -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c index aa8d7d9c3b..2d9c2c95a8 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -72,11 +72,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = DDR_ATTRIBUTES_CACHED; // SMB CS0 - NOR0 Flash VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf index 9e81b1c1cc..329f80dcfe 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf @@ -40,9 +40,6 @@ [Sources.common] CTA15-A7Helper.asm | RVCT CTA15-A7Helper.S | GCC -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c index 4403cbacb8..05e9abc572 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c @@ -53,11 +53,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = DDR_ATTRIBUTES_CACHED; #ifdef ARM_BIGLITTLE_TC2 // Secure NOR0 Flash diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf index 4cbd2ff4b4..8c6291c42f 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -45,9 +45,6 @@ [Sources.ARM] [Sources.AARCH64] AArch64/RTSMHelper.S -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf index 269760f8ba..2287756cf8 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf @@ -41,9 +41,6 @@ [Sources.ARM] [Sources.AARCH64] AArch64/RTSMHelper.S -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 6379e81751..9fb0803d31 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -90,9 +90,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - CacheAttributes = (FeaturePcdGet(PcdCacheEnable)) - ? DDR_ATTRIBUTES_CACHED - : DDR_ATTRIBUTES_UNCACHED; + CacheAttributes = DDR_ATTRIBUTES_CACHED; // ReMap (Either NOR Flash or DRAM) VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; From patchwork Thu Feb 8 19:30:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leif Lindholm X-Patchwork-Id: 127743 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1798182ljc; Thu, 8 Feb 2018 11:30:31 -0800 (PST) X-Google-Smtp-Source: AH8x224K5IgmwRH4f6B2noC0D8WkRPgGq42QYZi2XA5B8zzTJTFRAUkKq4vsGcDkCJepnXW5xs8m X-Received: by 2002:a17:902:42a5:: with SMTP id h34-v6mr85226pld.265.1518118231682; Thu, 08 Feb 2018 11:30:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518118231; cv=none; d=google.com; s=arc-20160816; b=J9LGnini8ba/WZhD3IRvT5yzhbcxOg/hqRk5aC/8xWLaRvKpGgPuZQn2s8GPlFcObb MWfK2gbs8vTxd7RmkZQPkee89qCMiKf1K32DPsR+wSeocLmPNvxrU1akC8dWJpYuDnRy IGIIXe5098eUBsMC0xNjB/MM6xVnpTGgHo3e1SvaMlxcLKe56GANCsNqR6E6qfqR3P6K mItM38hgh6KsCSIo8NdM5dd4jnHILEdfDEPU/jGjrH92Ynyr/JpFrziTSrs//xhbzqC8 QD+PVOMVn6gOxGoeXnCONwuGNyLRttCGkddgboVar77wWuADHQtxzCt6AqR6s3xtSfvj q4iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=OqquYISqqlIhLcYym5QhIi4Q0u8JENEsYjrWl+LiPXY=; b=RaAHantWvoA1iTWiC/RnNLQQDzPHxDj3MR6+MN6JHOqlmTj6c2c8UTSs/MKuj540Nw CV5FQMAEObgek4dX/DT/IzKtyLUpAsCliYfOBmIxaNC+ebEqvnrB52TvrV/BwLroD6zj ugettyFHQl4JeN5vn8eaKisidEyEDIDDp5GjyDPeImoak3RazV6lm1dK/THKddOMu+zm wpp2kJ/EyWGtJ8diZZ4fxbeXPsQ8XgZWGf/EoQ+8JDwFOgMF6nUeMYRpd+HY/982eAUo /tT3ZNZzx40/68Lm/euDzIYYevqJOtUiRxNTlPn1HJpk6pGWs8FR8eddxHTn/gH7tnyJ 8jMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SleZLe4p; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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[82.12.0.119]) by smtp.gmail.com with ESMTPSA id s9sm805758wra.4.2018.02.08.11.30.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:30:25 -0800 (PST) From: Leif Lindholm To: edk2-devel@lists.01.org Date: Thu, 8 Feb 2018 19:30:21 +0000 Message-Id: <20180208193021.24524-3-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208193021.24524-1-leif.lindholm@linaro.org> References: <20180208193021.24524-1-leif.lindholm@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/3] (Platform/Silicon)/Hisilicon: drop use of PcdCacheEnabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ard.biesheuvel@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PcdCacheEnabled was never useful for these platforms, but it was copied over from other platforms used as templates. Delete it here to keep the platforms building once the Pcd is removed from EmbeddedPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf | 3 --- Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c | 6 +----- .../Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 3 --- .../Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 6 +----- .../Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 3 --- 5 files changed, 2 insertions(+), 19 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf index 79723d3b17..6a47a4501e 100644 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf @@ -41,9 +41,6 @@ [Sources.common] [Sources.AARCH64] HiKeyHelper.S -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCoreMask diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c index c388a7a5ab..0f6ad89a02 100644 --- a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c @@ -164,11 +164,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = DDR_ATTRIBUTES_CACHED; Index = 0; diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf index 0a3a6c1bb7..706497584e 100644 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf +++ b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf @@ -45,9 +45,6 @@ [Sources.common] [Sources.AARCH64] AArch64/Helper.S -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c index b7bc75dc74..c5a745a44b 100644 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c +++ b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c @@ -58,11 +58,7 @@ ArmPlatformGetVirtualMemoryMap ( return; } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } + CacheAttributes = DDR_ATTRIBUTES_CACHED; Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes); diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf index 23eca287fe..b31ea41f51 100644 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf +++ b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf @@ -41,9 +41,6 @@ [Sources.common] [Sources.AARCH64] AArch64/Helper.S -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize