From patchwork Tue Dec 15 20:21:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B066EC4361B for ; Tue, 15 Dec 2020 20:23:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8216E22475 for ; Tue, 15 Dec 2020 20:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727693AbgLOUWg (ORCPT ); Tue, 15 Dec 2020 15:22:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727653AbgLOUW1 (ORCPT ); Tue, 15 Dec 2020 15:22:27 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38692C061257; Tue, 15 Dec 2020 12:21:47 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id a9so42739612lfh.2; Tue, 15 Dec 2020 12:21:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wtdH0LNE+NSh6TW8ldGVLX31qyTyLDOz4GRbXPCqTQ0=; b=JJAwolf5vyTCjYLv6qT+h+KCPXlFFnj5p/D/kGRQVyqeVQv5XWe+HzpA5di+MRXj1E 9tzQGum618T5dEEjjTJ3Yn7QC8TPgeMhRdmAPkBBCrtiizeMzT37UnN+Vw166bORwWAD /folXNiPFzJeJvBdZOcze9xzFX2fQVEJxIkwwcA6ZmX8/gL5oDEKG/557dNdp9R8dEDN 035G5Sjp3t0m3wnzJdwn5p8UqcdJzTZryi4BHo8W6xeY7lc9tJ5AjdIzAtnuGHC9hbYA 5eH1CDY4ulErdyh92YwUhm99TR2cBBVYofUTsKCGIM9jL/eNGA3GkjzRt/sbuS3L+oEV gOSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wtdH0LNE+NSh6TW8ldGVLX31qyTyLDOz4GRbXPCqTQ0=; b=J+K8gGgdrp+YzB5x+PcGBWdHxdIL1OZ8MKjHfNu9InILSll9yoRrEyI0SWBB/AkboQ 5lpWe9DL0lKysZl+3SF/hhdnXK+E6Rw4hglRYApctkJrfQA4VIVZVFbLbTraXLNw0CVM 9Z9Hv5ZBYCj0DtyEcr11CntqzrBxrJ6LQ+4cxZxUmA6flI5OVOscNyoEJngOTJQxFFUh vlh8IPUPENiRKr51ZEYQVMtnKUOfldjc2ozJOTVrYJkeqK4f4ziKsOoO+EELfrs7BLyg /sE1R7j010mlZcmQZw/r1wQej2bRtA5mF/ooOzTgGCwS2cl7sIb84vFrkqcFC2H1XVcs bf7w== X-Gm-Message-State: AOAM532zdaUVO+MSldK7GpVDwjSnrLQsdTJiJWfzphuMBsC7I076C7fL xfiQxxdSsb47dsNgDojzAVU= X-Google-Smtp-Source: ABdhPJzITjqOSIEwAgaIe7Ic1rXMNJAekEbaepZ8B4LNaIUWC63Ul7cV5BeIKu5fRvTPGZ4cIoi1Dg== X-Received: by 2002:a2e:b0d5:: with SMTP id g21mr13163485ljl.372.1608063705777; Tue, 15 Dec 2020 12:21:45 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:45 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/8] usb: phy: tegra: Add delay after power up Date: Tue, 15 Dec 2020 23:21:06 +0300 Message-Id: <20201215202113.30394-2-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The PHY hardware needs the delay of 2ms after power up, otherwise initial interrupt may be lost if USB controller is accessed before PHY is settled down. Previously this issue was masked by implicit delays, but now it pops up after squashing the older ehci-tegra driver into the ChipIdea driver. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/phy/phy-tegra-usb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index 03a333797382..cee9c9dbb775 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -784,6 +784,9 @@ static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) phy->powered_on = true; + /* let PHY to settle down */ + usleep_range(2000, 2500); + return 0; } From patchwork Tue Dec 15 20:21:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A182C2BB9A for ; Tue, 15 Dec 2020 20:24:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 28BE322AAE for ; Tue, 15 Dec 2020 20:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727652AbgLOUWh (ORCPT ); Tue, 15 Dec 2020 15:22:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727658AbgLOUW2 (ORCPT ); Tue, 15 Dec 2020 15:22:28 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33C8FC0611C5; Tue, 15 Dec 2020 12:21:48 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id o17so39802947lfg.4; Tue, 15 Dec 2020 12:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cJqQuNC/mfXNFGNx5Da7HZGyoqOlnkc4HHGflJlaRm4=; b=ZsjRm7/2+WwS5yMDVcqBtINZ8NDdQo4KrJ9zfjqNm0tClLEdvC8mytysIseDyHSrI7 4PA/oHo2PFB1hyPau4DNMe51/ydX6WA1EhgFmrlQPPTCyegnNEEb5Zs+F1fUs9VlbwOm V6a6M9xUyfJKN8oy1wHqKBixRQraL64CY4GT16xeg9v4QNnikuZ43hKLCm3H7vvYZOF0 E/1UyKCvgZSmGadb4IKs2WJ2of2d+XWqEATc/z9o6cbevHk22pgK+7weGFWIACsuJn6h k0HD3HkMURpv4VMK8KLsEq23+nzyreNMr8JktfYEOX1yw1BjLw6CxzNlsjCY39Aa0i21 hyMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cJqQuNC/mfXNFGNx5Da7HZGyoqOlnkc4HHGflJlaRm4=; b=ZPyoPFi6JMUIJ5Hxjc0HiQujb5rozyL3/by/sQZE6XiL45MXfIvN/sHizYuqEFmbV9 IPtgglB+QrxwLnRztd3HllSkX/x0zMklhiaF6cMosmG3kRaLXEVKYeI1NOwY85jNx4GP hDt6ZQFiI6xBzCQJFhVDvgNJndVHx/U0M2pvsiz3wmdulDC4CZ8bBZiSAG8bWsmFNyTT Ap1EBJbyG6+XbpqGZTBOzLBSzgqLrYQTADCKbXAlSdGwGiXVwgje/G7PspGy2bhfq5z5 65zI2ycOFRRFLnKESaoRYebmZWxH5LOnYhIaFWHu1zYCtwPBQlPY08pT+E+KvuQoMqTN +VIg== X-Gm-Message-State: AOAM533ZrOnnCZlqAJiZm7+irJpFllS+rWcEHIjypAPmNCMsXfcf+suN N0PLSGoelzas9GeAKdQ2cMs= X-Google-Smtp-Source: ABdhPJylXdFXDL+gGmub2vLkwmt6ax30waBWb81m8BXl7CIAZujkuNCOGwXc1qvKDiacjNkgvQen4g== X-Received: by 2002:a2e:858a:: with SMTP id b10mr2358904lji.227.1608063706721; Tue, 15 Dec 2020 12:21:46 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:46 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/8] usb: phy: tegra: Support waking up from a low power mode Date: Tue, 15 Dec 2020 23:21:07 +0300 Message-Id: <20201215202113.30394-3-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Support programming of waking up from a low power mode by implementing the generic set_wakeup() callback of the USB PHY API. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/phy/phy-tegra-usb.c | 79 ++++++++++++++++++++++++++++--- include/linux/usb/tegra_usb_phy.h | 2 + 2 files changed, 75 insertions(+), 6 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index cee9c9dbb775..ed5f6611b36a 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -45,6 +45,7 @@ #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) #define USB_SUSP_CTRL 0x400 +#define USB_WAKE_ON_RESUME_EN BIT(2) #define USB_WAKE_ON_CNNT_EN_DEV BIT(3) #define USB_WAKE_ON_DISCON_EN_DEV BIT(4) #define USB_SUSP_CLR BIT(5) @@ -56,6 +57,9 @@ #define USB_SUSP_SET BIT(14) #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) +#define USB_PHY_VBUS_WAKEUP_ID 0x408 +#define VBUS_WAKEUP_WAKEUP_EN BIT(30) + #define USB1_LEGACY_CTRL 0x410 #define USB1_NO_LEGACY_MODE BIT(0) #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) @@ -334,6 +338,11 @@ static int utmip_pad_power_on(struct tegra_usb_phy *phy) writel_relaxed(val, base + UTMIP_BIAS_CFG0); } + if (phy->pad_wakeup) { + phy->pad_wakeup = false; + utmip_pad_count--; + } + spin_unlock(&utmip_pad_lock); clk_disable_unprepare(phy->pad_clk); @@ -359,6 +368,17 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy) goto ulock; } + /* + * In accordance to TRM, OTG and Bias pad circuits could be turned off + * to save power if wake is enabled, but the VBUS-change detection + * method is board-specific and these circuits may need to be enabled + * to generate wakeup event, hence we will just keep them both enabled. + */ + if (phy->wakeup_enabled) { + phy->pad_wakeup = true; + utmip_pad_count++; + } + if (--utmip_pad_count == 0) { val = readl_relaxed(base + UTMIP_BIAS_CFG0); val |= UTMIP_OTGPD | UTMIP_BIASPD; @@ -503,11 +523,19 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) writel_relaxed(val, base + UTMIP_PLL_CFG1); } + val = readl_relaxed(base + USB_SUSP_CTRL); + val &= ~USB_WAKE_ON_RESUME_EN; + writel_relaxed(val, base + USB_SUSP_CTRL); + if (phy->mode == USB_DR_MODE_PERIPHERAL) { val = readl_relaxed(base + USB_SUSP_CTRL); val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); writel_relaxed(val, base + USB_SUSP_CTRL); + val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); + val &= ~VBUS_WAKEUP_WAKEUP_EN; + writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); + val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); val &= ~UTMIP_PD_CHRG; writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); @@ -605,31 +633,51 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) utmi_phy_clk_disable(phy); - if (phy->mode == USB_DR_MODE_PERIPHERAL) { - val = readl_relaxed(base + USB_SUSP_CTRL); - val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); - val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); - writel_relaxed(val, base + USB_SUSP_CTRL); - } + /* PHY won't resume if reset is asserted */ + if (phy->wakeup_enabled) + goto chrg_cfg0; val = readl_relaxed(base + USB_SUSP_CTRL); val |= UTMIP_RESET; writel_relaxed(val, base + USB_SUSP_CTRL); +chrg_cfg0: val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); val |= UTMIP_PD_CHRG; writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); + if (phy->wakeup_enabled) + goto xcvr_cfg1; + val = readl_relaxed(base + UTMIP_XCVR_CFG0); val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN; writel_relaxed(val, base + UTMIP_XCVR_CFG0); +xcvr_cfg1: val = readl_relaxed(base + UTMIP_XCVR_CFG1); val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN; writel_relaxed(val, base + UTMIP_XCVR_CFG1); + if (phy->wakeup_enabled) { + val = readl_relaxed(base + USB_SUSP_CTRL); + val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); + val |= USB_WAKEUP_DEBOUNCE_COUNT(5); + val |= USB_WAKE_ON_RESUME_EN; + writel_relaxed(val, base + USB_SUSP_CTRL); + + /* + * Ask VBUS sensor to generate wake event once cable is + * connected. + */ + if (phy->mode == USB_DR_MODE_PERIPHERAL) { + val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); + val |= VBUS_WAKEUP_WAKEUP_EN; + writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); + } + } + return utmip_pad_power_off(phy); } @@ -765,6 +813,15 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy) usleep_range(5000, 6000); clk_disable_unprepare(phy->clk); + /* + * Wakeup currently unimplemented for ULPI, thus PHY needs to be + * force-resumed. + */ + if (WARN_ON_ONCE(phy->wakeup_enabled)) { + ulpi_phy_power_on(phy); + return -EOPNOTSUPP; + } + return 0; } @@ -827,6 +884,15 @@ static void tegra_usb_phy_shutdown(struct usb_phy *u_phy) phy->freq = NULL; } +static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable) +{ + struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); + + phy->wakeup_enabled = enable; + + return 0; +} + static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend) { struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); @@ -1198,6 +1264,7 @@ static int tegra_usb_phy_probe(struct platform_device *pdev) tegra_phy->u_phy.dev = &pdev->dev; tegra_phy->u_phy.init = tegra_usb_phy_init; tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown; + tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup; tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend; platform_set_drvdata(pdev, tegra_phy); diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index c29d1b4c9381..fd1c9f6a4e37 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -79,6 +79,8 @@ struct tegra_usb_phy { bool is_ulpi_phy; struct gpio_desc *reset_gpio; struct reset_control *pad_rst; + bool wakeup_enabled; + bool pad_wakeup; bool powered_on; }; From patchwork Tue Dec 15 20:21:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3B10C2BB48 for ; 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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:47 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/8] usb: chipidea: tegra: Remove MODULE_ALIAS Date: Tue, 15 Dec 2020 23:21:08 +0300 Message-Id: <20201215202113.30394-4-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The module alias is provided by the OF core for the OF drivers, it overrides the alias set by the drivers. Hence remove the unneeded macro in order to keep the driver code cleaner. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/usb/chipidea/ci_hdrc_tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index 7455df0ede49..10eaaba2a3f0 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -128,5 +128,4 @@ module_platform_driver(tegra_udc_driver); MODULE_DESCRIPTION("NVIDIA Tegra USB device mode driver"); MODULE_AUTHOR("Thierry Reding "); -MODULE_ALIAS("platform:tegra-udc"); MODULE_LICENSE("GPL v2"); From patchwork Tue Dec 15 20:21:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 420FDC2BB48 for ; Tue, 15 Dec 2020 20:31:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D03522573 for ; Tue, 15 Dec 2020 20:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728002AbgLOUbe (ORCPT ); Tue, 15 Dec 2020 15:31:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727407AbgLOUWa (ORCPT ); Tue, 15 Dec 2020 15:22:30 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3338CC0611CB; Tue, 15 Dec 2020 12:21:50 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id o13so19543998lfr.3; Tue, 15 Dec 2020 12:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LriiNL0B11yYagEvJlZ6UmmXdC2w+0m3jsvBoyDUI6o=; b=sqXDROPHjiEo8SSapQPDVr7rhunD8MVwGxgEGOC+ehECyoZ5Q8ialUnLVCibLkE2iG C3KlwG1z/kzVkD6cAJL9SRTQtK5cUNn9dEiwI11oY+riSK8WDrAFvBf3tF2/EmeWwyc2 U5QAA5//otRWq7UWoleDKLDWN6Z6c5AUp7qsTxs/qwx8vU7M9bhsszq8TUw28kso80kT ThX5rWoU9Qe6Q+kEVId69jCOgG6ax3KndtjCpUFYSCTQG3xiZr118GTFCSOO+XZeLjnB Lks0Cd5EQVJLokEzVoYMCWrjFMGoixFjjhbVHp03dumgwzQ+TsosR6Qv968cZHqDEtaX AGRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LriiNL0B11yYagEvJlZ6UmmXdC2w+0m3jsvBoyDUI6o=; b=NLJk5JCmCRnXCZxmfuU2gTaLA6hix3czhL1GxI+s1lSwCUwx5mtDu2v4CmWtLtJvKV U4aGebNKukrW6kvhCH8z/pXKJuZZ72LXwBt3Od3BMeiUURALahwoevrjIDNFhoxlbpBu 91RsSAARLGm9jjgYArYH2moyXbF7BTGkvPu1k2U6gAxQbbuwO4mNwUl8tjUQPtslN7ut nX7KqxCr5DuGo/7oYAw5OUJUda/4P/A9bI2cZ6W3x1VNccWqhwZ74aK8fHsXtT6nhOeU 2YiBDKVKCaZgacnOoe/fPrK3PxduZk4LBSFdOhsUlIiyVvYbvWOJZSRF/yf5NSmmYJx3 GCiA== X-Gm-Message-State: AOAM5329Hq8mxF6g7Dz7kGdRGJSsV/aLdUdAV1Q5sLVjo56mPgl3eew8 dFbTdv3PY30kMYn544pGSrg= X-Google-Smtp-Source: ABdhPJysasr/WNHPbS8QIonxwxP0+d6mrPjENnI+gCKrV7n9xXi9IiyHLsGaomzqkuMtIr+4tGUMwg== X-Received: by 2002:a2e:760c:: with SMTP id r12mr13059020ljc.11.1608063708724; Tue, 15 Dec 2020 12:21:48 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:48 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/8] usb: chipidea: tegra: Rename UDC to USB Date: Tue, 15 Dec 2020 23:21:09 +0300 Message-Id: <20201215202113.30394-5-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Rename all occurrences in the code from "udc" to "usb" and change the Kconfig entry in order to show that this driver supports USB modes other than device-only mode. The follow up patch will add host-mode support and it will be cleaner to perform the renaming separately, i.e. in this patch. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/chipidea/Kconfig | 2 +- drivers/usb/chipidea/ci_hdrc_tegra.c | 78 ++++++++++++++-------------- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig index 8bafcfc6080d..8685ead6ccc7 100644 --- a/drivers/usb/chipidea/Kconfig +++ b/drivers/usb/chipidea/Kconfig @@ -53,7 +53,7 @@ config USB_CHIPIDEA_GENERIC default USB_CHIPIDEA config USB_CHIPIDEA_TEGRA - tristate "Enable Tegra UDC glue driver" if EMBEDDED + tristate "Enable Tegra USB glue driver" if EMBEDDED depends on OF depends on USB_CHIPIDEA_UDC default USB_CHIPIDEA diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index 10eaaba2a3f0..d8efa80aa1c2 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -12,7 +12,7 @@ #include "ci.h" -struct tegra_udc { +struct tegra_usb { struct ci_hdrc_platform_data data; struct platform_device *dev; @@ -20,15 +20,15 @@ struct tegra_udc { struct clk *clk; }; -struct tegra_udc_soc_info { +struct tegra_usb_soc_info { unsigned long flags; }; -static const struct tegra_udc_soc_info tegra_udc_soc_info = { +static const struct tegra_usb_soc_info tegra_udc_soc_info = { .flags = CI_HDRC_REQUIRES_ALIGNED_DMA, }; -static const struct of_device_id tegra_udc_of_match[] = { +static const struct of_device_id tegra_usb_of_match[] = { { .compatible = "nvidia,tegra20-udc", .data = &tegra_udc_soc_info, @@ -45,16 +45,16 @@ static const struct of_device_id tegra_udc_of_match[] = { /* sentinel */ } }; -MODULE_DEVICE_TABLE(of, tegra_udc_of_match); +MODULE_DEVICE_TABLE(of, tegra_usb_of_match); -static int tegra_udc_probe(struct platform_device *pdev) +static int tegra_usb_probe(struct platform_device *pdev) { - const struct tegra_udc_soc_info *soc; - struct tegra_udc *udc; + const struct tegra_usb_soc_info *soc; + struct tegra_usb *usb; int err; - udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); - if (!udc) + usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL); + if (!usb) return -ENOMEM; soc = of_device_get_match_data(&pdev->dev); @@ -63,69 +63,69 @@ static int tegra_udc_probe(struct platform_device *pdev) return -EINVAL; } - udc->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); - if (IS_ERR(udc->phy)) { - err = PTR_ERR(udc->phy); + usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); + if (IS_ERR(usb->phy)) { + err = PTR_ERR(usb->phy); dev_err(&pdev->dev, "failed to get PHY: %d\n", err); return err; } - udc->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(udc->clk)) { - err = PTR_ERR(udc->clk); + usb->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(usb->clk)) { + err = PTR_ERR(usb->clk); dev_err(&pdev->dev, "failed to get clock: %d\n", err); return err; } - err = clk_prepare_enable(udc->clk); + err = clk_prepare_enable(usb->clk); if (err < 0) { dev_err(&pdev->dev, "failed to enable clock: %d\n", err); return err; } /* setup and register ChipIdea HDRC device */ - udc->data.name = "tegra-udc"; - udc->data.flags = soc->flags; - udc->data.usb_phy = udc->phy; - udc->data.capoffset = DEF_CAPOFFSET; - - udc->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, - pdev->num_resources, &udc->data); - if (IS_ERR(udc->dev)) { - err = PTR_ERR(udc->dev); + usb->data.name = "tegra-usb"; + usb->data.flags = soc->flags; + usb->data.usb_phy = usb->phy; + usb->data.capoffset = DEF_CAPOFFSET; + + usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, + pdev->num_resources, &usb->data); + if (IS_ERR(usb->dev)) { + err = PTR_ERR(usb->dev); dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err); goto fail_power_off; } - platform_set_drvdata(pdev, udc); + platform_set_drvdata(pdev, usb); return 0; fail_power_off: - clk_disable_unprepare(udc->clk); + clk_disable_unprepare(usb->clk); return err; } -static int tegra_udc_remove(struct platform_device *pdev) +static int tegra_usb_remove(struct platform_device *pdev) { - struct tegra_udc *udc = platform_get_drvdata(pdev); + struct tegra_usb *usb = platform_get_drvdata(pdev); - ci_hdrc_remove_device(udc->dev); - clk_disable_unprepare(udc->clk); + ci_hdrc_remove_device(usb->dev); + clk_disable_unprepare(usb->clk); return 0; } -static struct platform_driver tegra_udc_driver = { +static struct platform_driver tegra_usb_driver = { .driver = { - .name = "tegra-udc", - .of_match_table = tegra_udc_of_match, + .name = "tegra-usb", + .of_match_table = tegra_usb_of_match, }, - .probe = tegra_udc_probe, - .remove = tegra_udc_remove, + .probe = tegra_usb_probe, + .remove = tegra_usb_remove, }; -module_platform_driver(tegra_udc_driver); +module_platform_driver(tegra_usb_driver); -MODULE_DESCRIPTION("NVIDIA Tegra USB device mode driver"); +MODULE_DESCRIPTION("NVIDIA Tegra USB driver"); MODULE_AUTHOR("Thierry Reding "); MODULE_LICENSE("GPL v2"); From patchwork Tue Dec 15 20:21:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96594C2BB9A for ; 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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:49 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/8] usb: chipidea: tegra: Support host mode Date: Tue, 15 Dec 2020 23:21:10 +0300 Message-Id: <20201215202113.30394-6-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Peter Geis Add USB host mode to the Tegra HDRC driver. This allows us to benefit from support provided by the generic ChipIdea driver instead of duplicating the effort in a separate ehci-terga driver. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Signed-off-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/chipidea/Kconfig | 1 - drivers/usb/chipidea/ci_hdrc_tegra.c | 243 ++++++++++++++++++++++++++- drivers/usb/chipidea/core.c | 10 +- drivers/usb/chipidea/host.c | 103 +++++++++++- include/linux/usb/chipidea.h | 6 + 5 files changed, 355 insertions(+), 8 deletions(-) diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig index 8685ead6ccc7..661818e8fed6 100644 --- a/drivers/usb/chipidea/Kconfig +++ b/drivers/usb/chipidea/Kconfig @@ -55,7 +55,6 @@ config USB_CHIPIDEA_GENERIC config USB_CHIPIDEA_TEGRA tristate "Enable Tegra USB glue driver" if EMBEDDED depends on OF - depends on USB_CHIPIDEA_UDC default USB_CHIPIDEA endif diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index d8efa80aa1c2..fff130f08996 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -4,11 +4,18 @@ */ #include +#include #include #include #include +#include #include +#include +#include +#include + +#include "../host/ehci.h" #include "ci.h" @@ -16,20 +23,47 @@ struct tegra_usb { struct ci_hdrc_platform_data data; struct platform_device *dev; + const struct tegra_usb_soc_info *soc; struct usb_phy *phy; struct clk *clk; + + bool needs_double_reset; }; struct tegra_usb_soc_info { unsigned long flags; + unsigned int txfifothresh; + enum usb_dr_mode dr_mode; +}; + +static const struct tegra_usb_soc_info tegra20_ehci_soc_info = { + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | + CI_HDRC_OVERRIDE_PHY_CONTROL, + .dr_mode = USB_DR_MODE_HOST, + .txfifothresh = 10, +}; + +static const struct tegra_usb_soc_info tegra30_ehci_soc_info = { + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | + CI_HDRC_OVERRIDE_PHY_CONTROL + .dr_mode = USB_DR_MODE_HOST, + .txfifothresh = 16, }; static const struct tegra_usb_soc_info tegra_udc_soc_info = { - .flags = CI_HDRC_REQUIRES_ALIGNED_DMA, + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | + CI_HDRC_OVERRIDE_PHY_CONTROL, + .dr_mode = USB_DR_MODE_UNKNOWN, }; static const struct of_device_id tegra_usb_of_match[] = { { + .compatible = "nvidia,tegra20-ehci", + .data = &tegra20_ehci_soc_info, + }, { + .compatible = "nvidia,tegra30-ehci", + .data = &tegra30_ehci_soc_info, + }, { .compatible = "nvidia,tegra20-udc", .data = &tegra_udc_soc_info, }, { @@ -47,6 +81,181 @@ static const struct of_device_id tegra_usb_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_usb_of_match); +static int tegra_usb_reset_controller(struct device *dev) +{ + struct reset_control *rst, *rst_utmi; + struct device_node *phy_np; + int err; + + rst = devm_reset_control_get_shared(dev, "usb"); + if (IS_ERR(rst)) { + dev_err(dev, "can't get ehci reset: %pe\n", rst); + return PTR_ERR(rst); + } + + phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0); + if (!phy_np) + return -ENOENT; + + /* + * The 1st USB controller contains some UTMI pad registers that are + * global for all the controllers on the chip. Those registers are + * also cleared when reset is asserted to the 1st controller. + */ + rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads"); + if (IS_ERR(rst_utmi)) { + dev_warn(dev, "can't get utmi-pads reset from the PHY\n"); + dev_warn(dev, "continuing, but please update your DT\n"); + } else { + /* + * PHY driver performs UTMI-pads reset in a case of a + * non-legacy DT. + */ + reset_control_put(rst_utmi); + } + + of_node_put(phy_np); + + /* reset control is shared, hence initialize it first */ + err = reset_control_deassert(rst); + if (err) + return err; + + err = reset_control_assert(rst); + if (err) + return err; + + udelay(1); + + err = reset_control_deassert(rst); + if (err) + return err; + + return 0; +} + +static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event) +{ + struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent); + struct ehci_hcd *ehci; + + switch (event) { + case CI_HDRC_CONTROLLER_RESET_EVENT: + if (ci->hcd) { + ehci = hcd_to_ehci(ci->hcd); + ehci->has_tdi_phy_lpm = false; + ehci_writel(ehci, usb->soc->txfifothresh << 16, + &ehci->regs->txfill_tuning); + } + break; + } + + return 0; +} + +static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci, + u32 __iomem *portsc_reg, + unsigned long *flags) +{ + u32 saved_usbintr, temp; + unsigned int i, tries; + int retval = 0; + + saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); + /* disable USB interrupt */ + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + spin_unlock_irqrestore(&ehci->lock, *flags); + + /* + * Here we have to do Port Reset at most twice for + * Port Enable bit to be set. + */ + for (i = 0; i < 2; i++) { + temp = ehci_readl(ehci, portsc_reg); + temp |= PORT_RESET; + ehci_writel(ehci, temp, portsc_reg); + mdelay(10); + temp &= ~PORT_RESET; + ehci_writel(ehci, temp, portsc_reg); + mdelay(1); + tries = 100; + do { + mdelay(1); + /* + * Up to this point, Port Enable bit is + * expected to be set after 2 ms waiting. + * USB1 usually takes extra 45 ms, for safety, + * we take 100 ms as timeout. + */ + temp = ehci_readl(ehci, portsc_reg); + } while (!(temp & PORT_PE) && tries--); + if (temp & PORT_PE) + break; + } + if (i == 2) + retval = -ETIMEDOUT; + + /* + * Clear Connect Status Change bit if it's set. + * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. + */ + if (temp & PORT_CSC) + ehci_writel(ehci, PORT_CSC, portsc_reg); + + /* + * Write to clear any interrupt status bits that might be set + * during port reset. + */ + temp = ehci_readl(ehci, &ehci->regs->status); + ehci_writel(ehci, temp, &ehci->regs->status); + + /* restore original interrupt-enable bits */ + spin_lock_irqsave(&ehci->lock, *flags); + ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); + + return retval; +} + +static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue, + u16 wIndex, char *buf, u16 wLength, + bool *done, unsigned long *flags) +{ + struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent); + struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd); + u32 __iomem *status_reg; + int retval = 0; + + status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; + + switch (typeReq) { + case SetPortFeature: + if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset) + break; + + /* for USB1 port we need to issue Port Reset twice internally */ + retval = tegra_usb_internal_port_reset(ehci, status_reg, flags); + *done = true; + break; + } + + return retval; +} + +static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable) +{ + /* + * Touching any register which belongs to AHB clock domain will + * hang CPU if USB controller is put into low power mode because + * AHB USB clock is gated on Tegra in the LPM. + * + * Tegra PHY has a separate register for checking the clock status + * and usb_phy_set_suspend() takes care of gating/ungating the clocks + * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers + * shouldn't be touched directly by the CI driver. + */ + usb_phy_set_suspend(ci->usb_phy, enable); +} + static int tegra_usb_probe(struct platform_device *pdev) { const struct tegra_usb_soc_info *soc; @@ -83,24 +292,49 @@ static int tegra_usb_probe(struct platform_device *pdev) return err; } + if (device_property_present(&pdev->dev, "nvidia,needs-double-reset")) + usb->needs_double_reset = true; + + err = tegra_usb_reset_controller(&pdev->dev); + if (err) { + dev_err(&pdev->dev, "failed to reset controller: %d\n", err); + goto fail_power_off; + } + + /* + * USB controller registers shan't be touched before PHY is + * initialized, otherwise CPU will hang because clocks are gated. + * PHY driver controls gating of internal USB clocks on Tegra. + */ + err = usb_phy_init(usb->phy); + if (err) + goto fail_power_off; + + platform_set_drvdata(pdev, usb); + /* setup and register ChipIdea HDRC device */ + usb->soc = soc; usb->data.name = "tegra-usb"; usb->data.flags = soc->flags; usb->data.usb_phy = usb->phy; + usb->data.dr_mode = soc->dr_mode; usb->data.capoffset = DEF_CAPOFFSET; + usb->data.enter_lpm = tegra_usb_enter_lpm; + usb->data.hub_control = tegra_ehci_hub_control; + usb->data.notify_event = tegra_usb_notify_event; usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, pdev->num_resources, &usb->data); if (IS_ERR(usb->dev)) { err = PTR_ERR(usb->dev); dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err); - goto fail_power_off; + goto phy_shutdown; } - platform_set_drvdata(pdev, usb); - return 0; +phy_shutdown: + usb_phy_shutdown(usb->phy); fail_power_off: clk_disable_unprepare(usb->clk); return err; @@ -111,6 +345,7 @@ static int tegra_usb_remove(struct platform_device *pdev) struct tegra_usb *usb = platform_get_drvdata(pdev); ci_hdrc_remove_device(usb->dev); + usb_phy_shutdown(usb->phy); clk_disable_unprepare(usb->clk); return 0; diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index aa40e510b806..3f6c21406dbd 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -195,7 +195,7 @@ static void hw_wait_phy_stable(void) } /* The PHY enters/leaves low power mode */ -static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) +static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable) { enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); @@ -208,6 +208,11 @@ static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 0); } +static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) +{ + return ci->platdata->enter_lpm(ci, enable); +} + static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) { u32 reg; @@ -790,6 +795,9 @@ static int ci_get_platdata(struct device *dev, platdata->pins_device = p; } + if (!platdata->enter_lpm) + platdata->enter_lpm = ci_hdrc_enter_lpm_common; + return 0; } diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index 48e4a5ca1835..b8a4c44ab580 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -29,6 +29,12 @@ struct ehci_ci_priv { bool enabled; }; +struct ci_hdrc_dma_aligned_buffer { + void *kmalloc_ptr; + void *old_xfer_buffer; + u8 data[0]; +}; + static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); @@ -160,14 +166,14 @@ static int host_start(struct ci_hdrc *ci) pinctrl_select_state(ci->platdata->pctl, ci->platdata->pins_host); + ci->hcd = hcd; + ret = usb_add_hcd(hcd, 0, 0); if (ret) { goto disable_reg; } else { struct usb_otg *otg = &ci->otg; - ci->hcd = hcd; - if (ci_otg_is_fsm_mode(ci)) { otg->host = &hcd->self; hcd->self.otg_port = 1; @@ -237,6 +243,7 @@ static int ci_ehci_hub_control( u32 temp; unsigned long flags; int retval = 0; + bool done = false; struct device *dev = hcd->self.controller; struct ci_hdrc *ci = dev_get_drvdata(dev); @@ -244,6 +251,13 @@ static int ci_ehci_hub_control( spin_lock_irqsave(&ehci->lock, flags); + if (ci->platdata->hub_control) { + retval = ci->platdata->hub_control(ci, typeReq, wValue, wIndex, + buf, wLength, &done, &flags); + if (done) + goto done; + } + if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { temp = ehci_readl(ehci, status_reg); if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { @@ -349,6 +363,86 @@ static int ci_ehci_bus_suspend(struct usb_hcd *hcd) return 0; } +static void ci_hdrc_free_dma_aligned_buffer(struct urb *urb) +{ + struct ci_hdrc_dma_aligned_buffer *temp; + size_t length; + + if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) + return; + + temp = container_of(urb->transfer_buffer, + struct ci_hdrc_dma_aligned_buffer, data); + + if (usb_urb_dir_in(urb)) { + if (usb_pipeisoc(urb->pipe)) + length = urb->transfer_buffer_length; + else + length = urb->actual_length; + + memcpy(temp->old_xfer_buffer, temp->data, length); + } + urb->transfer_buffer = temp->old_xfer_buffer; + kfree(temp->kmalloc_ptr); + + urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; +} + +static int ci_hdrc_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) +{ + struct ci_hdrc_dma_aligned_buffer *temp, *kmalloc_ptr; + const unsigned int ci_hdrc_usb_dma_align = 32; + size_t kmalloc_size; + + if (urb->num_sgs || urb->sg || urb->transfer_buffer_length == 0 || + !((uintptr_t)urb->transfer_buffer & (ci_hdrc_usb_dma_align - 1))) + return 0; + + /* Allocate a buffer with enough padding for alignment */ + kmalloc_size = urb->transfer_buffer_length + + sizeof(struct ci_hdrc_dma_aligned_buffer) + + ci_hdrc_usb_dma_align - 1; + + kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); + if (!kmalloc_ptr) + return -ENOMEM; + + /* Position our struct dma_aligned_buffer such that data is aligned */ + temp = PTR_ALIGN(kmalloc_ptr + 1, ci_hdrc_usb_dma_align) - 1; + temp->kmalloc_ptr = kmalloc_ptr; + temp->old_xfer_buffer = urb->transfer_buffer; + if (usb_urb_dir_out(urb)) + memcpy(temp->data, urb->transfer_buffer, + urb->transfer_buffer_length); + urb->transfer_buffer = temp->data; + + urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; + + return 0; +} + +static int ci_hdrc_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, + gfp_t mem_flags) +{ + int ret; + + ret = ci_hdrc_alloc_dma_aligned_buffer(urb, mem_flags); + if (ret) + return ret; + + ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); + if (ret) + ci_hdrc_free_dma_aligned_buffer(urb); + + return ret; +} + +static void ci_hdrc_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) +{ + usb_hcd_unmap_urb_for_dma(hcd, urb); + ci_hdrc_free_dma_aligned_buffer(urb); +} + int ci_hdrc_host_init(struct ci_hdrc *ci) { struct ci_role_driver *rdrv; @@ -366,6 +460,11 @@ int ci_hdrc_host_init(struct ci_hdrc *ci) rdrv->name = "host"; ci->roles[CI_ROLE_HOST] = rdrv; + if (ci->platdata->flags & CI_HDRC_REQUIRES_ALIGNED_DMA) { + ci_ehci_hc_driver.map_urb_for_dma = ci_hdrc_map_urb_for_dma; + ci_ehci_hc_driver.unmap_urb_for_dma = ci_hdrc_unmap_urb_for_dma; + } + return 0; } diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index 025b41687ce9..edf3342507f1 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -88,6 +88,12 @@ struct ci_hdrc_platform_data { struct pinctrl_state *pins_default; struct pinctrl_state *pins_host; struct pinctrl_state *pins_device; + + /* platform-specific hooks */ + int (*hub_control)(struct ci_hdrc *ci, u16 typeReq, u16 wValue, + u16 wIndex, char *buf, u16 wLength, + bool *done, unsigned long *flags); + void (*enter_lpm)(struct ci_hdrc *ci, bool enable); }; /* Default offset of capability registers */ From patchwork Tue Dec 15 20:21:11 2020 Content-Type: text/plain; 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[109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:50 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/8] usb: chipidea: tegra: Support runtime PM Date: Tue, 15 Dec 2020 23:21:11 +0300 Message-Id: <20201215202113.30394-7-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Tegra PHY driver now supports waking up controller from a low power mode. Enable runtime PM in order to put controller into the LPM during idle. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/chipidea/ci_hdrc_tegra.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index fff130f08996..4531c2b069fe 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -38,21 +38,24 @@ struct tegra_usb_soc_info { static const struct tegra_usb_soc_info tegra20_ehci_soc_info = { .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | - CI_HDRC_OVERRIDE_PHY_CONTROL, + CI_HDRC_OVERRIDE_PHY_CONTROL | + CI_HDRC_SUPPORTS_RUNTIME_PM, .dr_mode = USB_DR_MODE_HOST, .txfifothresh = 10, }; static const struct tegra_usb_soc_info tegra30_ehci_soc_info = { .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | - CI_HDRC_OVERRIDE_PHY_CONTROL + CI_HDRC_OVERRIDE_PHY_CONTROL | + CI_HDRC_SUPPORTS_RUNTIME_PM, .dr_mode = USB_DR_MODE_HOST, .txfifothresh = 16, }; static const struct tegra_usb_soc_info tegra_udc_soc_info = { .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | - CI_HDRC_OVERRIDE_PHY_CONTROL, + CI_HDRC_OVERRIDE_PHY_CONTROL | + CI_HDRC_SUPPORTS_RUNTIME_PM, .dr_mode = USB_DR_MODE_UNKNOWN, }; @@ -323,6 +326,10 @@ static int tegra_usb_probe(struct platform_device *pdev) usb->data.hub_control = tegra_ehci_hub_control; usb->data.notify_event = tegra_usb_notify_event; + /* Tegra PHY driver currently doesn't support LPM for ULPI */ + if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI) + usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM; + usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, pdev->num_resources, &usb->data); if (IS_ERR(usb->dev)) { From patchwork Tue Dec 15 20:21:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2BEAC2BBCA for ; Tue, 15 Dec 2020 20:30:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0F4722C7B for ; Tue, 15 Dec 2020 20:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726330AbgLOUXe (ORCPT ); Tue, 15 Dec 2020 15:23:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727768AbgLOUXM (ORCPT ); Tue, 15 Dec 2020 15:23:12 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58B05C0611CE; Tue, 15 Dec 2020 12:21:53 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id l11so42773472lfg.0; Tue, 15 Dec 2020 12:21:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mCBGRL0NoE54pplFsMnc1gFJhjVImYEmO0rYWTnYwhs=; b=Rr9AjVFEPHuMPjDzmRAvhWFO8vnS/XjUG7MLsH8T8DOmRIpArqqNBlMe+T7xJOJUD3 1wkKmtYJueEit8WTKzDmniNuSH5jwf3LsG+WgB2gElrFoUY/yhDrjYB7KkDuBrwbo1Pu e+HTTmEpv2hSVg1ag5/2JrnqNXirvyifXCRN9+K5hcMMJYmcrJdAtNIvVuHNm+Wg3fE7 woRun5s8KYOJRdLfV7wQc+H1YxnzSuewAZzt6Tx761a4pKAi0uPwFLacpk13pIeBuXpt MLKfVJH4BX0YVkUP8C1et0bWNL5zYiVW/bZd61qI925HfSpF123qHx4I9CvHqXdaJ8MO bQAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mCBGRL0NoE54pplFsMnc1gFJhjVImYEmO0rYWTnYwhs=; b=mvq1tzjWhtYydqwsVbnTaAfXFyKR6E5qq3/dPzzqsAOqpneAQnPRVd8NXNPsYENN8w QOTbl87qfQD8PjaAYLypZNJ7IInibIaHcJp+m8VqidEDjxKDo1QE5/1WXeVlJGtffV1o yhxxBP0NVUr7wuuPsZQJSNTGp4OH+pyVYBGLZT+LFS7XDL6sxxlHb4UzCu7eNOgbk/DM NFIPzicGA04PI1xveV9MK38at53Ovl4CFntOPD3kbUIxqWWM5GAYY5BIFEbNhLZAMjdV 8WZKUHDj9GZmrDM09YFoTc0FHRVgkdgB39al5v2WRNEMw0FBmExMBGmen6K7z+Ksyk/7 U/Zg== X-Gm-Message-State: AOAM5312y4P4fJkLcx44K4FDvjGx/cB7XmdWR6fXMVM+encUsNDRLQVf QzU3NmACzNNN6JbOBsIh4ms= X-Google-Smtp-Source: ABdhPJyHsY2G1EkqfJsgL0NdC2TQ40WwLEjlNygb3NlVjdYrhHtPWJhjnx1dWIsRhIYGd7y6uDJ7JA== X-Received: by 2002:a19:a40a:: with SMTP id q10mr3425294lfc.39.1608063711685; Tue, 15 Dec 2020 12:21:51 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:51 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 7/8] usb: host: ehci-tegra: Remove the driver Date: Tue, 15 Dec 2020 23:21:12 +0300 Message-Id: <20201215202113.30394-8-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The ChipIdea driver now provides USB2 host mode support for NVIDIA Tegra SoCs. The ehci-tegra driver is obsolete now, remove it. Tested-by: Matt Merhar Tested-by: Nicolas Chauvet Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/host/Kconfig | 9 - drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-tegra.c | 604 ---------------------------------- 3 files changed, 614 deletions(-) delete mode 100644 drivers/usb/host/ehci-tegra.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 31e59309da1f..9c9e6ff9c43a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -266,15 +266,6 @@ config USB_EHCI_HCD_AT91 Enables support for the on-chip EHCI controller on Atmel chips. -config USB_EHCI_TEGRA - tristate "NVIDIA Tegra HCD support" - depends on ARCH_TEGRA - select USB_EHCI_ROOT_HUB_TT - select USB_TEGRA_PHY - help - This driver enables support for the internal USB Host Controllers - found in NVIDIA Tegra SoCs. The controllers are EHCI compliant. - config USB_EHCI_HCD_PPC_OF bool "EHCI support for PPC USB controller on OF platform bus" depends on PPC diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index c1b08703af10..3e4d298d851f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-st.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o -obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c deleted file mode 100644 index 869d9c4de5fc..000000000000 --- a/drivers/usb/host/ehci-tegra.c +++ /dev/null @@ -1,604 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2009 - 2013 NVIDIA Corporation - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ehci.h" - -#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) - -#define TEGRA_USB_DMA_ALIGN 32 - -#define DRIVER_DESC "Tegra EHCI driver" -#define DRV_NAME "tegra-ehci" - -static struct hc_driver __read_mostly tegra_ehci_hc_driver; - -struct tegra_ehci_soc_config { - bool has_hostpc; -}; - -struct tegra_ehci_hcd { - struct clk *clk; - struct reset_control *rst; - int port_resuming; - bool needs_double_reset; -}; - -static int tegra_reset_usb_controller(struct platform_device *pdev) -{ - struct device_node *phy_np; - struct usb_hcd *hcd = platform_get_drvdata(pdev); - struct tegra_ehci_hcd *tegra = - (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv; - struct reset_control *rst; - int err; - - phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0); - if (!phy_np) - return -ENOENT; - - /* - * The 1st USB controller contains some UTMI pad registers that are - * global for all the controllers on the chip. Those registers are - * also cleared when reset is asserted to the 1st controller. - */ - rst = of_reset_control_get_shared(phy_np, "utmi-pads"); - if (IS_ERR(rst)) { - dev_warn(&pdev->dev, - "can't get utmi-pads reset from the PHY\n"); - dev_warn(&pdev->dev, - "continuing, but please update your DT\n"); - } else { - /* - * PHY driver performs UTMI-pads reset in a case of - * non-legacy DT. - */ - reset_control_put(rst); - } - - of_node_put(phy_np); - - /* reset control is shared, hence initialize it first */ - err = reset_control_deassert(tegra->rst); - if (err) - return err; - - err = reset_control_assert(tegra->rst); - if (err) - return err; - - udelay(1); - - err = reset_control_deassert(tegra->rst); - if (err) - return err; - - return 0; -} - -static int tegra_ehci_internal_port_reset( - struct ehci_hcd *ehci, - u32 __iomem *portsc_reg -) -{ - u32 temp; - unsigned long flags; - int retval = 0; - int i, tries; - u32 saved_usbintr; - - spin_lock_irqsave(&ehci->lock, flags); - saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); - /* disable USB interrupt */ - ehci_writel(ehci, 0, &ehci->regs->intr_enable); - spin_unlock_irqrestore(&ehci->lock, flags); - - /* - * Here we have to do Port Reset at most twice for - * Port Enable bit to be set. - */ - for (i = 0; i < 2; i++) { - temp = ehci_readl(ehci, portsc_reg); - temp |= PORT_RESET; - ehci_writel(ehci, temp, portsc_reg); - mdelay(10); - temp &= ~PORT_RESET; - ehci_writel(ehci, temp, portsc_reg); - mdelay(1); - tries = 100; - do { - mdelay(1); - /* - * Up to this point, Port Enable bit is - * expected to be set after 2 ms waiting. - * USB1 usually takes extra 45 ms, for safety, - * we take 100 ms as timeout. - */ - temp = ehci_readl(ehci, portsc_reg); - } while (!(temp & PORT_PE) && tries--); - if (temp & PORT_PE) - break; - } - if (i == 2) - retval = -ETIMEDOUT; - - /* - * Clear Connect Status Change bit if it's set. - * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. - */ - if (temp & PORT_CSC) - ehci_writel(ehci, PORT_CSC, portsc_reg); - - /* - * Write to clear any interrupt status bits that might be set - * during port reset. - */ - temp = ehci_readl(ehci, &ehci->regs->status); - ehci_writel(ehci, temp, &ehci->regs->status); - - /* restore original interrupt enable bits */ - ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); - return retval; -} - -static int tegra_ehci_hub_control( - struct usb_hcd *hcd, - u16 typeReq, - u16 wValue, - u16 wIndex, - char *buf, - u16 wLength -) -{ - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv; - u32 __iomem *status_reg; - u32 temp; - unsigned long flags; - int retval = 0; - - status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; - - spin_lock_irqsave(&ehci->lock, flags); - - if (typeReq == GetPortStatus) { - temp = ehci_readl(ehci, status_reg); - if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { - /* Resume completed, re-enable disconnect detection */ - tegra->port_resuming = 0; - tegra_usb_phy_postresume(hcd->usb_phy); - } - } - - else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { - temp = ehci_readl(ehci, status_reg); - if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { - retval = -EPIPE; - goto done; - } - - temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); - temp |= PORT_WKDISC_E | PORT_WKOC_E; - ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); - - /* - * If a transaction is in progress, there may be a delay in - * suspending the port. Poll until the port is suspended. - */ - if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, - PORT_SUSPEND, 5000)) - pr_err("%s: timeout waiting for SUSPEND\n", __func__); - - set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); - goto done; - } - - /* For USB1 port we need to issue Port Reset twice internally */ - if (tegra->needs_double_reset && - (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { - spin_unlock_irqrestore(&ehci->lock, flags); - return tegra_ehci_internal_port_reset(ehci, status_reg); - } - - /* - * Tegra host controller will time the resume operation to clear the bit - * when the port control state switches to HS or FS Idle. This behavior - * is different from EHCI where the host controller driver is required - * to set this bit to a zero after the resume duration is timed in the - * driver. - */ - else if (typeReq == ClearPortFeature && - wValue == USB_PORT_FEAT_SUSPEND) { - temp = ehci_readl(ehci, status_reg); - if ((temp & PORT_RESET) || !(temp & PORT_PE)) { - retval = -EPIPE; - goto done; - } - - if (!(temp & PORT_SUSPEND)) - goto done; - - /* Disable disconnect detection during port resume */ - tegra_usb_phy_preresume(hcd->usb_phy); - - ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); - - temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); - /* start resume signalling */ - ehci_writel(ehci, temp | PORT_RESUME, status_reg); - set_bit(wIndex-1, &ehci->resuming_ports); - - spin_unlock_irqrestore(&ehci->lock, flags); - msleep(20); - spin_lock_irqsave(&ehci->lock, flags); - - /* Poll until the controller clears RESUME and SUSPEND */ - if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) - pr_err("%s: timeout waiting for RESUME\n", __func__); - if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) - pr_err("%s: timeout waiting for SUSPEND\n", __func__); - - ehci->reset_done[wIndex-1] = 0; - clear_bit(wIndex-1, &ehci->resuming_ports); - - tegra->port_resuming = 1; - goto done; - } - - spin_unlock_irqrestore(&ehci->lock, flags); - - /* Handle the hub control events here */ - return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); - -done: - spin_unlock_irqrestore(&ehci->lock, flags); - return retval; -} - -struct dma_aligned_buffer { - void *kmalloc_ptr; - void *old_xfer_buffer; - u8 data[]; -}; - -static void free_dma_aligned_buffer(struct urb *urb) -{ - struct dma_aligned_buffer *temp; - size_t length; - - if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) - return; - - temp = container_of(urb->transfer_buffer, - struct dma_aligned_buffer, data); - - if (usb_urb_dir_in(urb)) { - if (usb_pipeisoc(urb->pipe)) - length = urb->transfer_buffer_length; - else - length = urb->actual_length; - - memcpy(temp->old_xfer_buffer, temp->data, length); - } - urb->transfer_buffer = temp->old_xfer_buffer; - kfree(temp->kmalloc_ptr); - - urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; -} - -static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) -{ - struct dma_aligned_buffer *temp, *kmalloc_ptr; - size_t kmalloc_size; - - if (urb->num_sgs || urb->sg || - urb->transfer_buffer_length == 0 || - !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) - return 0; - - /* Allocate a buffer with enough padding for alignment */ - kmalloc_size = urb->transfer_buffer_length + - sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; - - kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); - if (!kmalloc_ptr) - return -ENOMEM; - - /* Position our struct dma_aligned_buffer such that data is aligned */ - temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; - temp->kmalloc_ptr = kmalloc_ptr; - temp->old_xfer_buffer = urb->transfer_buffer; - if (usb_urb_dir_out(urb)) - memcpy(temp->data, urb->transfer_buffer, - urb->transfer_buffer_length); - urb->transfer_buffer = temp->data; - - urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; - - return 0; -} - -static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, - gfp_t mem_flags) -{ - int ret; - - ret = alloc_dma_aligned_buffer(urb, mem_flags); - if (ret) - return ret; - - ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); - if (ret) - free_dma_aligned_buffer(urb); - - return ret; -} - -static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) -{ - usb_hcd_unmap_urb_for_dma(hcd, urb); - free_dma_aligned_buffer(urb); -} - -static const struct tegra_ehci_soc_config tegra30_soc_config = { - .has_hostpc = true, -}; - -static const struct tegra_ehci_soc_config tegra20_soc_config = { - .has_hostpc = false, -}; - -static const struct of_device_id tegra_ehci_of_match[] = { - { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config }, - { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config }, - { }, -}; - -static int tegra_ehci_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - const struct tegra_ehci_soc_config *soc_config; - struct resource *res; - struct usb_hcd *hcd; - struct ehci_hcd *ehci; - struct tegra_ehci_hcd *tegra; - int err = 0; - int irq; - struct usb_phy *u_phy; - - match = of_match_device(tegra_ehci_of_match, &pdev->dev); - if (!match) { - dev_err(&pdev->dev, "Error: No device match found\n"); - return -ENODEV; - } - soc_config = match->data; - - /* Right now device-tree probed devices don't get dma_mask set. - * Since shared usb code relies on it, set it here for now. - * Once we have dma capability bindings this can go away. - */ - err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); - if (err) - return err; - - hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) { - dev_err(&pdev->dev, "Unable to create HCD\n"); - return -ENOMEM; - } - platform_set_drvdata(pdev, hcd); - ehci = hcd_to_ehci(hcd); - tegra = (struct tegra_ehci_hcd *)ehci->priv; - - hcd->has_tt = 1; - - tegra->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(tegra->clk)) { - dev_err(&pdev->dev, "Can't get ehci clock\n"); - err = PTR_ERR(tegra->clk); - goto cleanup_hcd_create; - } - - tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb"); - if (IS_ERR(tegra->rst)) { - dev_err(&pdev->dev, "Can't get ehci reset\n"); - err = PTR_ERR(tegra->rst); - goto cleanup_hcd_create; - } - - err = clk_prepare_enable(tegra->clk); - if (err) - goto cleanup_hcd_create; - - err = tegra_reset_usb_controller(pdev); - if (err) { - dev_err(&pdev->dev, "Failed to reset controller\n"); - goto cleanup_clk_en; - } - - u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); - if (IS_ERR(u_phy)) { - err = -EPROBE_DEFER; - goto cleanup_clk_en; - } - hcd->usb_phy = u_phy; - hcd->skip_phy_initialization = 1; - - tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, - "nvidia,needs-double-reset"); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hcd->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(hcd->regs)) { - err = PTR_ERR(hcd->regs); - goto cleanup_clk_en; - } - hcd->rsrc_start = res->start; - hcd->rsrc_len = resource_size(res); - - ehci->caps = hcd->regs + 0x100; - ehci->has_hostpc = soc_config->has_hostpc; - - err = usb_phy_init(hcd->usb_phy); - if (err) { - dev_err(&pdev->dev, "Failed to initialize phy\n"); - goto cleanup_clk_en; - } - - u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), - GFP_KERNEL); - if (!u_phy->otg) { - err = -ENOMEM; - goto cleanup_phy; - } - u_phy->otg->host = hcd_to_bus(hcd); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - err = irq; - goto cleanup_phy; - } - - otg_set_host(u_phy->otg, &hcd->self); - - err = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (err) { - dev_err(&pdev->dev, "Failed to add USB HCD\n"); - goto cleanup_otg_set_host; - } - device_wakeup_enable(hcd->self.controller); - - return err; - -cleanup_otg_set_host: - otg_set_host(u_phy->otg, NULL); -cleanup_phy: - usb_phy_shutdown(hcd->usb_phy); -cleanup_clk_en: - clk_disable_unprepare(tegra->clk); -cleanup_hcd_create: - usb_put_hcd(hcd); - return err; -} - -static int tegra_ehci_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - struct tegra_ehci_hcd *tegra = - (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv; - - usb_remove_hcd(hcd); - otg_set_host(hcd->usb_phy->otg, NULL); - usb_phy_shutdown(hcd->usb_phy); - clk_disable_unprepare(tegra->clk); - usb_put_hcd(hcd); - - return 0; -} - -static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - - if (hcd->driver->shutdown) - hcd->driver->shutdown(hcd); -} - -static struct platform_driver tegra_ehci_driver = { - .probe = tegra_ehci_probe, - .remove = tegra_ehci_remove, - .shutdown = tegra_ehci_hcd_shutdown, - .driver = { - .name = DRV_NAME, - .of_match_table = tegra_ehci_of_match, - } -}; - -static int tegra_ehci_reset(struct usb_hcd *hcd) -{ - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - int retval; - int txfifothresh; - - retval = ehci_setup(hcd); - if (retval) - return retval; - - /* - * We should really pull this value out of tegra_ehci_soc_config, but - * to avoid needing access to it, make use of the fact that Tegra20 is - * the only one so far that needs a value of 10, and Tegra20 is the - * only one which doesn't set has_hostpc. - */ - txfifothresh = ehci->has_hostpc ? 0x10 : 10; - ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning); - - return 0; -} - -static const struct ehci_driver_overrides tegra_overrides __initconst = { - .extra_priv_size = sizeof(struct tegra_ehci_hcd), - .reset = tegra_ehci_reset, -}; - -static int __init ehci_tegra_init(void) -{ - if (usb_disabled()) - return -ENODEV; - - pr_info(DRV_NAME ": " DRIVER_DESC "\n"); - - ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides); - - /* - * The Tegra HW has some unusual quirks, which require Tegra-specific - * workarounds. We override certain hc_driver functions here to - * achieve that. We explicitly do not enhance ehci_driver_overrides to - * allow this more easily, since this is an unusual case, and we don't - * want to encourage others to override these functions by making it - * too easy. - */ - - tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma; - tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma; - tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control; - - return platform_driver_register(&tegra_ehci_driver); -} -module_init(ehci_tegra_init); - -static void __exit ehci_tegra_cleanup(void) -{ - platform_driver_unregister(&tegra_ehci_driver); -} -module_exit(ehci_tegra_cleanup); - -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:" DRV_NAME); -MODULE_DEVICE_TABLE(of, tegra_ehci_of_match); From patchwork Tue Dec 15 20:21:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 344784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69EC9C4361B for ; Tue, 15 Dec 2020 20:31:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A0CD22510 for ; Tue, 15 Dec 2020 20:31:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727884AbgLOUXu (ORCPT ); Tue, 15 Dec 2020 15:23:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727785AbgLOUXM (ORCPT ); Tue, 15 Dec 2020 15:23:12 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D54C0611CF; Tue, 15 Dec 2020 12:21:54 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id m25so42701790lfc.11; Tue, 15 Dec 2020 12:21:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NiGZvLOgQKcEvFh0a0FUmNFhvqrnqyE23ruUDRJZB2I=; b=QjcxInygzQDn5Q2Y6w1yyIP9hqWYhCCfGUb1W83mJ/+Q9j1XajUymEW5oudaawQQx3 sFiuMMVA2EbvB09FJeDuu2094e4N2OwgcjopoSObtRdOJ5ux0ozEcJsS1xCaz23axWoX LrDC/gEMFSxKR4vhI9C82VJvtM5t/YZrOGcHgjtmCdjwbjk62KXeAdFeQRVih9Xf5HtS ArCSyOwSoVyujV3IvFShs7Ac/8bEQCQH1bZhT//7nCp0KiHfBtcsVwIyzWciFkjhIqWE VizNSwRqUzgzH0Lh+JTUmaz3BV0ez2Dtc9KgzHQjnhTb5rOiTv01EKnOGd3U9Uj4+bpE sffA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NiGZvLOgQKcEvFh0a0FUmNFhvqrnqyE23ruUDRJZB2I=; b=I5QvqleGQRmCgjC1BAnT1KSybQUw3qVk/NfpvtZGkhrjVIn/XcpaIOAZXcq4oSm9Wj pqUunPI5vZ6XipfOXBaJy3Gnl5orJYjyN9HKbXWxiRUHssQ0JWLri1IyzkUSrpCOKPpr JolvIFwDC+gZbv6Mqo5ibOdWnp3eJwlObYneDgDbUQgKzRhZ9MvppHDWunSa5CuBRkXV 4tQac3Uw+kYoYeQ8DSAVE8sXTdJiFH05GvwVh+NH8vLRQcSg/RgMTC3WVm7d+TI2HJ51 okxNSX47QyAwFMXnMXDNwLVum3Px/4FzaXKJ55yX2GJ9H0pytAkYvbvtGrfQP4RltWNu b2FA== X-Gm-Message-State: AOAM533IXrtQ1kkyUhL5T8qkmZi/gXevluN6o5oNw27xcD2Lr8Qzl220 FaY4yqZE4CCRyRG3sm6CmWM= X-Google-Smtp-Source: ABdhPJzkaum52qZSSRrn3kFMmBxupTarz67eo18LBFI2iCUwfw9etjBbHdWJgNUEg8mbU5ApFg35/Q== X-Received: by 2002:a19:a0c:: with SMTP id 12mr11822065lfk.436.1608063712582; Tue, 15 Dec 2020 12:21:52 -0800 (PST) Received: from localhost.localdomain (109-252-192-57.dynamic.spd-mgts.ru. [109.252.192.57]) by smtp.gmail.com with ESMTPSA id f3sm2873711ljp.114.2020.12.15.12.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 12:21:52 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter Chen , Greg Kroah-Hartman , Alan Stern , Felipe Balbi , Matt Merhar , Nicolas Chauvet , Peter Geis Cc: linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 8/8] ARM: tegra_defconfig: Enable USB_CHIPIDEA and remove USB_EHCI_TEGRA Date: Tue, 15 Dec 2020 23:21:13 +0300 Message-Id: <20201215202113.30394-9-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215202113.30394-1-digetx@gmail.com> References: <20201215202113.30394-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The ehci-tegra driver was superseded by the generic ChipIdea USB driver, update the tegra's defconfig accordingly. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 74739a52a8ad..ae0709265493 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -237,12 +237,13 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_ACM=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_TEGRA=y CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=16