From patchwork Thu Feb 8 10:21:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 127281 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1339430ljc; Thu, 8 Feb 2018 02:21:19 -0800 (PST) X-Google-Smtp-Source: AH8x2263PaAnG30qLpqbKnzgxGcmG1RNb3qGmcZvrh7FISFyWrpVMwQTTxMoL8PY8zsQO35uDK3h X-Received: by 10.101.78.201 with SMTP id w9mr135679pgq.43.1518085279016; Thu, 08 Feb 2018 02:21:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518085279; cv=none; d=google.com; s=arc-20160816; b=Lu3pH42a7k+i4hndJw8ijoEphKBfzNdZSvNZqM/paP6gqdlx3Zmf8H/hRjYQndGaBw pg3jqjWFQhSTgwlclk7dIk7JdLx/+kRJG+mQs7HVty3bydHp9Kid6W+oFmfFcbs5WAOe 38thjCb78Yu0knm/Fh+SooSz1JHPAGR8y5VBkrcWmFV0qZQy8z/sbzcs+83StDU3OZzB vYD3BnwwybGQka3+bQoJPqT8kuKKfCg7bnuddNrs+PAzv/fVfzw9no1i/3gVETP0v6Wy 4ucM4D8qtPt+HqwXkdSlwgHt1dGv+Ic2yo1JX8fbySqKktscN2OkpTcIrXPiUc9N/naZ T+QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=Wwh6k+c32m3rR/4sg2iPWAdvJEfHbLiCkRTGvaP3nGI=; b=l5uAgBHMzC0u3XETo7RchIz64yW4mW2Z8s8W2Jd9AqWBtwTO0ahNnZ++1owaTGIu6Q tho1yxkcxBXmHuY/75iEDXitVdxz5GtzsB7qnxO2WRor//NX8qxN6fArFIvaxVAzAj0Q QbVah7HfVeMflTWRLtq7EbVLhkSYQbd73jddLIIRQFRZFZs6fzZYdD8gK95vTlcv+SJ7 /8KcOiJFwDLtrsGdHGjrKGKfzL9fcTCCv/LyKCx8KnSkEyeOHd+D8D0c77HQmwSGDi8W wD2yCR3Cj8ysenopiFe+Zy2s8VlhGGTb4G7vLnO9TDvRyWxNwIaTsKc7jQQjulZeeGwo xBuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=QIaWJ1So; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id u17-v6si1217013plj.646.2018.02.08.02.21.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 02:21:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=QIaWJ1So; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF8AC6E5BF; Thu, 8 Feb 2018 10:21:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44F2A6E5BB for ; Thu, 8 Feb 2018 10:21:15 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALCS8023324; Thu, 8 Feb 2018 04:21:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085272; bh=jD+6s7cUjInvSzdv0uGXHWSs1lBXiopZUy/lidUoRic=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QIaWJ1SoYtlQHhxXEOZbjsl9gahJ+Ygw7DP4NjBa2klLSk8rWwtaKYZEj+1DbJWFn m+0I0CnQHXr+XHHGFiMGm/khJ0dZw3FpaK9mD0uMkio+57c9lYSWY0kIxZRKC+5+Cv 8M36xq1BnwFxYOmLksfpvopIWzynQxLthE+0W1lE= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALCTg015827; Thu, 8 Feb 2018 04:21:12 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:12 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:12 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9Bv012092; Thu, 8 Feb 2018 04:21:11 -0600 From: Jyri Sarha To: Subject: [PATCH v4 1/6] drm/omap: Fail probe if irq registration fails Date: Thu, 8 Feb 2018 12:21:01 +0200 Message-ID: <802e7cedf8a697deeef3f143cc1068520b35f2f6.1518084092.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Call to omap_drm_irq_install() may fail with an error code. In such a case the driver probe should fail. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/omap_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 71ea43f..e6e7a2c 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -329,9 +329,9 @@ static int omap_modeset_init(struct drm_device *dev) drm_mode_config_reset(dev); - omap_drm_irq_install(dev); + ret = omap_drm_irq_install(dev); - return 0; + return ret; } /* From patchwork Thu Feb 8 10:21:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 127283 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1339791ljc; Thu, 8 Feb 2018 02:21:51 -0800 (PST) X-Google-Smtp-Source: AH8x224QmzuGyG1dbWodz0pMJMhSmGs/28AiWCDhBDymbLzWL/A8Gwtrq3TtQdkfhGZ9jm1W+Mea X-Received: by 2002:a17:902:8496:: with SMTP id c22-v6mr204527plo.36.1518085311095; Thu, 08 Feb 2018 02:21:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518085311; cv=none; d=google.com; s=arc-20160816; b=vnFAEfWy4eCdZgdqvgPYxvSZ4z465BysHSQ+FRRZIyIS3CCQXks5oybZgFXd7peWBs 80OaVGpsIF8jn2WwGTucAeQGYv3JnZ+LJWKmtW2/TEIzthrT2dTNPiMl4G+igBfAkbiy DEnRmP0YScJAP8ayvdIx2vJNIKC+oXtRz0BrsbsO4UGEzd3R3dYKhmg6S6KOaeLMvE0p ll6lqYV/c+3Mw2dHBp6OXhnGFQxnwsJcco5WGBcJMw6+NfxXFjUUCAYMH9FQ73lBZi8D O1FgXz1s7CPlpUsV2zmlawnA4pdRtIqSHkwON6U4TJc3xiuU18b52t65fQkhVahohhgR Gvjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=w2JU9Hquo3vCgQRjgpeWYLlZvAd06W7vGSRkvIem64c=; b=FWnTPSJpWuLnHoSHJnp+LsX6A4CglOgI5YUBx99c944qqVicrletzvHXimy8qVSylK 8OSIMOr6cCYxUepkx0Ydb8Iu5fkIMBzIX6pSRxTF3Wzzpk9iXC3IT9BrGIrpVhMMBh5I HD7/lvobG5WGMQoKzgwXE5Q5hjkZ/Ai1GrE1iiByDMNnqvcN8LX+COfNQ/chM4+5/EbD GydtCUebz+7zzhf4oW1FEOeH9ZIHGzatCfXozjoYMpH/rUZn5UEWP5hPb6zARXI6bc2K hmKsy11opd20cypU15RIo12X0Zs+o9j+Q5LDkNUpEHQlLtuNxhKfAj9XUk5DPCV8ePZf sTNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Eso5gsS9; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id q73si2614669pfj.270.2018.02.08.02.21.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 02:21:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Eso5gsS9; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F35616E5C0; Thu, 8 Feb 2018 10:21:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C19A6E5C0 for ; Thu, 8 Feb 2018 10:21:16 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALECS013775; Thu, 8 Feb 2018 04:21:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085274; bh=nZklAUGx/9amIta1wpCgkqVAauc6+OpgCKGKDwtTKe4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Eso5gsS9MW+CMxiCK5rm3WcHnNIjz+J7TijkcOi9q4Il8em5PZFcqcKdFg7CH/Mwu JNcJXaKnVdd78bZKgXp+/SmhT0qA2z7fBiqJtfxyiLul9WSOVzEufwSeQEjJr6xT+I Mj/7Tpy1njLY2wxAAEsT71Cifu3KLuGRWiwCQGec= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALEWo002926; Thu, 8 Feb 2018 04:21:14 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:13 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:13 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9Bw012092; Thu, 8 Feb 2018 04:21:12 -0600 From: Jyri Sarha To: Subject: [PATCH v4 2/6] drm/omap: Add get_ovl_name() and get_mgr_name() to dispc_ops Date: Thu, 8 Feb 2018 12:21:02 +0200 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add get_ovl_name() and get_mgr_name() to dispc_ops and get rid of adhoc names here and there in the omapdrm code. This moves the names of hardware entities to omapdss side where they have to be when new omapdss backend drivers are introduced. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/dispc.c | 21 +++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 +++ drivers/gpu/drm/omapdrm/omap_crtc.c | 11 ++--------- drivers/gpu/drm/omapdrm/omap_irq.c | 19 +++++++------------ drivers/gpu/drm/omapdrm/omap_plane.c | 13 +++---------- 5 files changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 4e8f68e..8b4814a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -680,6 +680,24 @@ void dispc_runtime_put(void) WARN_ON(r < 0 && r != -ENOSYS); } +static const char *dispc_get_ovl_name(enum omap_plane_id plane) +{ + static const char * const ovl_names[] = { + [OMAP_DSS_GFX] = "GFX", + [OMAP_DSS_VIDEO1] = "VID1", + [OMAP_DSS_VIDEO2] = "VID2", + [OMAP_DSS_VIDEO3] = "VID3", + [OMAP_DSS_WB] = "WB", + }; + + return ovl_names[plane]; +} + +static const char *dispc_get_mgr_name(enum omap_channel channel) +{ + return mgr_desc[channel].name; +} + static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) { return mgr_desc[channel].vsync_irq; @@ -4506,6 +4524,9 @@ static void dispc_errata_i734_wa(void) .get_num_ovls = dispc_get_num_ovls, .get_num_mgrs = dispc_get_num_mgrs, + .get_ovl_name = dispc_get_ovl_name, + .get_mgr_name = dispc_get_mgr_name, + .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit, .mgr_enable = dispc_mgr_enable, diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index f8f83e8..d7ed1a4 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -691,6 +691,9 @@ struct dispc_ops { int (*get_num_ovls)(void); int (*get_num_mgrs)(void); + const char *(*get_ovl_name)(enum omap_plane_id plane); + const char *(*get_mgr_name)(enum omap_channel channel); + u32 (*get_memory_bandwidth_limit)(void); void (*mgr_enable)(enum omap_channel channel, bool enable); diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 1b8154e..fee8a63 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -662,13 +662,6 @@ static void omap_crtc_reset(struct drm_crtc *crtc) * Init and Cleanup */ -static const char *channel_names[] = { - [OMAP_DSS_CHANNEL_LCD] = "lcd", - [OMAP_DSS_CHANNEL_DIGIT] = "tv", - [OMAP_DSS_CHANNEL_LCD2] = "lcd2", - [OMAP_DSS_CHANNEL_LCD3] = "lcd3", -}; - void omap_crtc_pre_init(void) { memset(omap_crtcs, 0, sizeof(omap_crtcs)); @@ -696,7 +689,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, channel = out->dispc_channel; omap_dss_put_device(out); - DBG("%s", channel_names[channel]); + DBG("%s", priv->dispc_ops->get_mgr_name(channel)); /* Multiple displays on same channel is not allowed */ if (WARN_ON(omap_crtcs[channel] != NULL)) @@ -711,7 +704,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, init_waitqueue_head(&omap_crtc->pending_wait); omap_crtc->channel = channel; - omap_crtc->name = channel_names[channel]; + omap_crtc->name = priv->dispc_ops->get_mgr_name(channel); ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, &omap_crtc_funcs, NULL); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 53ba424..b0f6850 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -144,15 +144,10 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, { static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - static const struct { - const char *name; - u32 mask; - } sources[] = { - { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, - { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, - { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, - { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, - }; + static const u32 irqbits[] = { DISPC_IRQ_GFX_FIFO_UNDERFLOW, + DISPC_IRQ_VID1_FIFO_UNDERFLOW, + DISPC_IRQ_VID2_FIFO_UNDERFLOW, + DISPC_IRQ_VID3_FIFO_UNDERFLOW }; const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | DISPC_IRQ_VID1_FIFO_UNDERFLOW @@ -172,9 +167,9 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, DRM_ERROR("FIFO underflow on "); - for (i = 0; i < ARRAY_SIZE(sources); ++i) { - if (sources[i].mask & irqstatus) - pr_cont("%s ", sources[i].name); + for (i = 0; i < ARRAY_SIZE(irqbits); ++i) { + if (irqbits[i] & irqstatus) + pr_cont("%s ", priv->dispc_ops->get_ovl_name(i)); } pr_cont("(0x%08x)\n", irqstatus); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 7d789d1..6f9d9ef 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -239,13 +239,6 @@ static int omap_plane_atomic_get_property(struct drm_plane *plane, .atomic_get_property = omap_plane_atomic_get_property, }; -static const char *plane_id_to_name[] = { - [OMAP_DSS_GFX] = "gfx", - [OMAP_DSS_VIDEO1] = "vid1", - [OMAP_DSS_VIDEO2] = "vid2", - [OMAP_DSS_VIDEO3] = "vid3", -}; - static const enum omap_plane_id plane_idx_to_id[] = { OMAP_DSS_GFX, OMAP_DSS_VIDEO1, @@ -272,7 +265,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, id = plane_idx_to_id[idx]; - DBG("%s: type=%d", plane_id_to_name[id], type); + DBG("%s: type=%d", priv->dispc_ops->get_ovl_name(id), type); omap_plane = kzalloc(sizeof(*omap_plane), GFP_KERNEL); if (!omap_plane) @@ -282,7 +275,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, for (nformats = 0; formats[nformats]; ++nformats) ; omap_plane->id = id; - omap_plane->name = plane_id_to_name[id]; + omap_plane->name = priv->dispc_ops->get_ovl_name(id); plane = &omap_plane->base; @@ -301,7 +294,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, error: dev_err(dev->dev, "%s(): could not create plane: %s\n", - __func__, plane_id_to_name[id]); + __func__, priv->dispc_ops->get_ovl_name(id)); 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[131.252.210.177]) by mx.google.com with ESMTPS id k77si816020pfj.127.2018.02.08.02.21.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 02:21:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=oqNe1hSH; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 952C36E5C1; Thu, 8 Feb 2018 10:21:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6D806E5C1 for ; Thu, 8 Feb 2018 10:21:22 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALFaj013783; Thu, 8 Feb 2018 04:21:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085275; bh=J46yC+SH4PJkK7gxmuY+xqej+oycbcRgv8djVuSKJLc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oqNe1hSHXmN+SshfwksvbO03ELY29gBaqcibcvqXGN3rg9XyryZTlfgDkyAfFjQfX 9uxASg3G8iAhor/Usc1nMEgMj+/2JA2tkhbktM82Qru2igcHFdgSHgBIXGl5zAjvA1 kJQPUjhdDW5NAQkXcC1rbeu8koF9hHTNk2fGEd80= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALFNh015866; Thu, 8 Feb 2018 04:21:15 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:14 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:14 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9Bx012092; Thu, 8 Feb 2018 04:21:13 -0600 From: Jyri Sarha To: Subject: [PATCH v4 3/6] drm/omap: Make omapdss API more generic Date: Thu, 8 Feb 2018 12:21:03 +0200 Message-ID: <5a6218a94818ad46a49895a614fc4c8d54c8dfff.1518084092.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The new omapdss API is HW independent and cleans up some of the DSS5 specific hacks from the omapdrm side and gets rid off the DSS5 IRQ register bits and replace them with HW independent generic u64 based macros. The new macros make it more straight forward to implement the IRQ code for the future DSS versions that do not share the same register structure as DSS2 to DSS5 has. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/dispc.c | 106 ++++++++++++++++++++++-------- drivers/gpu/drm/omapdrm/dss/dispc.h | 33 ++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 64 ++++++++---------- drivers/gpu/drm/omapdrm/omap_crtc.c | 16 +++-- drivers/gpu/drm/omapdrm/omap_crtc.h | 2 +- drivers/gpu/drm/omapdrm/omap_drv.h | 3 +- drivers/gpu/drm/omapdrm/omap_irq.c | 120 +++++++++++++++------------------- drivers/gpu/drm/omapdrm/omap_irq.h | 2 +- drivers/gpu/drm/omapdrm/omap_plane.c | 7 ++ drivers/gpu/drm/omapdrm/omap_plane.h | 1 + 10 files changed, 214 insertions(+), 140 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 8b4814a..2caffed 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -698,27 +698,10 @@ static const char *dispc_get_mgr_name(enum omap_channel channel) return mgr_desc[channel].name; } -static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) +static bool dispc_mgr_has_framedone(enum omap_channel channel) { - return mgr_desc[channel].vsync_irq; -} - -static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) -{ - if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) - return 0; - - return mgr_desc[channel].framedone_irq; -} - -static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) -{ - return mgr_desc[channel].sync_lost_irq; -} - -u32 dispc_wb_get_framedone_irq(void) -{ - return DISPC_IRQ_FRAMEDONEWB; + return channel != OMAP_DSS_CHANNEL_DIGIT || + !dispc.feat->no_framedone_tv; } static void dispc_mgr_enable(enum omap_channel channel, bool enable) @@ -3604,6 +3587,77 @@ static void dispc_write_irqenable(u32 mask) dispc_read_reg(DISPC_IRQENABLE); } +struct dispc_irq_bit { + u32 hw; + u64 api; +}; + +static const struct dispc_irq_bit dispc_irq_bits[] = { + { DISPC_IRQ_OCP_ERR, DSS_IRQ_DEVICE_OCP_ERR }, + + { DISPC_IRQ_FRAMEDONE, DSS_IRQ_MGR_FRAME_DONE(0) }, + { DISPC_IRQ_VSYNC, DSS_IRQ_MGR_VSYNC_EVEN(0) }, + { DISPC_IRQ_SYNC_LOST, DSS_IRQ_MGR_SYNC_LOST(0) }, + + { DISPC_IRQ_EVSYNC_EVEN, DSS_IRQ_MGR_VSYNC_EVEN(1) }, + { DISPC_IRQ_EVSYNC_ODD, DSS_IRQ_MGR_VSYNC_ODD(1) }, + { DISPC_IRQ_SYNC_LOST_DIGIT, DSS_IRQ_MGR_SYNC_LOST(1) }, + { DISPC_IRQ_FRAMEDONETV, DSS_IRQ_MGR_FRAME_DONE(1) }, + + { DISPC_IRQ_SYNC_LOST2, DSS_IRQ_MGR_SYNC_LOST(2) }, + { DISPC_IRQ_VSYNC2, DSS_IRQ_MGR_VSYNC_EVEN(2) }, + { DISPC_IRQ_FRAMEDONE2, DSS_IRQ_MGR_FRAME_DONE(2) }, + + { DISPC_IRQ_SYNC_LOST3, DSS_IRQ_MGR_SYNC_LOST(3) }, + { DISPC_IRQ_VSYNC3, DSS_IRQ_MGR_VSYNC_EVEN(3) }, + { DISPC_IRQ_FRAMEDONE3, DSS_IRQ_MGR_FRAME_DONE(3) }, + + { DISPC_IRQ_GFX_FIFO_UNDERFLOW, DSS_IRQ_OVL_FIFO_UNDERFLOW(0) }, + { DISPC_IRQ_VID1_FIFO_UNDERFLOW, DSS_IRQ_OVL_FIFO_UNDERFLOW(1) }, + { DISPC_IRQ_VID2_FIFO_UNDERFLOW, DSS_IRQ_OVL_FIFO_UNDERFLOW(2) }, + { DISPC_IRQ_VID3_FIFO_UNDERFLOW, DSS_IRQ_OVL_FIFO_UNDERFLOW(3) }, +}; + +static u64 dispc_hw_to_api_irq(u32 hw) +{ + u64 api = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(dispc_irq_bits); i++) + if (hw & dispc_irq_bits[i].hw) + api |= dispc_irq_bits[i].api; + + return api; +} + +static u32 dispc_api_to_hw_irq(u64 api) +{ + u32 hw = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(dispc_irq_bits); i++) + if (api & dispc_irq_bits[i].api) + hw |= dispc_irq_bits[i].hw; + + return hw; +} + +static u64 dispc_api_read_and_clear_irqstatus(void) +{ + u32 hw_status = dispc_read_irqstatus(); + + dispc_clear_irqstatus(hw_status); + + return dispc_hw_to_api_irq(hw_status); +} + +static void dispc_api_write_irqenable(u64 enable) +{ + u32 hw_enable = dispc_api_to_hw_irq(enable); + + dispc_write_irqenable(hw_enable); +} + void dispc_enable_sidle(void) { REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ @@ -4453,7 +4507,7 @@ static void dispc_errata_i734_wa_fini(void) static void dispc_errata_i734_wa(void) { - u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD); + u32 framedone_irq = DISPC_IRQ_FRAMEDONE; struct omap_overlay_info ovli; struct dss_lcd_mgr_config lcd_conf; u32 gatestate; @@ -4511,9 +4565,8 @@ static void dispc_errata_i734_wa(void) } static const struct dispc_ops dispc_ops = { - .read_irqstatus = dispc_read_irqstatus, - .clear_irqstatus = dispc_clear_irqstatus, - .write_irqenable = dispc_write_irqenable, + .read_and_clear_irqstatus = dispc_api_read_and_clear_irqstatus, + .write_irqenable = dispc_api_write_irqenable, .request_irq = dispc_request_irq, .free_irq = dispc_free_irq, @@ -4527,13 +4580,12 @@ static void dispc_errata_i734_wa(void) .get_ovl_name = dispc_get_ovl_name, .get_mgr_name = dispc_get_mgr_name, + .mgr_has_framedone = dispc_mgr_has_framedone, + .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit, .mgr_enable = dispc_mgr_enable, .mgr_is_enabled = dispc_mgr_is_enabled, - .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, - .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq, - .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq, .mgr_go_busy = dispc_mgr_go_busy, .mgr_go = dispc_mgr_go, .mgr_set_lcd_config = dispc_mgr_set_lcd_config, diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.h b/drivers/gpu/drm/omapdrm/dss/dispc.h index e901dd1..e71266e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.h +++ b/drivers/gpu/drm/omapdrm/dss/dispc.h @@ -18,6 +18,39 @@ #ifndef __OMAP2_DISPC_REG_H #define __OMAP2_DISPC_REG_H +/* DISPC IRQ bits */ +#define DISPC_IRQ_FRAMEDONE (1 << 0) +#define DISPC_IRQ_VSYNC (1 << 1) +#define DISPC_IRQ_EVSYNC_EVEN (1 << 2) +#define DISPC_IRQ_EVSYNC_ODD (1 << 3) +#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) +#define DISPC_IRQ_PROG_LINE_NUM (1 << 5) +#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) +#define DISPC_IRQ_GFX_END_WIN (1 << 7) +#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) +#define DISPC_IRQ_OCP_ERR (1 << 9) +#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) +#define DISPC_IRQ_VID1_END_WIN (1 << 11) +#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) +#define DISPC_IRQ_VID2_END_WIN (1 << 13) +#define DISPC_IRQ_SYNC_LOST (1 << 14) +#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) +#define DISPC_IRQ_WAKEUP (1 << 16) +#define DISPC_IRQ_SYNC_LOST2 (1 << 17) +#define DISPC_IRQ_VSYNC2 (1 << 18) +#define DISPC_IRQ_VID3_END_WIN (1 << 19) +#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) +#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) +#define DISPC_IRQ_FRAMEDONE2 (1 << 22) +#define DISPC_IRQ_FRAMEDONEWB (1 << 23) +#define DISPC_IRQ_FRAMEDONETV (1 << 24) +#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) +#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) +#define DISPC_IRQ_SYNC_LOST3 (1 << 27) +#define DISPC_IRQ_VSYNC3 (1 << 28) +#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) +#define DISPC_IRQ_FRAMEDONE3 (1 << 30) + /* DISPC common registers */ #define DISPC_REVISION 0x0000 #define DISPC_SYSCONFIG 0x0010 diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index d7ed1a4..4b2068e 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -27,37 +27,29 @@ #include #include -#define DISPC_IRQ_FRAMEDONE (1 << 0) -#define DISPC_IRQ_VSYNC (1 << 1) -#define DISPC_IRQ_EVSYNC_EVEN (1 << 2) -#define DISPC_IRQ_EVSYNC_ODD (1 << 3) -#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) -#define DISPC_IRQ_PROG_LINE_NUM (1 << 5) -#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) -#define DISPC_IRQ_GFX_END_WIN (1 << 7) -#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) -#define DISPC_IRQ_OCP_ERR (1 << 9) -#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) -#define DISPC_IRQ_VID1_END_WIN (1 << 11) -#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) -#define DISPC_IRQ_VID2_END_WIN (1 << 13) -#define DISPC_IRQ_SYNC_LOST (1 << 14) -#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) -#define DISPC_IRQ_WAKEUP (1 << 16) -#define DISPC_IRQ_SYNC_LOST2 (1 << 17) -#define DISPC_IRQ_VSYNC2 (1 << 18) -#define DISPC_IRQ_VID3_END_WIN (1 << 19) -#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) -#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) -#define DISPC_IRQ_FRAMEDONE2 (1 << 22) -#define DISPC_IRQ_FRAMEDONEWB (1 << 23) -#define DISPC_IRQ_FRAMEDONETV (1 << 24) -#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) -#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) -#define DISPC_IRQ_SYNC_LOST3 (1 << 27) -#define DISPC_IRQ_VSYNC3 (1 << 28) -#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) -#define DISPC_IRQ_FRAMEDONE3 (1 << 30) +#define DSS_MAX_CHANNELS 8 +#define DSS_MAX_OVLS 8 + +#define DSS_IRQ_DEVICE_OCP_ERR BIT_ULL(0) + +#define DSS_IRQ_MGR_BIT_N(ch, bit) (4 + 4 * ch + bit) +#define DSS_IRQ_OVL_BIT_N(ovl, bit) \ + (DSS_IRQ_MGR_BIT_N(DSS_MAX_CHANNELS, 0) + 1 * ovl + bit) + +#define DSS_IRQ_MGR_BIT(ch, bit) BIT_ULL(DSS_IRQ_MGR_BIT_N(ch, bit)) +#define DSS_IRQ_OVL_BIT(ovl, bit) BIT_ULL(DSS_IRQ_OVL_BIT_N(ovl, bit)) + +#define DSS_IRQ_MGR_MASK(ch) \ + GENMASK_ULL(DSS_IRQ_MGR_BIT_N(ch, 3), DSS_IRQ_MGR_BIT_N(ch, 0)) +#define DSS_IRQ_OVL_MASK(ovl) \ + GENMASK_ULL(DSS_IRQ_OVL_BIT_N(ovl, 0), DSS_IRQ_OVL_BIT_N(ovl, 0)) + +#define DSS_IRQ_MGR_FRAME_DONE(ch) DSS_IRQ_MGR_BIT(ch, 0) +#define DSS_IRQ_MGR_VSYNC_EVEN(ch) DSS_IRQ_MGR_BIT(ch, 1) +#define DSS_IRQ_MGR_VSYNC_ODD(ch) DSS_IRQ_MGR_BIT(ch, 2) +#define DSS_IRQ_MGR_SYNC_LOST(ch) DSS_IRQ_MGR_BIT(ch, 3) + +#define DSS_IRQ_OVL_FIFO_UNDERFLOW(ovl) DSS_IRQ_OVL_BIT(ovl, 0) struct omap_dss_device; struct dss_lcd_mgr_config; @@ -678,9 +670,8 @@ void dss_mgr_unregister_framedone_handler(enum omap_channel channel, /* dispc ops */ struct dispc_ops { - u32 (*read_irqstatus)(void); - void (*clear_irqstatus)(u32 mask); - void (*write_irqenable)(u32 mask); + u64 (*read_and_clear_irqstatus)(void); + void (*write_irqenable)(u64 enable); int (*request_irq)(irq_handler_t handler, void *dev_id); void (*free_irq)(void *dev_id); @@ -694,13 +685,12 @@ struct dispc_ops { const char *(*get_ovl_name)(enum omap_plane_id plane); const char *(*get_mgr_name)(enum omap_channel channel); + bool (*mgr_has_framedone)(enum omap_channel channel); + u32 (*get_memory_bandwidth_limit)(void); void (*mgr_enable)(enum omap_channel channel, bool enable); bool (*mgr_is_enabled)(enum omap_channel channel); - u32 (*mgr_get_vsync_irq)(enum omap_channel channel); - u32 (*mgr_get_framedone_irq)(enum omap_channel channel); - u32 (*mgr_get_sync_lost_irq)(enum omap_channel channel); bool (*mgr_go_busy)(enum omap_channel channel); void (*mgr_go)(enum omap_channel channel); void (*mgr_set_lcd_config)(enum omap_channel channel, diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index fee8a63..f7e1668 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -149,7 +149,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) struct omap_crtc *omap_crtc = to_omap_crtc(crtc); enum omap_channel channel = omap_crtc->channel; struct omap_irq_wait *wait; - u32 framedone_irq, vsync_irq; + u64 vsync_irq, framedone_irq; int ret; if (WARN_ON(omap_crtc->enabled == enable)) @@ -169,8 +169,10 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) omap_crtc->ignore_digit_sync_lost = true; } - framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel); - vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel); + + vsync_irq = (DSS_IRQ_MGR_VSYNC_EVEN(channel) | + DSS_IRQ_MGR_VSYNC_ODD(channel)); + framedone_irq = DSS_IRQ_MGR_FRAME_DONE(channel); if (enable) { wait = omap_irq_wait_init(dev, vsync_irq, 1); @@ -184,7 +186,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) * even and odd frames. */ - if (framedone_irq) + if (priv->dispc_ops->mgr_has_framedone(channel)) wait = omap_irq_wait_init(dev, framedone_irq, 1); else wait = omap_irq_wait_init(dev, vsync_irq, 2); @@ -272,17 +274,17 @@ static void omap_crtc_dss_unregister_framedone( * Setup, Flush and Page Flip */ -void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus) +void omap_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); if (omap_crtc->ignore_digit_sync_lost) { - irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; + irqstatus &= ~DSS_IRQ_MGR_SYNC_LOST(omap_crtc->channel); if (!irqstatus) return; } - DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); + DRM_ERROR_RATELIMITED("%s: errors: %016llx\n", omap_crtc->name, irqstatus); } void omap_crtc_vblank_irq(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.h b/drivers/gpu/drm/omapdrm/omap_crtc.h index ad7b007..55e2e02 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.h +++ b/drivers/gpu/drm/omapdrm/omap_crtc.h @@ -37,7 +37,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, struct drm_plane *plane, struct omap_dss_device *dssdev); int omap_crtc_wait_pending(struct drm_crtc *crtc); -void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus); +void omap_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus); void omap_crtc_vblank_irq(struct drm_crtc *crtc); #endif /* __OMAPDRM_CRTC_H__ */ diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 0ac97fe..22f88b5 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -81,7 +81,8 @@ struct omap_drm_private { /* irq handling: */ spinlock_t wait_lock; /* protects the wait_list */ struct list_head wait_list; /* list of omap_irq_wait */ - uint32_t irq_mask; /* enabled irqs in addition to wait_list */ + u64 irq_mask; /* enabled irqs in addition to wait_list */ + u64 irq_uf_mask; /* underflow irq bits for all planes */ /* memory bandwidth limit if it is needed on the platform */ unsigned int max_bandwidth; diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index b0f6850..a411ef2 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -20,25 +20,24 @@ struct omap_irq_wait { struct list_head node; wait_queue_head_t wq; - uint32_t irqmask; + u64 irqmask; int count; }; /* call with wait_lock and dispc runtime held */ -static void omap_irq_update(struct drm_device *dev) +static void omap_irq_full_mask(struct drm_device *dev, u64 *irqmask) { struct omap_drm_private *priv = dev->dev_private; struct omap_irq_wait *wait; - uint32_t irqmask = priv->irq_mask; assert_spin_locked(&priv->wait_lock); - list_for_each_entry(wait, &priv->wait_list, node) - irqmask |= wait->irqmask; + *irqmask = priv->irq_mask; - DBG("irqmask=%08x", irqmask); + list_for_each_entry(wait, &priv->wait_list, node) + *irqmask |= wait->irqmask; - priv->dispc_ops->write_irqenable(irqmask); + DBG("irqmask 0x%016llx", *irqmask); } static void omap_irq_wait_handler(struct omap_irq_wait *wait) @@ -48,19 +47,24 @@ static void omap_irq_wait_handler(struct omap_irq_wait *wait) } struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, - uint32_t irqmask, int count) + u64 waitmask, int count) { struct omap_drm_private *priv = dev->dev_private; struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); unsigned long flags; + u64 irqmask; + + if (!wait) + return NULL; init_waitqueue_head(&wait->wq); - wait->irqmask = irqmask; + wait->irqmask = waitmask; wait->count = count; spin_lock_irqsave(&priv->wait_lock, flags); list_add(&wait->node, &priv->wait_list); - omap_irq_update(dev); + omap_irq_full_mask(dev, &irqmask); + priv->dispc_ops->write_irqenable(irqmask); spin_unlock_irqrestore(&priv->wait_lock, flags); return wait; @@ -71,13 +75,15 @@ int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, { struct omap_drm_private *priv = dev->dev_private; unsigned long flags; + u64 irqmask; int ret; ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout); spin_lock_irqsave(&priv->wait_lock, flags); list_del(&wait->node); - omap_irq_update(dev); + omap_irq_full_mask(dev, &irqmask); + priv->dispc_ops->write_irqenable(irqmask); spin_unlock_irqrestore(&priv->wait_lock, flags); kfree(wait); @@ -104,12 +110,15 @@ int omap_irq_enable_vblank(struct drm_crtc *crtc) struct omap_drm_private *priv = dev->dev_private; unsigned long flags; enum omap_channel channel = omap_crtc_channel(crtc); + u64 irqmask; DBG("dev=%p, crtc=%u", dev, channel); spin_lock_irqsave(&priv->wait_lock, flags); - priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel); - omap_irq_update(dev); + priv->irq_mask |= DSS_IRQ_MGR_VSYNC_EVEN(channel) | + DSS_IRQ_MGR_VSYNC_ODD(channel); + omap_irq_full_mask(dev, &irqmask); + priv->dispc_ops->write_irqenable(irqmask); spin_unlock_irqrestore(&priv->wait_lock, flags); return 0; @@ -130,36 +139,31 @@ void omap_irq_disable_vblank(struct drm_crtc *crtc) struct omap_drm_private *priv = dev->dev_private; unsigned long flags; enum omap_channel channel = omap_crtc_channel(crtc); + u64 irqmask; DBG("dev=%p, crtc=%u", dev, channel); spin_lock_irqsave(&priv->wait_lock, flags); - priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel); - omap_irq_update(dev); + priv->irq_mask &= ~(DSS_IRQ_MGR_VSYNC_EVEN(channel) | + DSS_IRQ_MGR_VSYNC_ODD(channel)); + omap_irq_full_mask(dev, &irqmask); + priv->dispc_ops->write_irqenable(irqmask); spin_unlock_irqrestore(&priv->wait_lock, flags); } static void omap_irq_fifo_underflow(struct omap_drm_private *priv, - u32 irqstatus) + u64 irqstatus) { static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - static const u32 irqbits[] = { DISPC_IRQ_GFX_FIFO_UNDERFLOW, - DISPC_IRQ_VID1_FIFO_UNDERFLOW, - DISPC_IRQ_VID2_FIFO_UNDERFLOW, - DISPC_IRQ_VID3_FIFO_UNDERFLOW }; - - const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW - | DISPC_IRQ_VID1_FIFO_UNDERFLOW - | DISPC_IRQ_VID2_FIFO_UNDERFLOW - | DISPC_IRQ_VID3_FIFO_UNDERFLOW; unsigned int i; + u64 masked; spin_lock(&priv->wait_lock); - irqstatus &= priv->irq_mask & mask; + masked = irqstatus & priv->irq_uf_mask & priv->irq_mask; spin_unlock(&priv->wait_lock); - if (!irqstatus) + if (!masked) return; if (!__ratelimit(&_rs)) @@ -167,21 +171,19 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, DRM_ERROR("FIFO underflow on "); - for (i = 0; i < ARRAY_SIZE(irqbits); ++i) { - if (irqbits[i] & irqstatus) - pr_cont("%s ", priv->dispc_ops->get_ovl_name(i)); + for (i = 0; i < DSS_MAX_OVLS; ++i) { + if (masked & DSS_IRQ_OVL_FIFO_UNDERFLOW(i)) + pr_cont("%u:%s ", i, priv->dispc_ops->get_ovl_name(i)); } - pr_cont("(0x%08x)\n", irqstatus); + pr_cont("(%016llx)\n", irqstatus); } static void omap_irq_ocp_error_handler(struct drm_device *dev, - u32 irqstatus) + u64 irqstatus) { - if (!(irqstatus & DISPC_IRQ_OCP_ERR)) - return; - - dev_err_ratelimited(dev->dev, "OCP error\n"); + if (irqstatus & DSS_IRQ_DEVICE_OCP_ERR) + dev_err_ratelimited(dev->dev, "OCP error\n"); } static irqreturn_t omap_irq_handler(int irq, void *arg) @@ -191,24 +193,23 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) struct omap_irq_wait *wait, *n; unsigned long flags; unsigned int id; - u32 irqstatus; + u64 irqstatus; - irqstatus = priv->dispc_ops->read_irqstatus(); - priv->dispc_ops->clear_irqstatus(irqstatus); - priv->dispc_ops->read_irqstatus(); /* flush posted write */ + irqstatus = priv->dispc_ops->read_and_clear_irqstatus(); - VERB("irqs: %08x", irqstatus); + VERB("irqs: 0x%016llx\n", irqstatus); for (id = 0; id < priv->num_crtcs; id++) { struct drm_crtc *crtc = priv->crtcs[id]; enum omap_channel channel = omap_crtc_channel(crtc); - if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) { + if (irqstatus & (DSS_IRQ_MGR_VSYNC_EVEN(channel) | + DSS_IRQ_MGR_VSYNC_ODD(channel))) { drm_handle_vblank(dev, id); omap_crtc_vblank_irq(crtc); } - if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel)) + if (irqstatus & DSS_IRQ_MGR_SYNC_LOST(channel)) omap_crtc_error_irq(crtc, irqstatus); } @@ -217,7 +218,7 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) spin_lock_irqsave(&priv->wait_lock, flags); list_for_each_entry_safe(wait, n, &priv->wait_list, node) { - if (wait->irqmask & irqstatus) + if (irqstatus & wait->irqmask) omap_irq_wait_handler(wait); } spin_unlock_irqrestore(&priv->wait_lock, flags); @@ -225,13 +226,6 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -static const u32 omap_underflow_irqs[] = { - [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, - [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW, - [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW, - [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW, -}; - /* * We need a special version, instead of just using drm_irq_install(), * because we need to register the irq via omapdss. Once omapdss and @@ -242,29 +236,23 @@ static irqreturn_t omap_irq_handler(int irq, void *arg) int omap_drm_irq_install(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; - unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(); - unsigned int max_planes; unsigned int i; int ret; spin_lock_init(&priv->wait_lock); INIT_LIST_HEAD(&priv->wait_list); - priv->irq_mask = DISPC_IRQ_OCP_ERR; - - max_planes = min(ARRAY_SIZE(priv->planes), - ARRAY_SIZE(omap_underflow_irqs)); - for (i = 0; i < max_planes; ++i) { - if (priv->planes[i]) - priv->irq_mask |= omap_underflow_irqs[i]; - } + priv->irq_mask = DSS_IRQ_DEVICE_OCP_ERR; - for (i = 0; i < num_mgrs; ++i) - priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i); + priv->irq_uf_mask = 0; + for (i = 0; i < priv->num_planes; ++i) + priv->irq_uf_mask |= DSS_IRQ_OVL_FIFO_UNDERFLOW( + omap_plane_get_id(priv->planes[i])); + priv->irq_mask |= priv->irq_uf_mask; - priv->dispc_ops->runtime_get(); - priv->dispc_ops->clear_irqstatus(0xffffffff); - priv->dispc_ops->runtime_put(); + for (i = 0; i < priv->num_crtcs; ++i) + priv->irq_mask |= DSS_IRQ_MGR_SYNC_LOST( + omap_crtc_channel(priv->crtcs[i])); ret = priv->dispc_ops->request_irq(omap_irq_handler, dev); if (ret < 0) diff --git a/drivers/gpu/drm/omapdrm/omap_irq.h b/drivers/gpu/drm/omapdrm/omap_irq.h index 606c099..8a7971d 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.h +++ b/drivers/gpu/drm/omapdrm/omap_irq.h @@ -32,7 +32,7 @@ int omap_drm_irq_install(struct drm_device *dev); struct omap_irq_wait *omap_irq_wait_init(struct drm_device *dev, - uint32_t irqmask, int count); + u64 irqmask, int count); int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, unsigned long timeout); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 6f9d9ef..0040d29 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -239,6 +239,13 @@ static int omap_plane_atomic_get_property(struct drm_plane *plane, .atomic_get_property = omap_plane_atomic_get_property, }; +enum omap_plane_id omap_plane_get_id(struct drm_plane *plane) +{ + struct omap_plane *omap_plane = to_omap_plane(plane); + + return omap_plane->id; +} + static const enum omap_plane_id plane_idx_to_id[] = { OMAP_DSS_GFX, OMAP_DSS_VIDEO1, diff --git a/drivers/gpu/drm/omapdrm/omap_plane.h b/drivers/gpu/drm/omapdrm/omap_plane.h index dc5e82a..dbab345 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.h +++ b/drivers/gpu/drm/omapdrm/omap_plane.h @@ -33,5 +33,6 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, u32 possible_crtcs); void omap_plane_install_properties(struct drm_plane *plane, struct drm_mode_object *obj); +enum omap_plane_id omap_plane_get_id(struct drm_plane *plane); #endif /* __OMAPDRM_PLANE_H__ */ From patchwork Thu Feb 8 10:21:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 127665 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1444569ljc; Thu, 8 Feb 2018 04:38:21 -0800 (PST) X-Google-Smtp-Source: AH8x22760Brtd+GH+HyEpkib99A9nj2PBKKZe3MBK2QWG45tp1vY4fwtoXwXVux8L0hu/+HGapMf X-Received: by 10.99.114.71 with SMTP id c7mr413668pgn.283.1518093500968; Thu, 08 Feb 2018 04:38:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518093500; cv=none; d=google.com; s=arc-20160816; b=ww6alfMSGsND5N27m64OHyobUPCiYCapgDSI13LgzUN+Lee6HUMv6xTeBQCDaBlPji vxW+ql2OgxuV4FHcZRicRzupzXkMl78RtnqFfWdALtWRuElTyQolWmyJ5uh+JhBVo2yI 4WO9K6JVzVkiKreO6BoJdbY9TuW2CQ0iG+oFYK64eXJ7778Gh0vi7KaH6P5u/8cTVGaw Oq5O0hZWHdRolksCev7DF0v7vQjNnCvHBHzM/wGj3Xya2KCn3ezPdPB1PKeff/AQ6rWY EHbZpCeI+EE9uhuTB+Ci1MjPVeu0wCaMqvzsS2PnIu5xEuhot7psjoA4QsacbIm90IkB 3sAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=AGqer2HIoE/0/FHiRXHs9gYkFAaDHdFhsFOYQNzcVC4=; b=Htks54VPzxV+c/m/ShxzFGSV4MD5nWe3EFbKkWcxLO/hzIsRMi7ZqrZWSb5tSOK+yp x5AJq+xPQMPa6RJQgZa9phRJae2RW8zi/PrxHds9GBG7C8Q3zsgOy/z4isgVCEo2OBaw XAjIlH84uAmlUEBKYypNIBq3tBazUAFowsTFXMHMhNlXF3a5WfImovQhca3LAOE6bUi3 iPTD9s7WGwSt1EuEa8FStKGumQxFvuC2ephLfpKgrdTSqka3FnlYZU5K8n8h/hgWcJmj Lc6V1qzicXyjFAm/Eygq3MgXqhid0Wr11kfWVP5LEDzlwRYUbDEVZdGS51j9IaFJWQar 8BYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b+dVm2SH; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id a5-v6si2710949plp.416.2018.02.08.04.38.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 04:38:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b+dVm2SH; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E78846E608; Thu, 8 Feb 2018 12:37:47 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B20D6E605 for ; Thu, 8 Feb 2018 12:37:45 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALG9p011009; Thu, 8 Feb 2018 04:21:16 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085276; bh=4ER3JWyEvIT3zlMkal45rQWHMxIc1UVKI7D0mKWa6Ps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b+dVm2SHUg/MR7kEiUmA9qs2Mc1FBFzr1TM0wS6OMA+mYJ1oIbe46d129+pa29oQy OAO7cs5hq7Goae5OmJ0l5k4ZEtFWKhHzyoVLGcXTw5BGpF7qgA413hY6FN91arnEut jgnAPqDlSUS8Jx1zT78e+NAaDsiy7hp+w9hxzyd0= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALGiM015881; Thu, 8 Feb 2018 04:21:16 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:16 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:16 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9C0012092; Thu, 8 Feb 2018 04:21:15 -0600 From: Jyri Sarha To: Subject: [PATCH v4 4/6] drm/omap: move common stuff from dss.h to omapdss.h Date: Thu, 8 Feb 2018 12:21:04 +0200 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tomi Valkeinen The new DSS6 driver needs some structs and defines which are currently in dss.h, which is for the old DSS driver. Move the required structs and defines from dss.h to omapdss.h. Signed-off-by: Tomi Valkeinen Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/dss.h | 37 ----------------------------------- drivers/gpu/drm/omapdrm/dss/omapdss.h | 37 +++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 6374e57e..7347cb9 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -65,14 +65,6 @@ pr_warn("omapdss: " format, ##__VA_ARGS__) #endif -/* OMAP TRM gives bitfields as start:end, where start is the higher bit - number. For example 7:0 */ -#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) -#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) -#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) -#define FLD_MOD(orig, val, start, end) \ - (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) - enum dss_model { DSS_MODEL_OMAP2, DSS_MODEL_OMAP3, @@ -81,12 +73,6 @@ enum dss_model { DSS_MODEL_DRA7, }; -enum dss_io_pad_mode { - DSS_IO_PAD_MODE_RESET, - DSS_IO_PAD_MODE_RFBI, - DSS_IO_PAD_MODE_BYPASS, -}; - enum dss_hdmi_venc_clk_source_select { DSS_VENC_TV_CLK = 0, DSS_HDMI_M_PCLK = 1, @@ -209,29 +195,6 @@ struct dss_reg_field { u8 start, end; }; -struct dispc_clock_info { - /* rates that we get with dividers below */ - unsigned long lck; - unsigned long pck; - - /* dividers */ - u16 lck_div; - u16 pck_div; -}; - -struct dss_lcd_mgr_config { - enum dss_io_pad_mode io_pad_mode; - - bool stallmode; - bool fifohandcheck; - - struct dispc_clock_info clock_info; - - int video_port_width; - - int lcden_sig_polarity; -}; - struct seq_file; struct platform_device; diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 4b2068e..8395d5b 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -624,6 +624,43 @@ static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) struct omap_dss_device * omapdss_of_find_source_for_first_ep(struct device_node *node); +/* OMAP TRM gives bitfields as start:end, where start is the higher bit + number. For example 7:0 */ +#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) +#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) +#define FLD_MOD(orig, val, start, end) \ + (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) + +enum dss_io_pad_mode { + DSS_IO_PAD_MODE_RESET, + DSS_IO_PAD_MODE_RFBI, + DSS_IO_PAD_MODE_BYPASS, +}; + +struct dispc_clock_info { + /* rates that we get with dividers below */ + unsigned long lck; + unsigned long pck; + + /* dividers */ + u16 lck_div; + u16 pck_div; +}; + +struct dss_lcd_mgr_config { + enum dss_io_pad_mode io_pad_mode; + + bool stallmode; + bool fifohandcheck; + + struct dispc_clock_info clock_info; + + int video_port_width; + + int lcden_sig_polarity; +}; + void omapdss_set_is_initialized(bool set); struct device_node *dss_of_port_get_parent_device(struct device_node *port); From patchwork Thu Feb 8 10:21:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 127664 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1444530ljc; Thu, 8 Feb 2018 04:38:18 -0800 (PST) X-Google-Smtp-Source: AH8x224mrzCeEdigatGj6HMNgP9md3cIxCZr9C+iWUA0S7Mg06oeUrmydmZxZVRZS5yJ6mfYwNDc X-Received: by 10.98.9.67 with SMTP id e64mr572049pfd.230.1518093498584; Thu, 08 Feb 2018 04:38:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518093498; cv=none; d=google.com; s=arc-20160816; b=J2qYqy9NiNuXrvAuFfQU22BGYJSJqkz19pDnPpHuk+MfyTzsrKMSuo/AzahHkQoevF +AOcZVLUGLA9fKfGkGWVUzNqfohDnSCOV3IZ0x7JDcJ4/n7B5OT4ZAgLYXUvPIKb+j2p X++d+VcuFhSrUMxopeoIR7TXLnnL4J8n8NZdTyZtdySK0S7YeFK12eDCXmWTBg8WgDvh +kkk5Vcp2Hd7zOP/eBMaoGMIcC62aJ8Ne4Hz4JS0Qd4PqZGDCvY/bBEt6GLPhD3KeJur VZAumvqw3+0TFJ5rivKNdkN19iEwKHCTXf8V/N1CiSy64+j8/5hnXWabbiAbfenEXD3/ AE9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=UczPLYdIMV+tT98AVuSbfdqiWDilmkoJ7I2yRf9trI4=; b=zLReSPBdZGWU2ChPwR2e48N+bqmvt56/1XDR5q9hJGCg3QupUZy0lG+HQtQcLjXymt RcQs2HOnWBiU4TEuXC/Ec75q63wTwYl9tKiiZoRWKwsiTGhVPmDPzTLewJzbh13tGETO vY2T7dcj7RLuE1rUwlx+O5q/tuCjyBSmclhmDXw9pae+j+Bltb5zGwUPCyvjOFfHuU4k 4H88dbScpYHrETyGkBMxFyAnfeHO588P+rNgRDhsAa8InobdRIwJ+2ZhoNlaGpabjiGs WX78rLtGQ0JMruWxBlq4MffrNo5OWPOq23cuJUHF+z2FKpi11SbeTme+vyPOIBbg95mw wkYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=pWe3F3Ww; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id i5-v6si1500330plr.335.2018.02.08.04.38.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 04:38:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=pWe3F3Ww; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C8F26E605; Thu, 8 Feb 2018 12:37:46 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 452B86E605 for ; Thu, 8 Feb 2018 12:37:45 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALIml011017; Thu, 8 Feb 2018 04:21:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085278; bh=CxFPzyothIvAw/Z2DeKxzp2s5DATZ5erSBU32RAQJsc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pWe3F3WwAEDRV8uumasNNeNHCVNeJBuXLmaq0wnfsboj9cHFFGslTngMlrB9NsAyb 364bam+3tltxeLs9WvNZbd5/3Lw38PO7ZZT0LR6WS7ky6kM7lZ5M3pUsmX1fm16kpg JklfOrZDZLS5zK3ViFw7QcrpmkP9qc6gzJhtnq0Y= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALIEJ002962; Thu, 8 Feb 2018 04:21:18 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:17 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:17 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9C1012092; Thu, 8 Feb 2018 04:21:16 -0600 From: Jyri Sarha To: Subject: [PATCH v4 5/6] drm/omap: dss: Move platform_device_register from core.c to dss.c probe Date: Thu, 8 Feb 2018 12:21:05 +0200 Message-ID: <60fa139e76020d244f0a4d5bd9807201a91d1f85.1518084092.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Register the omapdrm device when we know that dss device probe going to succeed. This avoids DSS6 and DSS2 omapdrm device registration from colliding with each other. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/core.c | 26 ++------------------------ drivers/gpu/drm/omapdrm/dss/dss.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/core.c b/drivers/gpu/drm/omapdrm/dss/core.c index acef7ec..6c9f667 100644 --- a/drivers/gpu/drm/omapdrm/dss/core.c +++ b/drivers/gpu/drm/omapdrm/dss/core.c @@ -45,36 +45,14 @@ #endif }; -static struct platform_device *omap_drm_device; - static int __init omap_dss_init(void) { - int r; - - r = platform_register_drivers(omap_dss_drivers, - ARRAY_SIZE(omap_dss_drivers)); - if (r) - goto err_reg; - - omap_drm_device = platform_device_register_simple("omapdrm", 0, NULL, 0); - if (IS_ERR(omap_drm_device)) { - r = PTR_ERR(omap_drm_device); - goto err_reg; - } - - return 0; - -err_reg: - platform_unregister_drivers(omap_dss_drivers, - ARRAY_SIZE(omap_dss_drivers)); - - return r; + return platform_register_drivers(omap_dss_drivers, + ARRAY_SIZE(omap_dss_drivers)); } static void __exit omap_dss_exit(void) { - platform_device_unregister(omap_drm_device); - platform_unregister_drivers(omap_dss_drivers, ARRAY_SIZE(omap_dss_drivers)); } diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 04300b2..3cfe4a7 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -1298,6 +1298,17 @@ static int dss_video_pll_probe(struct platform_device *pdev) { /* sentinel */ } }; +static struct platform_device *omap_drm_device = NULL; + +static int initialize_omapdrm_device(void) +{ + omap_drm_device = platform_device_register_simple("omapdrm", 0, NULL, 0); + if (IS_ERR(omap_drm_device)) + return PTR_ERR(omap_drm_device); + + return 0; +} + static int dss_bind(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -1359,6 +1370,10 @@ static int dss_bind(struct device *dev) if (r) goto err_component; + r = initialize_omapdrm_device(); + if (r) + goto err_omapdrm_device; + dss_debugfs_create_file("dss", dss_dump_regs); pm_set_vt_switch(0); @@ -1368,6 +1383,8 @@ static int dss_bind(struct device *dev) return 0; +err_omapdrm_device: + component_unbind_all(&pdev->dev, NULL); err_component: err_runtime_get: pm_runtime_disable(&pdev->dev); @@ -1390,6 +1407,8 @@ static void dss_unbind(struct device *dev) omapdss_set_is_initialized(false); + platform_device_unregister(omap_drm_device); + component_unbind_all(&pdev->dev, NULL); if (dss.video1_pll) From patchwork Thu Feb 8 10:21:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 127282 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1339481ljc; Thu, 8 Feb 2018 02:21:24 -0800 (PST) X-Google-Smtp-Source: AH8x224yIwG+jeXWcJOV6lyupoaw0/6HNO3gmCtglZecRcU0Gj7/7wDEVcawUWv/zsuGFc2h78zE X-Received: by 10.99.183.15 with SMTP id t15mr141094pgf.416.1518085284157; Thu, 08 Feb 2018 02:21:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518085284; cv=none; d=google.com; s=arc-20160816; b=sCLCZ8MKIUAxmyCVlVQNKyh7yz/hkicnVeQY3SULU+P/RKtQx5hCOVJVPjh93UXvDV ZzFTDD+SewnTrteJrwwa6SHlrjiF09J15fCDU1Ac39hHB/VNHdgdPm9fc64+3WSJvrgN NgZnmS4AI7eyyD+yndzfMLz0QxYcQXhxVQdWMd7nwt3/69jC6YskVD0fhqdxmJMHWdUM 9YiI+mlJFkCN9zqy2ch2z6HoVsJ283IiOFkHzcqHdb7N6I2Je7c+ssZ3Y0ystJg+SpFX MrJ5i53s5FGJQbwZjguseRtIrY7sK+RfI4mNn03TtQZX4sHtJilPpk7Q/4LGjNXExdRI 5XjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=R/xOz3O0Op0xt4qcaAWYo8hWn+a5FlrHbOizy5CNLBs=; b=Lk3PX3XGCI+/tSH3UPYf5jz3HJqGzC4mTD6VFBRPXdpKmrzwKqOQ6Xy7gx7cvFiTi8 Ab01s6sFW8ERNoA1k8JZ3qwy/XhaepdagbiCCSguMyDqETbVDI8yANfEhQu6moUrpmdn x6h9siQek/0Om32H8u/wpbGUCcgB+uY5fVyuKch8lrcVGycgRUKuwL6UtgNh62QP5csE DavzIMGxzbVXteYs+Mut9duMTkhbB/bdpMsa31TYBxtxnVoBv75iPZ6Sk6c0HoyW8QEH NDhjA+auRwWj7/Bcb3gD2VdVuKPhndkgkLJZj07Z4uKkTuy5qKj0leq6s44RMjJXxjVF U+iQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=TBsiQhpk; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id l8si1078355pgs.148.2018.02.08.02.21.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 02:21:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=TBsiQhpk; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 161F36E5C2; Thu, 8 Feb 2018 10:21:23 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by gabe.freedesktop.org (Postfix) with ESMTPS id A55116E5C1 for ; Thu, 8 Feb 2018 10:21:21 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w18ALJEO013792; Thu, 8 Feb 2018 04:21:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518085279; bh=oeU0IZcnw4kFgs9SsFclh5oD52GXCev4K9NUjyQtgaA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TBsiQhpkTboOSYT7drEsz/sppiGdKHlGwksvQhbJguRTbtVDm0bQpnswIf/TN5uGs cwDsDOuO2MoIPPvEl6LW10ox2hKgwZysSoJ40z0FaOHqbarT/vE2tmSZZIw6yyrIOZ NfKcjvLlDinz9bMVd5KrvLLkKhIF8qhsWPDlwpoA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18ALJUd002976; Thu, 8 Feb 2018 04:21:19 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 8 Feb 2018 04:21:18 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 8 Feb 2018 04:21:18 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w18AL9C2012092; Thu, 8 Feb 2018 04:21:17 -0600 From: Jyri Sarha To: Subject: [PATCH v4 6/6] drm/omap: dss: platform_register_drivers() to dss.c and remove core.c Date: Thu, 8 Feb 2018 12:21:06 +0200 Message-ID: <0205b9bfacc97245e7cded87cfa2b8762f9210cd.1518084092.git.jsarha@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The core.c just for registering the drivers is kind of useless. Let's get rid of it and register the dss drivers in dss.c. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/omapdrm/dss/Makefile | 2 +- drivers/gpu/drm/omapdrm/dss/core.c | 66 ------------------------------------ drivers/gpu/drm/omapdrm/dss/dss.c | 37 ++++++++++++++++++++ 3 files changed, 38 insertions(+), 67 deletions(-) delete mode 100644 drivers/gpu/drm/omapdrm/dss/core.c diff --git a/drivers/gpu/drm/omapdrm/dss/Makefile b/drivers/gpu/drm/omapdrm/dss/Makefile index 904101c..5950c3f 100644 --- a/drivers/gpu/drm/omapdrm/dss/Makefile +++ b/drivers/gpu/drm/omapdrm/dss/Makefile @@ -6,7 +6,7 @@ omapdss-base-y := base.o display.o dss-of.o output.o obj-$(CONFIG_OMAP2_DSS) += omapdss.o # Core DSS files -omapdss-y := core.o dss.o dispc.o dispc_coefs.o \ +omapdss-y := dss.o dispc.o dispc_coefs.o \ pll.o video-pll.o omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o diff --git a/drivers/gpu/drm/omapdrm/dss/core.c b/drivers/gpu/drm/omapdrm/dss/core.c deleted file mode 100644 index 6c9f667..0000000 --- a/drivers/gpu/drm/omapdrm/dss/core.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen - * - * Some code and ideas taken from drivers/video/omap/ driver - * by Imre Deak. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#define DSS_SUBSYS_NAME "CORE" - -#include -#include -#include - -#include "omapdss.h" -#include "dss.h" - -/* INIT */ -static struct platform_driver * const omap_dss_drivers[] = { - &omap_dsshw_driver, - &omap_dispchw_driver, -#ifdef CONFIG_OMAP2_DSS_DSI - &omap_dsihw_driver, -#endif -#ifdef CONFIG_OMAP2_DSS_VENC - &omap_venchw_driver, -#endif -#ifdef CONFIG_OMAP4_DSS_HDMI - &omapdss_hdmi4hw_driver, -#endif -#ifdef CONFIG_OMAP5_DSS_HDMI - &omapdss_hdmi5hw_driver, -#endif -}; - -static int __init omap_dss_init(void) -{ - return platform_register_drivers(omap_dss_drivers, - ARRAY_SIZE(omap_dss_drivers)); -} - -static void __exit omap_dss_exit(void) -{ - platform_unregister_drivers(omap_dss_drivers, - ARRAY_SIZE(omap_dss_drivers)); -} - -module_init(omap_dss_init); -module_exit(omap_dss_exit); - -MODULE_AUTHOR("Tomi Valkeinen "); -MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); -MODULE_LICENSE("GPL v2"); - diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 3cfe4a7..701f49b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -1564,3 +1564,40 @@ struct platform_driver omap_dsshw_driver = { .suppress_bind_attrs = true, }, }; + +/* INIT */ +static struct platform_driver * const omap_dss_drivers[] = { + &omap_dsshw_driver, + &omap_dispchw_driver, +#ifdef CONFIG_OMAP2_DSS_DSI + &omap_dsihw_driver, +#endif +#ifdef CONFIG_OMAP2_DSS_VENC + &omap_venchw_driver, +#endif +#ifdef CONFIG_OMAP4_DSS_HDMI + &omapdss_hdmi4hw_driver, +#endif +#ifdef CONFIG_OMAP5_DSS_HDMI + &omapdss_hdmi5hw_driver, +#endif +}; + +static int __init omap_dss_init(void) +{ + return platform_register_drivers(omap_dss_drivers, + ARRAY_SIZE(omap_dss_drivers)); +} + +static void __exit omap_dss_exit(void) +{ + platform_unregister_drivers(omap_dss_drivers, + ARRAY_SIZE(omap_dss_drivers)); +} + +module_init(omap_dss_init); +module_exit(omap_dss_exit); + +MODULE_AUTHOR("Tomi Valkeinen "); +MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); +MODULE_LICENSE("GPL v2");