From patchwork Fri Mar 24 08:24:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 95925 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1128371qgd; Fri, 24 Mar 2017 01:26:27 -0700 (PDT) X-Received: by 10.99.107.72 with SMTP id g69mr7582792pgc.149.1490343987735; Fri, 24 Mar 2017 01:26:27 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u27si1289549pfa.27.2017.03.24.01.26.27; Fri, 24 Mar 2017 01:26:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751584AbdCXIYj (ORCPT + 9 others); Fri, 24 Mar 2017 04:24:39 -0400 Received: from mail-lf0-f54.google.com ([209.85.215.54]:36324 "EHLO mail-lf0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751477AbdCXIYd (ORCPT ); Fri, 24 Mar 2017 04:24:33 -0400 Received: by mail-lf0-f54.google.com with SMTP id y193so2772246lfd.3 for ; Fri, 24 Mar 2017 01:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=CwrvpyvsFNAf5cJefRsEe5QZ9LcNUDdMljnzuHKCjpU=; b=d+ma/iNDJ/VNcIwFbZ9ZYzZ79hq1oMtYVKrpPHSZLdMXqbfieIjr2m91y8NSt5jdAF Cw71bH/ya3ogmCQlLRk6Z8/wD2nbg6vKQIlAsO7WBwQ1NyD/r/RFu8hhBkqlJal87gIw SExU2Ef6sui+t9D+B1UWYzAXHF4wOutzvUGkk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=CwrvpyvsFNAf5cJefRsEe5QZ9LcNUDdMljnzuHKCjpU=; b=Sg4GFnF1QrfxAgBAc/qHPg4+hnzP9AQHo5ClRdwxf9JlqiGOCvgjoI+2cZKBMMvGRV u6fFK/535YGw/8PA8cnkWaawELxw2UPyhXThewV9Y+SFT5httcQ7v01kh69zbR6RK8ZY EaIMTbxDp5WXFjrcHYhhUI+PHYH/Ag+0W+KVWlknyBKzSj0XJ88EkkPLFsl3jwRazcTS gyjueQjmc6TErKnXuQ9KcBnD+tPl+Iitq9HeejGA7PYsZY+ktLzbnxHHht69soJsOlwo 8Mk8An8CS+IB502ulg2IBuQfxS9Je+1gf90VOfb5EYBmsWvILWXep2dFeJGFgJicGLRc /VRQ== X-Gm-Message-State: AFeK/H1qYsHXvSAqa2wMOOE8u+CiBqWDsp6sgGFQvJ33dwnEDdwBTrL9w+Y1sm53KFHS74Lh X-Received: by 10.25.201.74 with SMTP id z71mr3589997lff.108.1490343870793; Fri, 24 Mar 2017 01:24:30 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id g70sm237669lfg.3.2017.03.24.01.24.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Mar 2017 01:24:29 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 1/2] clk: qcom: Update DT bindings for MSM8660 LCC Date: Fri, 24 Mar 2017 09:24:24 +0100 Message-Id: <20170324082424.6143-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds the right compatible string and header for the MSM8660 LCC and some new defines to the dt-bindings header. Take this opportunity to spell out the acronym LPASS for Low-power Audio Subsystem. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/clock/qcom,lcc.txt | 5 +-- include/dt-bindings/clock/qcom,lcc-msm8660.h | 40 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,lcc-msm8660.h -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt index a3c78aa88038..4de51df37f1a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.txt @@ -1,10 +1,11 @@ -Qualcomm LPASS Clock & Reset Controller Binding ------------------------------------------------- +Qualcomm Low-power Audio Subsystem (LPASS) Clock & Reset Controller Binding +--------------------------------------------------------------------------- Required properties : - compatible : shall contain only one of the following: "qcom,lcc-msm8960" + "qcom,lcc-msm8660" "qcom,lcc-apq8064" "qcom,lcc-ipq8064" "qcom,lcc-mdm9615" diff --git a/include/dt-bindings/clock/qcom,lcc-msm8660.h b/include/dt-bindings/clock/qcom,lcc-msm8660.h new file mode 100644 index 000000000000..7cddcbd6b1ee --- /dev/null +++ b/include/dt-bindings/clock/qcom,lcc-msm8660.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017 Linus Walleij + * Qualcomm MSM8660 Low-power Audio Subsystem (LPASS) Clock Controller + * devicetree definitions + */ + +#ifndef _DT_BINDINGS_CLK_LCC_MSM8660_H +#define _DT_BINDINGS_CLK_LCC_MSM8660_H + +#define LPA_PLL0 0 +#define MI2S_OSR_SRC 1 +#define MI2S_OSR_CLK 2 +#define MI2S_DIV_CLK 3 +#define MI2S_BIT_DIV_CLK 4 +#define MI2S_BIT_CLK 5 +#define CODEC_I2S_MIC_OSR_SRC 6 +#define CODEC_I2S_MIC_OSR_CLK 7 +#define CODEC_I2S_MIC_DIV_CLK 8 +#define CODEC_I2S_MIC_BIT_DIV_CLK 9 +#define CODEC_I2S_MIC_BIT_CLK 10 +#define SPARE_I2S_MIC_OSR_SRC 11 +#define SPARE_I2S_MIC_OSR_CLK 12 +#define SPARE_I2S_MIC_DIV_CLK 13 +#define SPARE_I2S_MIC_BIT_DIV_CLK 14 +#define SPARE_I2S_MIC_BIT_CLK 15 +#define CODEC_I2S_SPKR_OSR_SRC 16 +#define CODEC_I2S_SPKR_OSR_CLK 17 +#define CODEC_I2S_SPKR_DIV_CLK 18 +#define CODEC_I2S_SPKR_BIT_DIV_CLK 19 +#define CODEC_I2S_SPKR_BIT_CLK 20 +#define SPARE_I2S_SPKR_OSR_SRC 21 +#define SPARE_I2S_SPKR_OSR_CLK 22 +#define SPARE_I2S_SPKR_DIV_CLK 23 +#define SPARE_I2S_SPKR_BIT_DIV_CLK 24 +#define SPARE_I2S_SPKR_BIT_CLK 25 +#define PCM_SRC 26 +#define PCM_CLK_OUT 27 +#define PCM_CLK 28 + +#endif