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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/43] tcg: Do not flush icache for interpreter Date: Mon, 14 Dec 2020 08:02:32 -0600 Message-Id: <20201214140314.18544-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is currently a no-op within tci/tcg-target.h, but is about to be moved to a more generic location. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/tcg.c b/tcg/tcg.c index 43c6cf8f52..3b3f366acd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1077,7 +1077,9 @@ void tcg_prologue_init(TCGContext *s) #endif buf1 = s->code_ptr; +#ifndef CONFIG_TCG_INTERPRETER flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); +#endif /* Deduct the prologue from the buffer. */ prologue_size = tcg_current_code_size(s); @@ -4319,8 +4321,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -2; } +#ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); +#endif return tcg_current_code_size(s); } From patchwork Mon Dec 14 14:02:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343501 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3021652jai; Mon, 14 Dec 2020 06:05:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJw6875531P8eqQoBPPF7nPyb/lHBNhTUiHZVx9W8rypLhnJSzI86K90mENJPfftYYb/CD6C X-Received: by 2002:a25:a4ca:: with SMTP id g68mr35920309ybi.359.1607954708481; Mon, 14 Dec 2020 06:05:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954708; cv=none; d=google.com; s=arc-20160816; b=ppuauEjJbMvFa1ApkwX403WQABBVS7TNZ4mFKql+OdF2GXBL5qCyJh/QckFV0SvRIU pNmoQyoYwjKWPpE6D7Hu/6yDDaVvyvRVDPrNePEMdjpDYq9F5a6I2phcU4P1crlqSwdJ o4oI/0Er4X72LnSQ501cXKLruAn65bBXzZ4V34DDU7iLU3pIazadxz+AoSy1F7L7Ivt1 Zj23fI4kPqVtKQn5JMVL6Lc9wmQKeMsME6mD5szdijLxJhaw3dlT8vPwYKzY668Zc9WM IOOhlYQq34pM2cqBjbNAr9WNTSRPij3364ipNMIY3lVeh49xUK5tlvMj52z9XQj1utzB 8kcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eOSyuirsXar+NqX//DtRTIYo0GnDDZiWnjXVEGBW7Sk=; b=TfdPeCilK5nohL+bKKKcnHpls96X+F2BTK0mRsfSvaH1wR5l6TygKQynrZ+4eDy4Rz tOa8onYdqehGCCO2l5F4ifeRwTi8gFKG2k7btAl2BiVm3wHOAt5lAOPODP7ZBnZFQQwE CKzuFiv+OVeqeFFNkgbseFb9Lmlvs+6cNYmw3mjySu3hxAcW2WWB19j5Pvdt3Hb+PJ1+ TJoCshoFz58YsU3+fOnXwI+quIabOvoNWrEiybv2o0SbbS/pkqeJh5B3/R59B+LKf9VT 1SLxIgzWWNRonWalf9NA4K8QEq8fO3F/1BGtoQrzFVvFE40L7JKzWDrsLbxA6frZ7gbh sq0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A1CANqEF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/43] util: Extract flush_icache_range to cacheflush.c Date: Mon, 14 Dec 2020 08:02:33 -0600 Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson --- include/qemu/cacheflush.h | 24 +++++++++++++ tcg/aarch64/tcg-target.h | 5 --- tcg/arm/tcg-target.h | 5 --- tcg/i386/tcg-target.h | 4 --- tcg/mips/tcg-target.h | 11 ------ tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 5 --- tcg/s390/tcg-target.h | 4 --- tcg/sparc/tcg-target.h | 8 ----- tcg/tci/tcg-target.h | 4 --- softmmu/physmem.c | 1 + tcg/tcg.c | 1 + util/cacheflush.c | 71 +++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 ++ tcg/ppc/tcg-target.c.inc | 22 ------------ util/meson.build | 2 +- 16 files changed, 100 insertions(+), 70 deletions(-) create mode 100644 include/qemu/cacheflush.h create mode 100644 util/cacheflush.c -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h new file mode 100644 index 0000000000..58ae488491 --- /dev/null +++ b/include/qemu/cacheflush.h @@ -0,0 +1,24 @@ +/* + * Flush the host cpu caches. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_CACHEFLUSH_H +#define QEMU_CACHEFLUSH_H + +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) + +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + /* icache is coherent and does not require flushing. */ +} + +#else + +void flush_icache_range(uintptr_t start, uintptr_t stop); + +#endif + +#endif /* QEMU_CACHEFLUSH_H */ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..8a6b97598e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -148,11 +148,6 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..f1955ce4ac 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,11 +134,6 @@ enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *) start, (char *) stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..cd067e0b30 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -206,10 +206,6 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..92c1d63da3 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -198,20 +198,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif -#ifdef __OpenBSD__ -#include -#else -#include -#endif - #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - cacheflush ((void *)start, stop-start, ICACHE); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..a509a19628 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -175,7 +175,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 -void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..c1bd52bb9a 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -159,11 +159,6 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #endif -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..b4feb2f55a 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -145,10 +145,6 @@ enum { TCG_AREG0 = TCG_REG_R10, }; -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..d8b0e32e2e 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,14 +168,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p; - for (p = start & -8; p < ((stop + 7) & -8); p += 8) { - __asm__ __volatile__("flush\t%0" : : "r" (p)); - } -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..b84480f989 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -191,10 +191,6 @@ void tci_disas(uint8_t opc); #define HAVE_TCG_QEMU_TB_EXEC -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. We prefer consistency across hosts on this. */ diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 3027747c03..36854f0cd0 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qemu/cutils.h" +#include "qemu/cacheflush.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/target_page.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 3b3f366acd..4b4cafe952 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -35,6 +35,7 @@ #include "qemu/host-utils.h" #include "qemu/qemu-print.h" #include "qemu/timer.h" +#include "qemu/cacheflush.h" /* Note: the long term plan is to reduce the dependencies on the QEMU CPU definitions. Currently they are used for qemu_ld/st diff --git a/util/cacheflush.c b/util/cacheflush.c new file mode 100644 index 0000000000..2881832a38 --- /dev/null +++ b/util/cacheflush.c @@ -0,0 +1,71 @@ +/* + * Flush the host cpu caches. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/cacheflush.h" + + +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) + +/* Caches are coherent and do not require flushing; symbol inline. */ + +#elif defined(__mips__) + +#ifdef __OpenBSD__ +#include +#else +#include +#endif + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + cacheflush((void *)start, stop - start, ICACHE); +} + +#elif defined(__powerpc__) + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p, start1, stop1; + size_t dsize = qemu_dcache_linesize; + size_t isize = qemu_icache_linesize; + + start1 = start & ~(dsize - 1); + stop1 = (stop + dsize - 1) & ~(dsize - 1); + for (p = start1; p < stop1; p += dsize) { + asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + + start &= start & ~(isize - 1); + stop1 = (stop + isize - 1) & ~(isize - 1); + for (p = start1; p < stop1; p += isize) { + asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + asm volatile ("isync" : : : "memory"); +} + +#elif defined(__sparc__) + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p; + + for (p = start & -8; p < ((stop + 7) & -8); p += 8) { + __asm__ __volatile__("flush\t%0" : : "r" (p)); + } +} + +#else + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + __builtin___clear_cache((char *)start, (char *)stop); +} + +#endif diff --git a/MAINTAINERS b/MAINTAINERS index d48a4e8a8b..2e23a93fec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -119,6 +119,8 @@ F: softmmu/cpus.c F: cpus-common.c F: accel/tcg/ F: accel/stubs/tcg-stub.c +F: util/cacheinfo.c +F: util/cacheflush.c F: scripts/decodetree.py F: docs/devel/decodetree.rst F: include/exec/cpu*.h diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..0d068ec8ab 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3863,25 +3863,3 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } #endif /* __ELF__ */ - -void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p, start1, stop1; - size_t dsize = qemu_dcache_linesize; - size_t isize = qemu_icache_linesize; - - start1 = start & ~(dsize - 1); - stop1 = (stop + dsize - 1) & ~(dsize - 1); - for (p = start1; p < stop1; p += dsize) { - asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - - start &= start & ~(isize - 1); - stop1 = (stop + isize - 1) & ~(isize - 1); - for (p = start1; p < stop1; p += isize) { - asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - asm volatile ("isync" : : : "memory"); -} diff --git a/util/meson.build b/util/meson.build index f359af0d46..a3dfc0f966 100644 --- a/util/meson.build +++ b/util/meson.build @@ -21,7 +21,7 @@ util_ss.add(files('envlist.c', 'path.c', 'module.c')) util_ss.add(files('host-utils.c')) util_ss.add(files('bitmap.c', 'bitops.c')) util_ss.add(files('fifo8.c')) -util_ss.add(files('cacheinfo.c')) +util_ss.add(files('cacheinfo.c', 'cacheflush.c')) util_ss.add(files('error.c', 'qemu-error.c')) util_ss.add(files('qemu-print.c')) util_ss.add(files('id.c')) From patchwork Mon Dec 14 14:02:34 2020 Content-Type: text/plain; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/43] util: Enhance flush_icache_range with separate data pointer Date: Mon, 14 Dec 2020 08:02:34 -0600 Message-Id: <20201214140314.18544-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/cacheflush.h | 15 ++++++++++++-- softmmu/physmem.c | 2 +- tcg/tcg.c | 6 ++++-- util/cacheflush.c | 38 +++++++++++++++++++++--------------- util/cacheinfo.c | 8 +++++--- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 4 ++-- tcg/sparc/tcg-target.c.inc | 4 ++-- 9 files changed, 51 insertions(+), 30 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h index 58ae488491..ae20bcda73 100644 --- a/include/qemu/cacheflush.h +++ b/include/qemu/cacheflush.h @@ -8,16 +8,27 @@ #ifndef QEMU_CACHEFLUSH_H #define QEMU_CACHEFLUSH_H +/** + * flush_idcache_range: + * @rx: instruction address + * @rw: data address + * @len: length to flush + * + * Flush @len bytes of the data cache at @rw and the icache at @rx + * to bring them in sync. The two addresses may be different virtual + * mappings of the same physical page(s). + */ + #if defined(__i386__) || defined(__x86_64__) || defined(__s390__) -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { /* icache is coherent and does not require flushing. */ } #else -void flush_icache_range(uintptr_t start, uintptr_t stop); +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len); #endif diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 36854f0cd0..7aa706b1e3 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -2947,7 +2947,7 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, invalidate_and_set_dirty(mr, addr1, l); break; case FLUSH_CACHE: - flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l); + flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); break; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 4b4cafe952..675334e844 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1079,7 +1079,8 @@ void tcg_prologue_init(TCGContext *s) buf1 = s->code_ptr; #ifndef CONFIG_TCG_INTERPRETER - flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); + flush_idcache_range((uintptr_t)buf0, (uintptr_t)buf0, + tcg_ptr_byte_diff(buf1, buf0)); #endif /* Deduct the prologue from the buffer. */ @@ -4324,7 +4325,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ - flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); + flush_idcache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_buf, + tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); #endif return tcg_current_code_size(s); diff --git a/util/cacheflush.c b/util/cacheflush.c index 2881832a38..92805efe49 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -21,29 +21,32 @@ #include #endif -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - cacheflush((void *)start, stop - start, ICACHE); + if (rx != rw) { + cacheflush((void *)rw, len, DCACHE); + } + cacheflush((void *)rx, len, ICACHE); } #elif defined(__powerpc__) -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - uintptr_t p, start1, stop1; + uintptr_t p, b, e; size_t dsize = qemu_dcache_linesize; size_t isize = qemu_icache_linesize; - start1 = start & ~(dsize - 1); - stop1 = (stop + dsize - 1) & ~(dsize - 1); - for (p = start1; p < stop1; p += dsize) { + b = rw & ~(dsize - 1); + e = (rw + len + dsize - 1) & ~(dsize - 1); + for (p = b; p < e; p += dsize) { asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); } asm volatile ("sync" : : : "memory"); - start &= start & ~(isize - 1); - stop1 = (stop + isize - 1) & ~(isize - 1); - for (p = start1; p < stop1; p += isize) { + b = rx & ~(isize - 1); + e = (rx + len + isize - 1) & ~(isize - 1); + for (p = b; p < e; p += isize) { asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); } asm volatile ("sync" : : : "memory"); @@ -52,20 +55,23 @@ void flush_icache_range(uintptr_t start, uintptr_t stop) #elif defined(__sparc__) -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - uintptr_t p; - - for (p = start & -8; p < ((stop + 7) & -8); p += 8) { + /* No additional data flush to the RW virtual address required. */ + uintptr_t p, end = (rx + len + 7) & -8; + for (p = rx & -8; p < end; p += 8) { __asm__ __volatile__("flush\t%0" : : "r" (p)); } } #else -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - __builtin___clear_cache((char *)start, (char *)stop); + if (rw != rx) { + __builtin___clear_cache((char *)rw, (char *)rw + len); + } + __builtin___clear_cache((char *)rx, (char *)rx + len); } #endif diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 7804c186b6..b182f0b693 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -166,9 +166,11 @@ static void fallback_cache_info(int *isize, int *dsize) *isize = *dsize; } else { #if defined(_ARCH_PPC) - /* For PPC, we're going to use the icache size computed for - flush_icache_range. Which means that we must use the - architecture minimum. */ + /* + * For PPC, we're going to use the cache sizes computed for + * flush_idcache_range. Which means that we must use the + * architecture minimum. + */ *isize = *dsize = 16; #else /* Otherwise, 64 bytes is not uncommon. */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..83af3108a4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1363,7 +1363,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } pair = (uint64_t)i2 << 32 | i1; qatomic_set((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..c255ecb444 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2660,7 +2660,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); } typedef struct { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 0d068ec8ab..b756281042 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1753,12 +1753,12 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, /* As per the enclosing if, this is ppc64. Avoid the _Static_assert within qatomic_set that would fail to build a ppc32 host. */ qatomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } else { intptr_t diff = addr - jmp_addr; tcg_debug_assert(in_range_b(diff)); qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); } } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..6e2d755f6a 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1836,7 +1836,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, if (!USE_REG_TB) { qatomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); return; } @@ -1860,5 +1860,5 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } From patchwork Mon Dec 14 14:02:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343503 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3024469jai; Mon, 14 Dec 2020 06:07:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxmUJ0oQYwFw1g4n+PF7d12WTHG/WY5HgMSRiXWVOsoZqMkfbmJnUDQCJ5ciT4iYpXmzNJH X-Received: by 2002:a6b:7f0b:: with SMTP id l11mr31958748ioq.34.1607954876530; Mon, 14 Dec 2020 06:07:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954876; cv=none; d=google.com; s=arc-20160816; b=YsZtZqUghdQJSWMe5ri+Rp003jBrrvvV7MfbbFwJkGa9v2nTQ7EkaPDQAGS+jz3rFe mKaHrwaA3xkJQE8BK/vBRKzkBivM5DV7eDBoFXecwQwSw3RlIaa5+uuF5FNz/3975Gn1 4X5xOd0RDrkPf0W51qjF39YkS2ELXwr7L0O4XfJqP4I+oExs6PEb13u0HfA5r5fbqPVz c9vF6jjp5sU2Tw+/Etd24WmjGJJoHBSOLm/kbDM/7jld2sEIRlz5tORyAalXYrThMlZA 4Qm7+RXdkLlV4irWRO3BH4v/avEq/P9mpSjq7mqlIUuIz1NFBRpa+4ArCN96AuKT1luV lN0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OCpAIDmNxfXuUcIom3vUf6VIYVS6wp4D0QytQgRfHqY=; b=YesEZSzooDhFROJqOpyLct95br3j6LX2O+nyGZ/CO5SITXji//w20IEtpzsxhJQHi4 olu9487KNIfCu/4GggN6nECGOCTpxz7/bbOGT7GJm7FwpfUAUR/lgYrSjIIGIi8EtbVB pZCpx5Gr2M2LyoGbCG4xfS0dZjtpGSUqeGrE+kcolr89JBbf3520x/AoUmAKzwvSuIqh K7NIicBhW7qk4n/YmINP+AJO8ce4jEillemYbJmwdtBIjrMSI0iRwocc5RRyLvN2kBhq VxKePTSuPpoUtLoUMFdc8PbApepchurkcIKknSB5rNz8F5upaUxdeFL1ZIBz5JN+fXe0 LgXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kbYbAaJT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/43] util: Specialize flush_idcache_range for aarch64 Date: Mon, 14 Dec 2020 08:02:35 -0600 Message-Id: <20201214140314.18544-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For darwin, the CTR_EL0 register is not accessible, but there are system routines that we can use. For other hosts, copy the single pointer implementation from libgcc and modify it to support the double pointer interface we require. This halves the number of cache operations required when split-rwx is enabled. Cc: Joelle van Dyne Signed-off-by: Richard Henderson --- util/cacheflush.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/util/cacheflush.c b/util/cacheflush.c index 92805efe49..6a20723902 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -7,12 +7,81 @@ #include "qemu/osdep.h" #include "qemu/cacheflush.h" +#include "qemu/bitops.h" #if defined(__i386__) || defined(__x86_64__) || defined(__s390__) /* Caches are coherent and do not require flushing; symbol inline. */ +#elif defined(__aarch64__) + +#ifdef CONFIG_DARWIN +/* Apple does not expose CTR_EL0, so we must use system interfaces. */ +extern void sys_icache_invalidate(void *start, size_t len); +extern void sys_dcache_flush(void *start, size_t len); +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) +{ + sys_dcache_flush((void *)rw, len); + sys_icache_invalidate((void *)rx, len); +} +#else + +/* + * TODO: unify this with cacheinfo.c. + * We want to save the whole contents of CTR_EL0, so that we + * have more than the linesize, but also IDC and DIC. + */ +static unsigned int save_ctr_el0; +static void __attribute__((constructor)) init_ctr_el0(void) +{ + asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); +} + +/* + * This is a copy of gcc's __aarch64_sync_cache_range, modified + * to fit this three-operand interface. + */ +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) +{ + const unsigned CTR_IDC = 1u << 28; + const unsigned CTR_DIC = 1u << 29; + const unsigned int ctr_el0 = save_ctr_el0; + const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4); + const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4); + uintptr_t p; + + /* + * If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification + * is not required for instruction to data coherence. + */ + if (!(ctr_el0 & CTR_IDC)) { + /* + * Loop over the address range, clearing one cache line at once. + * Data cache must be flushed to unification first to make sure + * the instruction cache fetches the updated data. + */ + for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) { + asm volatile("dc\tcvau, %0" : : "r" (p) : "memory"); + } + asm volatile("dsb\tish" : : : "memory"); + } + + /* + * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point + * of Unification is not required for instruction to data coherence. + */ + if (!(ctr_el0 & CTR_DIC)) { + for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) { + asm volatile("ic\tivau, %0" : : "r"(p) : "memory"); + } + asm volatile ("dsb\tish" : : : "memory"); + } + + asm volatile("isb" : : : "memory"); +} +#endif /* CONFIG_DARWIN */ + #elif defined(__mips__) #ifdef __OpenBSD__ From patchwork Mon Dec 14 14:02:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343499 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3020786jai; Mon, 14 Dec 2020 06:04:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJyNNReX5SINxspFLHsU27aIiqywl2HtS2WsY084rMDaaMgyI6yaGWhNceFNHci9Ly36Qzse X-Received: by 2002:a5b:404:: with SMTP id m4mr7750221ybp.436.1607954653900; Mon, 14 Dec 2020 06:04:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954653; cv=none; d=google.com; s=arc-20160816; b=LsApocE4XuHmamwI9Xp5RvZjKHtB2hrjkbcXPEE+W5nDarCqT12qXUfhk53hte75Bo Y7P7A6eybu9vF+KSaH4LhmpdpJ0/Hfu0KIoRcBo5D6pGpvvuCK11h53F3sRvHzvRKyjM /3iTsxPRT/W5iv+IqTm9STK2ICC/FHtOX4Ih6bDIJiCE8AHfvXCY2nuHweWUZwE30gVQ TY5YCenglIUISN1Z/JM4q7FyUURP/UgolJFFqKw50XhjewE7uUmM3pktIpyjzjbOi/bl nsy/usj1MdPTrT3ol2F4bJP63v16JbYWwW8V70UV+/iBnVqt9oGdbLUQvvpD93rTF05T xyVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e4GkJv76UBMIB3dzCCmxjxbYnphaAHyABGBMlwHa+9g=; b=clb91dV15UcV1jZ220yp1cNB/Lq3mwbKtaAyRoy9K2sDeauTXxbVhPhdoVov/UwGK1 bZ3kVivnA8ofZqqX+8yBPfSCvS6Bs8y2Hygi/5TyK1uwiHjEXrLmJMw4b25S5Cz4mpxL vdVut67/+sz2iB8509UrtINWmCLksxXvw2DanHOa7jr1oZQlahWDTOISv7yLjEX2uGNf wDBjEHGFBWFCYsm9RWvOlKUmR7uqZjYZkfZ08S0Q56U5gSYHLAD+gAldBIN3bfOPt/Bc tKUKMtbCSpUoHlAS2CT5Pq0kKU1oFT5cD0SIZogrwnSP6UndMn2WKU8YIW2tTcH5t8wE nWmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e6qb9pB8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/43] tcg: Move tcg prologue pointer out of TCGContext Date: Mon, 14 Dec 2020 08:02:36 -0600 Message-Id: <20201214140314.18544-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::344; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Use the correct function pointer type, and name the variable tcg_qemu_tb_exec, which means that we are able to remove the macro that does the casting. Replace HAVE_TCG_QEMU_TB_EXEC with CONFIG_TCG_INTERPRETER, as this is somewhat clearer in intent. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 9 ++++----- tcg/tcg.c | 9 ++++++++- tcg/tci.c | 3 ++- 3 files changed, 14 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8ff9dad4ef..9cc412f90c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -621,7 +621,6 @@ struct TCGContext { here, because there's too much arithmetic throughout that relies on addition and subtraction working on bytes. Rely on the GCC extension that allows arithmetic on void*. */ - void *code_gen_prologue; void *code_gen_epilogue; void *code_gen_buffer; size_t code_gen_buffer_size; @@ -1222,11 +1221,11 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) #define TB_EXIT_IDXMAX 1 #define TB_EXIT_REQUESTED 3 -#ifdef HAVE_TCG_QEMU_TB_EXEC -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); +#ifdef CONFIG_TCG_INTERPRETER +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *tb_ptr); #else -# define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr) +typedef uintptr_t tcg_prologue_fn(CPUArchState *env, void *tb_ptr); +extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif void tcg_register_jit(void *buf, size_t buf_size); diff --git a/tcg/tcg.c b/tcg/tcg.c index 675334e844..67065c2ede 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -162,6 +162,10 @@ static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; +#ifndef CONFIG_TCG_INTERPRETER +tcg_prologue_fn *tcg_qemu_tb_exec; +#endif + struct tcg_region_tree { QemuMutex lock; GTree *tree; @@ -1055,7 +1059,10 @@ void tcg_prologue_init(TCGContext *s) s->code_ptr = buf0; s->code_buf = buf0; s->data_gen_ptr = NULL; - s->code_gen_prologue = buf0; + +#ifndef CONFIG_TCG_INTERPRETER + tcg_qemu_tb_exec = (tcg_prologue_fn *)buf0; +#endif /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger diff --git a/tcg/tci.c b/tcg/tci.c index 82039fd163..d996eb7cf8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -475,8 +475,9 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) #endif /* Interpret pseudo code in tb. */ -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *v_tb_ptr) { + uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); From patchwork Mon Dec 14 14:02:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343507 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3027289jai; Mon, 14 Dec 2020 06:10:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJxt0sjGWMGrxrYzLNbbZ4B7fJtCeNeTQTQj3hNWeRdirfRXTNEvcQSiAH+A54rgFlmPl58U X-Received: by 2002:a25:9887:: with SMTP id l7mr37856414ybo.319.1607955040862; Mon, 14 Dec 2020 06:10:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955040; cv=none; d=google.com; s=arc-20160816; b=JLyVtql2xo5KE16+ieWF17nPIeoh25f4/ldfolZJDj0ggqSh/Yjw1ayJcrdPZcO9Ut /IrccnleG1Kq4tB1mgJ9egKsllQ1DH1EMScaDASjMnEUtizLHWjXYiKnb6wd7lsGzsl9 pt9xtj9uLrKTbWyx/DIsHrdzvFM9m/4D2e1pmYAZedjaBldqgc3aC2dkowQPoaVptrJ6 tQ2TXDqANdSDUoUWImnKtb17ZZnWZ+O4eQWEZIC/RZQVDf44cnGZJ1DIRM9AAzd4UbEP MNR8Fn2EcbtE21/DGjMIXb3mnu9eo/AQ76u6aA71pXZMeaVrNSlRY1PePq35CfNxWHKy 0k9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Caod8Myfn6UMAwpFdXVp68OknFB2PbyNlugc5dGMlp0=; b=CFdWzrAgedgyWu6dj6uINsWPLnOBnZPvp+9GopoPRk3HLBOBruknb25BhQDyMm/+Pt ob8tASdadpQ4GhN7dRpSAUbHxO4ODwymX5h9uJwuTPtGJAGGws14mYQciTag8etBPGiT 3zLAXUskTgwgf+dBS+/ShcYzqZ0tffCSfrznvZCDbBGHQG5Gh810TrkQMkjQCyZF3yds EHi7FmIWsJ+WBeH+ZwM+hiIdDObfR8jkfM5bSacAIqaDetWFXvv1SJDYwy0/kDQfPjLw laVC/gE5+I27buqTtHFmaOmpyQOFsH0UlKruHH2DUmo2RvEQD8dopfD8U2uMkzIXyWAC 9dlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dFl8rFP7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/43] tcg: Move tcg epilogue pointer out of TCGContext Date: Mon, 14 Dec 2020 08:02:37 -0600 Message-Id: <20201214140314.18544-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- accel/tcg/tcg-runtime.c | 2 +- tcg/tcg.c | 3 ++- tcg/aarch64/tcg-target.c.inc | 4 ++-- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 4 ++-- tcg/s390/tcg-target.c.inc | 4 ++-- tcg/sparc/tcg-target.c.inc | 2 +- 11 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9cc412f90c..bb1e97b13b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -621,7 +621,6 @@ struct TCGContext { here, because there's too much arithmetic throughout that relies on addition and subtraction working on bytes. Rely on the GCC extension that allows arithmetic on void*. */ - void *code_gen_epilogue; void *code_gen_buffer; size_t code_gen_buffer_size; void *code_gen_ptr; @@ -678,6 +677,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; +extern void *tcg_code_gen_epilogue; extern TCGv_env cpu_env; static inline size_t temp_idx(TCGTemp *ts) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 446465a09a..f85dfefeab 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -154,7 +154,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb == NULL) { - return tcg_ctx->code_gen_epilogue; + return tcg_code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %d: %p [" diff --git a/tcg/tcg.c b/tcg/tcg.c index 67065c2ede..588686617d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -161,6 +161,7 @@ static int tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; +void *tcg_code_gen_epilogue; #ifndef CONFIG_TCG_INTERPRETER tcg_prologue_fn *tcg_qemu_tb_exec; @@ -1133,7 +1134,7 @@ void tcg_prologue_init(TCGContext *s) /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { - tcg_debug_assert(s->code_gen_epilogue != NULL); + tcg_debug_assert(tcg_code_gen_epilogue != NULL); } } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 83af3108a4..76f8ae48ad 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1873,7 +1873,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_goto_long(s, s->code_gen_epilogue); + tcg_out_goto_long(s, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); tcg_out_goto_long(s, tb_ret_addr); @@ -2894,7 +2894,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..1e32bf42b8 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2297,7 +2297,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..424dd1cdcf 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2267,7 +2267,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_jmp(s, s->code_gen_epilogue); + tcg_out_jmp(s, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); tcg_out_jmp(s, tb_ret_addr); @@ -3825,7 +3825,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c255ecb444..f641105f9a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2483,7 +2483,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b756281042..15d5c78798 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2341,7 +2341,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - s->code_gen_epilogue = tb_ret_addr = s->code_ptr; + tcg_code_gen_epilogue = tb_ret_addr = s->code_ptr; tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..ab08af7457 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1288,7 +1288,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_call_int(s, s->code_gen_epilogue, true); + tcg_out_call_int(s, tcg_code_gen_epilogue, true); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); tcg_out_call_int(s, tb_ret_addr, true); @@ -1822,7 +1822,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..ac99ccea73 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1756,7 +1756,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Reuse the zeroing that exists for goto_ptr. */ a0 = args[0]; if (a0 == 0) { - tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue); + tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); @@ -2561,7 +2561,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6e2d755f6a..5b3bc91b05 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1038,7 +1038,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); From patchwork Mon Dec 14 14:02:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343513 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3030369jai; Mon, 14 Dec 2020 06:13:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOXJhpiwWP273ofcBZxwqLFV2U2jGosIZWL6lAOXr5Aum1YJH2/WGowiGTA3PRk0QYdc9n X-Received: by 2002:a25:38c1:: with SMTP id f184mr34681830yba.41.1607955225093; Mon, 14 Dec 2020 06:13:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955225; cv=none; d=google.com; s=arc-20160816; b=IS5BpgbUQhHkYRxDfl6AQ35FQ75OOreivxDFOOfcQeZZnVslIDYncJ2oQbI7LsdrIq FOomjusbkuCUD8cHHsxXYFOd02LvW1apcAjc9NbfZZfdV2sRG+TjuSzM8wnNVkvRPqPA x101MGnjyT+G4GgQEQ4aRTn2Z9EfBygKITqt49CghapxC6SojEPbOjqUMIW3NpISYmqP Y0CAhgX2LX1lgkU+lI6DGljV8RorelfRU/HhRM/ECFmAjjTdfkkjuqzi5fGJfE4xP/dA jfHh2puvHQIA7gRA9X9U5b8HuohN7JPgwWDqpzbFDufQ2jMoquUgUFDIMzK2G0qgnrc9 ZFnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kjsZwqo16wWQgyXnGfAD2sB/J/+jiHAWTHwjAIw7NfU=; b=eGC/YTFmC1c22SXo+XsIXPZhDluzvLraPLlMDC+rtiIY3tK6qCgDAnKa/wb2ytZeEB emJKUxm5Rg/pDhxe9pc2g7wn7BSdLJLbCYoGiowAZroqmVYiKcUMx3kdzQhdEhY1GjxL VKfegHDDa9z+Z0q4f/An9w8s9MnA2mWnv1Ue9XKlAPCHP4zDrbSk/RL5YSAqGnYgnAwO GG4Ewhgi6WMg5z+uHvD6XqJJYzaQKm7D3elm8G/GVuVjHKIomxE8ztjG4GEJjqM0gitk DTx7ghfxfGIndgMGsgN+OdncjmUqC5RbvdDA8I9c5i8kGBu6fw2SbzVjjuRk8E1Sw4m5 EsDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rxipfw7P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/43] tcg: Add in_code_gen_buffer Date: Mon, 14 Dec 2020 08:02:38 -0600 Message-Id: <20201214140314.18544-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to determine if a pointer is within the buffer. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 6 ++++++ accel/tcg/translate-all.c | 26 ++++++++------------------ 2 files changed, 14 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index bb1e97b13b..e4d0ace44b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -680,6 +680,12 @@ extern __thread TCGContext *tcg_ctx; extern void *tcg_code_gen_epilogue; extern TCGv_env cpu_env; +static inline bool in_code_gen_buffer(const void *p) +{ + const TCGContext *s = &tcg_init_ctx; + return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; +} + static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n = ts - tcg_ctx->temps; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4572b4901f..744f97a717 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -392,27 +392,18 @@ void tb_destroy(TranslationBlock *tb) bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) { - TranslationBlock *tb; - bool r = false; - uintptr_t check_offset; - - /* The host_pc has to be in the region of current code buffer. If - * it is not we will not be able to resolve it here. The two cases - * where host_pc will not be correct are: + /* + * The host_pc has to be in the region of the code buffer. + * If it is not we will not be able to resolve it here. + * The two cases where host_pc will not be correct are: * * - fault during translation (instruction fetch) * - fault from helper (not using GETPC() macro) * * Either way we need return early as we can't resolve it here. - * - * We are using unsigned arithmetic so if host_pc < - * tcg_init_ctx.code_gen_buffer check_offset will wrap to way - * above the code_gen_buffer_size */ - check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; - - if (check_offset < tcg_init_ctx.code_gen_buffer_size) { - tb = tcg_tb_lookup(host_pc); + if (in_code_gen_buffer((const void *)host_pc)) { + TranslationBlock *tb = tcg_tb_lookup(host_pc); if (tb) { cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); if (tb_cflags(tb) & CF_NOCACHE) { @@ -421,11 +412,10 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) tcg_tb_remove(tb); tb_destroy(tb); } - r = true; + return true; } } - - return r; + return false; } static void page_init(void) From patchwork Mon Dec 14 14:02:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343511 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3029952jai; Mon, 14 Dec 2020 06:13:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJxpxJ6LAIAtGMgGJkaoQIu9HlhTFRRv505vlo5saqZDSpTfqMwHe5K9ccLKXdTQ0XvZHBaj X-Received: by 2002:a67:ca0d:: with SMTP id z13mr2756915vsk.32.1607955198221; Mon, 14 Dec 2020 06:13:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955198; cv=none; d=google.com; s=arc-20160816; b=pSc+uhsi3yJffjW9WIGzM5BqXWPChvngpjh7/+Dbg0jVR6mz8OMsmgHeL8PZ6SwSbp VLtwNIuweVdpZjh2wJM7dV4buM2faPTQ4sWBiLPgcHyoiaYX4/q80O1tkpgUbGB2NhnC bf7dkAz6wUg/qfWEm5aTzZ0MUxX8c5F3dK9ONjXG7FuHJ/SegjGx7blrIwmMmRGSEXej a4n0xngfs6aZxK0E32wfGBYxtT6RmzULl9b7W05iJKwuOQ2ksbuYclRapIjgG/f2qRfc 7DORvsfEBa0C2EpRKM5/rvZvstELZsVQhAlqN9gdiAQOG3lRFmahrKxLr0D7vzIiHfzP vnBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QypuJA60qQZAogzP9afzyC3XdL/acRRoiwUGlGjqcCU=; b=mHHDMlK1NBXnBlhs5iibkWKaWD9EbH2Tt8qH2tM1uQc8UqeZiY8v3oZEluZLQKKwUF O3NAfhnDZJXZ0whGTAZhAK/dA2aM762k+b081eEUzaRhOzEq6S6O6+c6CYA1OX5GlfP6 VwchXOdSa3A1/o0lZWhCn/Ry1jLjFOji7VdoHLjILvhKieP40cVHy9O/qoUVcsw7lxvf NsSMLaaeTQPB0PcaTteAUbV0L1zzAaL3Q1qh1lGV+euRg7yb2hRAFr59HAmGLd6uVlHu PAWXFe5tZ30QaKqGKkg+S1BiFvYIEY/cEwvZP/jO5IMJ5yVDOaytdomZ0rAuU5n07ZK/ fcFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V+Xs3cu5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/43] tcg: Introduce tcg_splitwx_to_{rx,rw} Date: Mon, 14 Dec 2020 08:02:39 -0600 Message-Id: <20201214140314.18544-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c42; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc42.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour. Begin using the functions in tcg common code only. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- include/disas/disas.h | 2 +- include/exec/exec-all.h | 2 +- include/exec/log.h | 2 +- include/tcg/tcg.h | 26 ++++++++++++++---- accel/tcg/cpu-exec.c | 2 +- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 33 +++++++++++------------ disas.c | 4 ++- tcg/tcg.c | 56 ++++++++++++++++++++++++++++++++++----- tcg/tci.c | 5 ++-- accel/tcg/trace-events | 2 +- tcg/tcg-pool.c.inc | 6 ++++- 13 files changed, 104 insertions(+), 40 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 4eda24e63a..c276c8beb5 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, cptr, env) DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) diff --git a/include/disas/disas.h b/include/disas/disas.h index 36c33f6f19..d363e95ede 100644 --- a/include/disas/disas.h +++ b/include/disas/disas.h @@ -7,7 +7,7 @@ #include "cpu.h" /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, void *code, unsigned long size); +void disas(FILE *out, const void *code, unsigned long size); void target_disas(FILE *out, CPUState *cpu, target_ulong code, target_ulong size); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 94fe05daaa..d2325a5834 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -448,7 +448,7 @@ int probe_access_flags(CPUArchState *env, target_ulong addr, * Note: the address of search data can be obtained by adding @size to @ptr. */ struct tb_tc { - void *ptr; /* pointer to the translated code */ + const void *ptr; /* pointer to the translated code */ size_t size; }; diff --git a/include/exec/log.h b/include/exec/log.h index e02fff5de1..3c7fa65ead 100644 --- a/include/exec/log.h +++ b/include/exec/log.h @@ -56,7 +56,7 @@ static inline void log_target_disas(CPUState *cpu, target_ulong start, rcu_read_unlock(); } -static inline void log_disas(void *code, unsigned long size) +static inline void log_disas(const void *code, unsigned long size) { QemuLogFile *logfile; rcu_read_lock(); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e4d0ace44b..249f83be72 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -678,6 +678,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern void *tcg_code_gen_epilogue; +extern uintptr_t tcg_splitwx_diff; extern TCGv_env cpu_env; static inline bool in_code_gen_buffer(const void *p) @@ -686,6 +687,21 @@ static inline bool in_code_gen_buffer(const void *p) return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; } +#ifdef CONFIG_DEBUG_TCG +const void *tcg_splitwx_to_rx(void *rw); +void *tcg_splitwx_to_rw(const void *rx); +#else +static inline const void *tcg_splitwx_to_rx(void *rw) +{ + return rw ? rw + tcg_splitwx_diff : NULL; +} + +static inline void *tcg_splitwx_to_rw(const void *rx) +{ + return rx ? (void *)rx - tcg_splitwx_diff : NULL; +} +#endif + static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n = ts - tcg_ctx->temps; @@ -1106,7 +1122,7 @@ static inline TCGLabel *arg_label(TCGArg i) * correct result. */ -static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) +static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) { return a - b; } @@ -1120,9 +1136,9 @@ static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) * to the destination address. */ -static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) +static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) { - return tcg_ptr_byte_diff(target, s->code_ptr); + return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); } /** @@ -1228,9 +1244,9 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) #define TB_EXIT_REQUESTED 3 #ifdef CONFIG_TCG_INTERPRETER -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *tb_ptr); +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); #else -typedef uintptr_t tcg_prologue_fn(CPUArchState *env, void *tb_ptr); +typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 58aea605d8..1e3cb570f6 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,7 +150,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr = itb->tc.ptr; + const void *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %d: %p [" diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index f85dfefeab..d736f4ff55 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -145,7 +145,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } -void *HELPER(lookup_tb_ptr)(CPUArchState *env) +const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu = env_cpu(env); TranslationBlock *tb; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 744f97a717..7b85ddacd2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -269,9 +269,9 @@ static uint8_t *encode_sleb128(uint8_t *p, target_long val) /* Decode a signed leb128 sequence at *PP; increment *PP past the decoded value. Return the decoded value. */ -static target_long decode_sleb128(uint8_t **pp) +static target_long decode_sleb128(const uint8_t **pp) { - uint8_t *p = *pp; + const uint8_t *p = *pp; target_long val = 0; int byte, shift = 0; @@ -342,7 +342,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; uintptr_t host_pc = (uintptr_t)tb->tc.ptr; CPUArchState *env = cpu->env_ptr; - uint8_t *p = tb->tc.ptr + tb->tc.size; + const uint8_t *p = tb->tc.ptr + tb->tc.size; int i, j, num_insns = tb->icount; #ifdef CONFIG_PROFILER TCGProfile *prof = &tcg_ctx->prof; @@ -393,7 +393,7 @@ void tb_destroy(TranslationBlock *tb) bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) { /* - * The host_pc has to be in the region of the code buffer. + * The host_pc has to be in the rx region of the code buffer. * If it is not we will not be able to resolve it here. * The two cases where host_pc will not be correct are: * @@ -402,7 +402,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) * * Either way we need return early as we can't resolve it here. */ - if (in_code_gen_buffer((const void *)host_pc)) { + if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb = tcg_tb_lookup(host_pc); if (tb) { cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); @@ -1712,7 +1712,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } gen_code_buf = tcg_ctx->code_gen_ptr; - tb->tc.ptr = gen_code_buf; + tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); tb->pc = pc; tb->cs_base = cs_base; tb->flags = flags; @@ -1806,15 +1806,19 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && qemu_log_in_addr_range(tb->pc)) { FILE *logfile = qemu_log_lock(); - int code_size, data_size = 0; + int code_size, data_size; + const tcg_target_ulong *rx_data_gen_ptr; size_t chunk_start; int insn = 0; if (tcg_ctx->data_gen_ptr) { - code_size = tcg_ctx->data_gen_ptr - tb->tc.ptr; + rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr); + code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr; data_size = gen_code_size - code_size; } else { + rx_data_gen_ptr = 0; code_size = gen_code_size; + data_size = 0; } /* Dump header and the first instruction */ @@ -1849,16 +1853,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (data_size) { int i; qemu_log(" data: [size=%d]\n", data_size); - for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { - if (sizeof(tcg_target_ulong) == 8) { - qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", - (uintptr_t)tcg_ctx->data_gen_ptr + i, - *(uint64_t *)(tcg_ctx->data_gen_ptr + i)); - } else { - qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", - (uintptr_t)tcg_ctx->data_gen_ptr + i, - *(uint32_t *)(tcg_ctx->data_gen_ptr + i)); - } + for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) { + qemu_log("0x%08" PRIxPTR ": .quad 0x%" TCG_PRIlx "\n", + (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); } } qemu_log("\n"); diff --git a/disas.c b/disas.c index 7c18d7d2a7..de1de7be94 100644 --- a/disas.c +++ b/disas.c @@ -299,8 +299,10 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t size) } /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, void *code, unsigned long size) +void disas(FILE *out, const void *ccode, unsigned long size) { + /* TODO: Push constness through the disas backends. */ + void *code = (void *)ccode; uintptr_t pc; int count; CPUDebug s; diff --git a/tcg/tcg.c b/tcg/tcg.c index 588686617d..5bb1edb804 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -162,6 +162,7 @@ static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; void *tcg_code_gen_epilogue; +uintptr_t tcg_splitwx_diff; #ifndef CONFIG_TCG_INTERPRETER tcg_prologue_fn *tcg_qemu_tb_exec; @@ -406,8 +407,9 @@ static void tcg_region_trees_init(void) } } -static struct tcg_region_tree *tc_ptr_to_region_tree(void *p) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) { + void *p = tcg_splitwx_to_rw(cp); size_t region_idx; if (p < region.start_aligned) { @@ -701,6 +703,7 @@ void tcg_region_init(void) size_t region_size; size_t n_regions; size_t i; + uintptr_t splitwx_diff; n_regions = tcg_n_regions(); @@ -731,6 +734,7 @@ void tcg_region_init(void) region.end -= page_size; /* set guard pages */ + splitwx_diff = tcg_splitwx_diff; for (i = 0; i < region.n; i++) { void *start, *end; int rc; @@ -738,6 +742,10 @@ void tcg_region_init(void) tcg_region_bounds(i, &start, &end); rc = qemu_mprotect_none(end, page_size); g_assert(!rc); + if (splitwx_diff) { + rc = qemu_mprotect_none(end + splitwx_diff, page_size); + g_assert(!rc); + } } tcg_region_trees_init(); @@ -752,6 +760,29 @@ void tcg_region_init(void) #endif } +#ifdef CONFIG_DEBUG_TCG +const void *tcg_splitwx_to_rx(void *rw) +{ + /* Pass NULL pointers unchanged. */ + if (rw) { + g_assert(in_code_gen_buffer(rw)); + rw += tcg_splitwx_diff; + } + return rw; +} + +void *tcg_splitwx_to_rw(const void *rx) +{ + /* Pass NULL pointers unchanged. */ + if (rx) { + rx -= tcg_splitwx_diff; + /* Assert that we end with a pointer in the rw region. */ + g_assert(in_code_gen_buffer(rx)); + } + return (void *)rx; +} +#endif /* CONFIG_DEBUG_TCG */ + static void alloc_tcg_plugin_context(TCGContext *s) { #ifdef CONFIG_PLUGIN @@ -1061,8 +1092,15 @@ void tcg_prologue_init(TCGContext *s) s->code_buf = buf0; s->data_gen_ptr = NULL; + /* + * The region trees are not yet configured, but tcg_splitwx_to_rx + * needs the bounds for an assert. + */ + region.start = buf0; + region.end = buf0 + total_size; + #ifndef CONFIG_TCG_INTERPRETER - tcg_qemu_tb_exec = (tcg_prologue_fn *)buf0; + tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(buf0); #endif /* Compute a high-water mark, at which we voluntarily flush the buffer @@ -1087,7 +1125,7 @@ void tcg_prologue_init(TCGContext *s) buf1 = s->code_ptr; #ifndef CONFIG_TCG_INTERPRETER - flush_idcache_range((uintptr_t)buf0, (uintptr_t)buf0, + flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(buf0), (uintptr_t)buf0, tcg_ptr_byte_diff(buf1, buf0)); #endif @@ -4227,8 +4265,13 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_reg_alloc_start(s); - s->code_buf = tb->tc.ptr; - s->code_ptr = tb->tc.ptr; + /* + * Reset the buffer pointers when restarting after overflow. + * TODO: Move this into translate-all.c with the rest of the + * buffer management. Having only this done here is confusing. + */ + s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); + s->code_ptr = s->code_buf; #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); @@ -4333,7 +4376,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ - flush_idcache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_buf, + flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), + (uintptr_t)s->code_buf, tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); #endif diff --git a/tcg/tci.c b/tcg/tci.c index d996eb7cf8..262a2b39ce 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -475,9 +475,10 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) #endif /* Interpret pseudo code in tb. */ -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *v_tb_ptr) +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - uint8_t *tb_ptr = v_tb_ptr; + /* TODO: Propagate const through this file. */ + uint8_t *tb_ptr = (uint8_t *)v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 385b9f749b..6eefb37f5d 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -7,4 +7,4 @@ exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=0x%x" # translate-all.c -translate_block(void *tb, uintptr_t pc, uint8_t *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" +translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" diff --git a/tcg/tcg-pool.c.inc b/tcg/tcg-pool.c.inc index 82cbcc89bd..90c2e63b7f 100644 --- a/tcg/tcg-pool.c.inc +++ b/tcg/tcg-pool.c.inc @@ -140,6 +140,8 @@ static int tcg_out_pool_finalize(TCGContext *s) for (; p != NULL; p = p->next) { size_t size = sizeof(tcg_target_ulong) * p->nlong; + uintptr_t value; + if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { if (unlikely(a > s->code_gen_highwater)) { return -1; @@ -148,7 +150,9 @@ static int tcg_out_pool_finalize(TCGContext *s) a += size; l = p; } - if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) { + + value = (uintptr_t)tcg_splitwx_to_rx(a) - size; + if (!patch_reloc(p->label, p->rtype, value, p->addend)) { return -2; } } From patchwork Mon Dec 14 14:02:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343517 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3033175jai; Mon, 14 Dec 2020 06:16:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzeXmEvuUzONanlnYn0tyhyOosGg+PyZ0hUcJ7qfRPelCt5gFPMJt47gNUS/7KsnURefTMA X-Received: by 2002:a25:c74e:: with SMTP id w75mr34824043ybe.520.1607955404822; Mon, 14 Dec 2020 06:16:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955404; cv=none; d=google.com; s=arc-20160816; b=GdITvfKkum5aFRWbizsUvUimrYqdTbNiqt10KSDrOAP4hj9firjr+zbprtPqdMY0B1 jxCLCnegQ8HJ7woVaxaWyApbz9EK+9ju1r8WHZpgy2gzlAxq5SpRVs3NWuZfFLVG7R8e jNlMWUWvKbbRPs/TuA7dJcaE/jkVT5FjPGxiNp5geWPqRjBrzxDpllAU2vkui1yqq57t K5QXNU0n9M9qshj5yOjfhGzsf9Dboa/ww6aPGWi/OPUicQ9QFHiCsl/HPdwU/vJpbwBC imgusuhE47ZQBP6UFt97/o3pI6bTKJKU/dvsPp/18xCJHVbjrDQ5R4S0kngv6sg2vXOJ RROQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3VsbV4FnPPISc6ywNLv+k5MiXrPyQIckC3OGJZ+UW18=; b=aABx3pqVDddyFCcbg3cJVJHxn5gECLBwoZxVy+qYuLe5hasG0i3sPtm17moMa49J9a XZDXp5ZPGYZAWaOBZ+jM8turYS3cVjxmdGT7g6Mq73dn7obVKUGyRwCkTvKmRwNGVrq8 UWvrBIskuVmFY0+nJiEzUu1FUJLoOH8Ma2ByZFEs1nGK625eYIWTUR9tIFJxgkPBZ3xs zqGiXxHZSjpK4nMePyvOavtckiJ9C7xuJEYgkSfPmbuEiDHnmHsUm32AoUe1407LE85y kHw3hmUeOHt//aAkeudyv4tR9Bmbieo6mHlpz0T3xcgLdyOgys8YgxJBmlSPCRvsIu+m avDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8WBcWlQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/43] tcg: Adjust TCGLabel for const Date: Mon, 14 Dec 2020 08:02:40 -0600 Message-Id: <20201214140314.18544-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change TCGLabel.u.value_ptr to const, and initialize it with tcg_splitwx_to_rx. Propagate const through tcg/host/ only as far as needed to avoid errors from the value_ptr change. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 5 +++-- tcg/ppc/tcg-target.c.inc | 4 ++-- tcg/s390/tcg-target.c.inc | 2 +- 7 files changed, 10 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 249f83be72..b2ba16ea8c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -261,7 +261,7 @@ struct TCGLabel { unsigned refs : 16; union { uintptr_t value; - tcg_insn_unit *value_ptr; + const tcg_insn_unit *value_ptr; } u; QSIMPLEQ_HEAD(, TCGRelocation) relocs; QSIMPLEQ_ENTRY(TCGLabel) next; diff --git a/tcg/tcg.c b/tcg/tcg.c index 5bb1edb804..98cd42d311 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -306,7 +306,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) { tcg_debug_assert(!l->has_value); l->has_value = 1; - l->u.value_ptr = ptr; + l->u.value_ptr = tcg_splitwx_to_rx(ptr); } TCGLabel *gen_new_label(void) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 76f8ae48ad..96dc9f4d0b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1306,7 +1306,7 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, } } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; tcg_debug_assert(offset == sextract64(offset, 0, 26)); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1e32bf42b8..f8f485d807 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1019,7 +1019,7 @@ static inline void tcg_out_st8(TCGContext *s, int cond, * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which does. */ -static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) +static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index f641105f9a..a3f838fa51 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -144,7 +144,8 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, + const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); @@ -152,7 +153,7 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) return disp & 0xffff; } -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) { *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 15d5c78798..d108f01fec 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -184,7 +184,7 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint32_t reloc_pc24_val(tcg_insn_unit *pc, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); @@ -201,7 +201,7 @@ static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) return false; } -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint16_t reloc_pc14_val(tcg_insn_unit *pc, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index ac99ccea73..1b5c4f0ab0 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1302,7 +1302,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); } -static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest) +static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/43] tcg: Adjust tcg_out_call for const Date: Mon, 14 Dec 2020 08:02:41 -0600 Message-Id: <20201214140314.18544-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must change all targets at once, since all must match the declaration in tcg.c. Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 6 +++--- tcg/ppc/tcg-target.c.inc | 8 ++++---- tcg/riscv/tcg-target.c.inc | 6 +++--- tcg/s390/tcg-target.c.inc | 2 +- tcg/sparc/tcg-target.c.inc | 4 ++-- tcg/tci/tcg-target.c.inc | 2 +- 10 files changed, 19 insertions(+), 19 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/tcg/tcg.c b/tcg/tcg.c index 98cd42d311..435b0f1662 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -149,7 +149,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 96dc9f4d0b..6d8152c468 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1329,7 +1329,7 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg) tcg_out_insn(s, 3207, BLR, reg); } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index f8f485d807..a197e6bc45 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1033,7 +1033,7 @@ static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr) /* The call case is mostly used for helpers - so it's not unreasonable * for them to be beyond branch range */ -static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 424dd1cdcf..095553ce28 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1591,7 +1591,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, } } -static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) +static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) { intptr_t disp = tcg_pcrel_diff(s, dest) - 5; @@ -1610,7 +1610,7 @@ static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) } } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 1, dest); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a3f838fa51..6d2c369a85 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -517,7 +517,7 @@ static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, * Type jump. * Returns true if the branch was in range and the insn was emitted. */ -static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) +static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) { uintptr_t dest = (uintptr_t)target; uintptr_t from = (uintptr_t)s->code_ptr + 4; @@ -1080,7 +1080,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, } } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { /* Note that the ABI requires the called function's address to be loaded into T9, even if a direct branch is in range. */ @@ -1098,7 +1098,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); tcg_out_nop(s); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d108f01fec..38dabe40c4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1106,7 +1106,7 @@ static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) tcg_out_zori32(s, dst, src, c, XORI, XORIS); } -static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) +static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_pcrel_diff(s, target); if (in_range_b(disp)) { @@ -1762,13 +1762,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we don't have to spend too much effort on building the toc. */ - void *tgt = ((void **)target)[0]; - uintptr_t toc = ((uintptr_t *)target)[1]; + const void *tgt = ((const void * const *)target)[0]; + uintptr_t toc = ((const uintptr_t *)target)[1]; intptr_t diff = tcg_pcrel_diff(s, tgt); if (in_range_b(diff) && toc == (uint32_t)toc) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ab08af7457..4416a93e1f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -449,7 +449,7 @@ static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) return false; } -static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; int32_t lo = sextreg(offset, 0, 12); @@ -861,7 +861,7 @@ static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); @@ -888,7 +888,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 1b5c4f0ab0..37f4dc4cfd 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1415,7 +1415,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, tgen_branch(s, cc, l); } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; if (off == (int32_t)off) { diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 5b3bc91b05..1a40911660 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -840,7 +840,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, +static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { ptrdiff_t disp = tcg_pcrel_diff(s, dest); @@ -855,7 +855,7 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..d5a4d9d37c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -545,7 +545,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr = s->code_ptr; tcg_out_op_t(s, INDEX_op_call); From patchwork Mon Dec 14 14:02:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343518 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3034464jai; Mon, 14 Dec 2020 06:18:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwttl0B2Hhpt8b6OVeeOWo/XECURYxTA5jHdP814XUspBDIOdq1ykDHS7Ksqv84s/Rjd8iB X-Received: by 2002:a25:4081:: with SMTP id n123mr27265680yba.237.1607955494069; Mon, 14 Dec 2020 06:18:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955494; cv=none; d=google.com; s=arc-20160816; b=zxzHwC3vXaGBrsAOGtL9iZb3x2siwk9KNXgf+1X6WD1GTg1k4RliO16tA7iWK3uC62 cLsxUNHabcSUx4mPE8u7DJ981+7w/gRzNC4Odixur0wI8i7J1E8b3+OU8GE/wxYB2noK hP0/NutrkbJJOOEghHcQpnDgJUiN59XQATvB5LZ9AQEj3sSEX/TVHVazIA6rX6zj82An cHP87Ca/gCSdKzBKk1yYNjR62Zpmhv1pnQ766uBiIRjrtggK2Mhpo4yYXjOVpap0BFof 1zBN67wrTVg+Uinkjnlra49EQAR/T0vYJmjaRwfI58pGLT1pUuRbTWB1NnHpRj/ecLOW ZDIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1GlVA1Mk+DCqrpNhETwdyV3r3sGUvkB6WjkwT6v+rmo=; b=i4mNGs3L0obTUDEW5hEN9qazvyU7c9YJMODAlz3m6QAEr+xKiDspUURnsSjm6NODkr xSIjVyVaTjuO0+RtyiHwMK5//0XmX2xlo+pcWE3Z3gGpmW1tGP5FdnEnhSVbV8Pweet4 VyWxN9Sjvd2wr+YRfznYoNH+kOKJdoRtfYcLama+RaKM0/juNMAGv+6iDqIqRvXZOAoa GORH7URvUDsJ+4bHmGI/+vSJdR4mLkHgl3XuGWzskKwFXXXiZ9HWzPAhlQacc/XXeBuj Q2nix5/k86mZ11G3IoYCjSxIGZIR2BzkDDw/n6gCRyQ9y2Thsvq6FvArWVMAOF040BO4 Kvkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZGwRjpz7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/43] tcg: Adjust tcg_out_label for const Date: Mon, 14 Dec 2020 08:02:42 -0600 Message-Id: <20201214140314.18544-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Simplify the arguments to always use s->code_ptr instead of take it as an argument. That makes it easy to ensure that the value_ptr is always the rx version. Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++--- tcg/i386/tcg-target.c.inc | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/tcg/tcg.c b/tcg/tcg.c index 435b0f1662..d94d38cc28 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -302,11 +302,11 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); } -static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) +static void tcg_out_label(TCGContext *s, TCGLabel *l) { tcg_debug_assert(!l->has_value); l->has_value = 1; - l->u.value_ptr = tcg_splitwx_to_rx(ptr); + l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); } TCGLabel *gen_new_label(void) @@ -4325,7 +4325,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) break; case INDEX_op_set_label: tcg_reg_alloc_bb_end(s, s->reserved_regs); - tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); + tcg_out_label(s, arg_label(op->args[0])); break; case INDEX_op_call: tcg_reg_alloc_call(s, op); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 095553ce28..0ac1ef3d82 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1452,7 +1452,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, default: tcg_abort(); } - tcg_out_label(s, label_next, s->code_ptr); + tcg_out_label(s, label_next); } #endif @@ -1494,10 +1494,10 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); tcg_out_jxx(s, JCC_JMP, label_over, 1); - tcg_out_label(s, label_true, s->code_ptr); + tcg_out_label(s, label_true); tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); - tcg_out_label(s, label_over, s->code_ptr); + tcg_out_label(s, label_over); } else { /* When the destination does not overlap one of the arguments, clear the destination first, jump if cond false, and emit an @@ -1511,7 +1511,7 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, tcg_out_brcond2(s, new_args, const_args+1, 1); tgen_arithi(s, ARITH_ADD, args[0], 1, 0); - tcg_out_label(s, label_over, s->code_ptr); + tcg_out_label(s, label_over); } } #endif @@ -1525,7 +1525,7 @@ static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, TCGLabel *over = gen_new_label(); tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); tcg_out_mov(s, TCG_TYPE_I32, dest, v1); - tcg_out_label(s, over, s->code_ptr); + tcg_out_label(s, over); } } From patchwork Mon Dec 14 14:02:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343500 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3020942jai; Mon, 14 Dec 2020 06:04:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJz9h892dSEVZpbVMMGovABAfOrV9cfolX+Nx/+WaC4kFapYp/je0HN0jDMl2ieeE8HybUn/ X-Received: by 2002:a5b:34e:: with SMTP id q14mr34127811ybp.291.1607954662257; Mon, 14 Dec 2020 06:04:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954662; cv=none; d=google.com; s=arc-20160816; b=Y2SBLkwxuguz+L+CCstjJq+yrQgYlSySBvXVMVHcYNDms8aeIwAFUlfclCg9P49jC0 IiKvYNJoItNZgkSLhfgHoHHiOY6RoG3m8lw8wQVuxnk4sFcyZddmE769Qe0yW9oIAUnE fbamf+AmW6xVKBTPDBQSpySjJ7z2cRZ6kjWdhglgWqd7kjyitcZD/WjvU2Clqzw+oqoI h8ouUTJaFB/rqFtapP0TzoGdB/Mk6f3RAYYUVY49KVzU65LOq/+UKtnOIsjnkIVQEfob Dg3hBlk9nMBfegmK4z72lmuYiGBZyXZFHnwzIVgy5J2qhqql75T/2yJZpcow5KeovrxZ YJfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EeMew5wTlTMjBZ99xkYZl0TWaxQaxxbFks8B9K3f6rI=; b=yvKBN4gROsAYk+fCaBA3v+wKDe7NQvuT7qswhS91nA+A+fZxYEjnmFGlzD4GujiA26 qipDgi2ycQfvkNiPDZYlWWm2dMV9XBJSU6/5JhwjYLoE/F7lc1ul3H9tK14IQX6rrWDl MRbajVmjXjAg9SVGaXNWVQXF7Rr4s4NqsqChAXRHAdbmEFwqOMPjCMCgbE3zYa48Kc3Z lbmC873fIy619PTjdEHfLbeAmZDbeAaZX6s3om8GqS0g5z4qpZ1Qe6rz6ZoC3WYM2RjV ikc26RJIzYynCgPAc5hcqejP3I94AgOJ6Vcn0CjQnEN25I/m7qDVJdW7RVqCmarWE1fU cxWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=djVNtLKc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/43] tcg: Adjust tcg_register_jit for const Date: Mon, 14 Dec 2020 08:02:43 -0600 Message-Id: <20201214140314.18544-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must change all targets at once, since all must match the declaration in tcg.c. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 10 +++++----- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 2 +- tcg/s390/tcg-target.c.inc | 2 +- tcg/sparc/tcg-target.c.inc | 2 +- 10 files changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b2ba16ea8c..67d57695c2 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1250,7 +1250,7 @@ typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif -void tcg_register_jit(void *buf, size_t buf_size); +void tcg_register_jit(const void *buf, size_t buf_size); #if TCG_TARGET_MAYBE_vec /* Return zero if the tuple (opc, type, vece) is unsupportable; diff --git a/tcg/tcg.c b/tcg/tcg.c index d94d38cc28..5f585c2ed2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -97,7 +97,7 @@ typedef struct QEMU_PACKED { DebugFrameFDEHeader fde; } DebugFrameHeader; -static void tcg_register_jit_int(void *buf, size_t size, +static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) __attribute__((unused)); @@ -1137,7 +1137,7 @@ void tcg_prologue_init(TCGContext *s) total_size -= prologue_size; s->code_gen_buffer_size = total_size; - tcg_register_jit(s->code_gen_buffer, total_size); + tcg_register_jit(tcg_splitwx_to_rx(s->code_gen_buffer), total_size); #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { @@ -4507,7 +4507,7 @@ static int find_string(const char *strtab, const char *str) } } -static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, +static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, const void *debug_frame, size_t debug_frame_size) { @@ -4709,13 +4709,13 @@ static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, /* No support for the feature. Provide the entry point expected by exec.c, and implement the internal function we declared earlier. */ -static void tcg_register_jit_int(void *buf, size_t size, +static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) { } -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { } #endif /* ELF_HOST_MACHINE */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 6d8152c468..9ace859db3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2964,7 +2964,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index a197e6bc45..9b9400f164 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2353,7 +2353,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0ac1ef3d82..7f74c77d7f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3998,7 +3998,7 @@ static const DebugFrame debug_frame = { #endif #if defined(ELF_HOST_MACHINE) -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 6d2c369a85..e9c8c24741 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2703,7 +2703,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 38dabe40c4..a0a5bac13f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3847,7 +3847,7 @@ static DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { uint8_t *p = &debug_frame.fde_reg_ofs[3]; int i; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4416a93e1f..025e3cd0bb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1907,7 +1907,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 37f4dc4cfd..1444914428 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2620,7 +2620,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 1a40911660..4c81d5f1c2 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1816,7 +1816,7 @@ static const DebugFrame debug_frame = { .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } From patchwork Mon Dec 14 14:02:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343537 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3039194jai; Mon, 14 Dec 2020 06:23:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJynaQS1/HMwJDMWxV3+VXBExdvqtsQbucVie6izIra0zUpYyPVn/LEL7jprCnhyyeV1kPcs X-Received: by 2002:a5b:107:: with SMTP id 7mr26608914ybx.253.1607955823322; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/43] tcg: Adjust tb_target_set_jmp_target for split-wx Date: Mon, 14 Dec 2020 08:02:44 -0600 Message-Id: <20201214140314.18544-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::344; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass both rx and rw addresses to tb_target_set_jmp_target. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/arm/tcg-target.h | 2 +- tcg/i386/tcg-target.h | 6 +++--- tcg/mips/tcg-target.h | 2 +- tcg/ppc/tcg-target.h | 2 +- tcg/riscv/tcg-target.h | 2 +- tcg/s390/tcg-target.h | 8 ++++---- tcg/sparc/tcg-target.h | 2 +- tcg/tci/tcg-target.h | 6 +++--- accel/tcg/cpu-exec.c | 4 +++- tcg/aarch64/tcg-target.c.inc | 12 ++++++------ tcg/mips/tcg-target.c.inc | 8 ++++---- tcg/ppc/tcg-target.c.inc | 16 ++++++++-------- tcg/sparc/tcg-target.c.inc | 14 +++++++------- 14 files changed, 44 insertions(+), 42 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 8a6b97598e..6ba248f447 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -148,7 +148,7 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index f1955ce4ac..6ca4537ca6 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -135,7 +135,7 @@ enum { #define TCG_TARGET_HAS_MEMORY_BSWAP 1 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index cd067e0b30..0dcaed7fe6 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -206,11 +206,11 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 92c1d63da3..d23baf7cda 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -201,7 +201,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a509a19628..c41d10142b 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -175,7 +175,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c1bd52bb9a..3d0745c70c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -160,7 +160,7 @@ typedef enum { #endif /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index b4feb2f55a..3750952598 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -145,12 +145,12 @@ enum { TCG_AREG0 = TCG_REG_R10, }; -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - intptr_t disp = addr - (jmp_addr - 2); - qatomic_set((int32_t *)jmp_addr, disp / 2); + intptr_t disp = addr - (jmp_rx - 2); + qatomic_set((int32_t *)jmp_rw, disp / 2); /* no need to flush icache explicitly */ } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8b0e32e2e..9c15c91d39 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,7 +168,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index b84480f989..fcec2e70db 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,11 +198,11 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 1e3cb570f6..272d596e0c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -354,7 +354,9 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset = tb->jmp_target_arg[n]; uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr; - tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); + uintptr_t jmp_rx = tc_ptr + offset; + uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff; + tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr); } else { tb->jmp_target_arg[n] = addr; } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 9ace859db3..fea784cf75 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1340,21 +1340,21 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) } } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { tcg_insn_unit i1, i2; TCGType rt = TCG_TYPE_I64; TCGReg rd = TCG_REG_TMP; uint64_t pair; - ptrdiff_t offset = addr - jmp_addr; + ptrdiff_t offset = addr - jmp_rx; if (offset == sextract64(offset, 0, 26)) { i1 = I3206_B | ((offset >> 2) & 0x3ffffff); i2 = NOP; } else { - offset = (addr >> 12) - (jmp_addr >> 12); + offset = (addr >> 12) - (jmp_rx >> 12); /* patch ADRP */ i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd; @@ -1362,8 +1362,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; } pair = (uint64_t)i2 << 32 | i1; - qatomic_set((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e9c8c24741..52638e920c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2657,11 +2657,11 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { - qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } typedef struct { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index a0a5bac13f..0eb9c4ebe2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1722,13 +1722,13 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { if (TCG_TARGET_REG_BITS == 64) { tcg_insn_unit i1, i2; intptr_t tb_diff = addr - tc_ptr; - intptr_t br_diff = addr - (jmp_addr + 4); + intptr_t br_diff = addr - (jmp_rx + 4); uint64_t pair; /* This does not exercise the range of the branch, but we do @@ -1752,13 +1752,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, /* As per the enclosing if, this is ppc64. Avoid the _Static_assert within qatomic_set that would fail to build a ppc32 host. */ - qatomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set__nocheck((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } else { - intptr_t diff = addr - jmp_addr; + intptr_t diff = addr - jmp_rx; tcg_debug_assert(in_range_b(diff)); - qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 4c81d5f1c2..d599ae27b5 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1821,11 +1821,11 @@ void tcg_register_jit(const void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { intptr_t tb_disp = addr - tc_ptr; - intptr_t br_disp = addr - jmp_addr; + intptr_t br_disp = addr - jmp_rx; tcg_insn_unit i1, i2; /* We can reach the entire address space for ILP32. @@ -1834,9 +1834,9 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, tcg_debug_assert(br_disp == (int32_t)br_disp); if (!USE_REG_TB) { - qatomic_set((uint32_t *)jmp_addr, + qatomic_set((uint32_t *)jmp_rw, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + flush_idcache_range(jmp_rx, jmp_rw, 4); return; } @@ -1859,6 +1859,6 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); } - qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1)); + flush_idcache_range(jmp_rx, jmp_rw, 8); } From patchwork Mon Dec 14 14:02:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343533 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3037220jai; Mon, 14 Dec 2020 06:21:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJzYQEMyzRgCLe7XD0QqdtUKgInmRqkbWsU8FGaxZvOwFE2ipHSmLSjj2J2bdIcQ5+R3nsk8 X-Received: by 2002:a5b:812:: with SMTP id x18mr38932247ybp.334.1607955677740; Mon, 14 Dec 2020 06:21:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955677; cv=none; d=google.com; s=arc-20160816; b=mm9IwFH2VyqK7wnAbjCay6MgpVKPAqFiIuFSniaKS5MSHZ4H+1aWkdtxcDLGmdp3Dp j0s9x4L+bVlfyo9yRqFKTe2qZgF53WjJesc0bdYWJHEUxHNQzSTSc+moWktF72yRsU/u a21TkiZz4jtEpv93gDz3vgZxLspBV/3LLC+UYd5SMbGX+c87yZnFisQYdAPrTP1QJwkd fPGomg1hg7u01ZzQIucm4Ndv7zfBIr2VGGZ+ZUxikOW6G0CdsxPRcpFuIpnySkpokU+b ZthG92PdWttEawf0XZ873NdZYafGh6zr5ELjcOqRYzqZ8NZ71facJEgOwgalAMRpYXO6 5mWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wpyFYYIqvE4n/WbNDVjRAK3hdmdxC+OlWEmANDViNo4=; b=fwCRldWQsaWoYFbYtd7g8XBc3RWattm9Z0aUD0jt/GJjlU7pYfML+YEmrXGb/R0El6 ahOtX32ieqaGUyWjEnjxLqFDgw1+tPv9Scu82s4zpCZLI4Jqkfz6YD1jAYfdg2aUg2Vu LCj9dgNpchD5T25xYqlZKlwZOdhD7ZKWrSeITZcFfRezVcE5LtoSFsItMkBFuzPW229B UJ4qqCwsQmSnlifODKQHWyzzcPFVwkgpJKLn+wp3fUleEX6v0AdFXSCWZOJNYuvQc3qs A8MvNKB8znLdqJw73QrkXF8hcEJ5B90vun2SzHffpDHA37HRS9qVVQNe2uTpejTBm6XN i5Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VkU03tSW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/43] tcg: Make DisasContextBase.tb const Date: Mon, 14 Dec 2020 08:02:45 -0600 Message-Id: <20201214140314.18544-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 4 ++-- include/exec/translator.h | 2 +- include/tcg/tcg-op.h | 2 +- accel/tcg/translator.c | 4 ++-- target/arm/translate-a64.c | 2 +- tcg/tcg-op.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 822c43cfd3..aa4b44354a 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -32,7 +32,7 @@ static inline void gen_io_end(void) tcg_temp_free_i32(tmp); } -static inline void gen_tb_start(TranslationBlock *tb) +static inline void gen_tb_start(const TranslationBlock *tb) { TCGv_i32 count, imm; @@ -71,7 +71,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(count); } -static inline void gen_tb_end(TranslationBlock *tb, int num_insns) +static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) { if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know diff --git a/include/exec/translator.h b/include/exec/translator.h index 638e1529c5..24232ead41 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -67,7 +67,7 @@ typedef enum DisasJumpType { * Architecture-agnostic disassembly context. */ typedef struct DisasContextBase { - TranslationBlock *tb; + const TranslationBlock *tb; target_ulong pc_first; target_ulong pc_next; DisasJumpType is_jmp; diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5abf17fecc..cbe39a3b95 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -805,7 +805,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, * be NULL and @idx should be 0. Otherwise, @tb should be valid and * @idx should be one of the TB_EXIT_ values. */ -void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx); +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); /** * tcg_gen_goto_tb() - output goto_tb TCG operation diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index fb1e19c585..a49a794065 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -133,8 +133,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } /* The disas_log hook may use these values rather than recompute. */ - db->tb->size = db->pc_next - db->pc_first; - db->tb->icount = db->num_insns; + tb->size = db->pc_next - db->pc_first; + tb->icount = db->num_insns; #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e3fdfdf6b..ef63edfc68 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -410,7 +410,7 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) { - TranslationBlock *tb; + const TranslationBlock *tb; tb = s->base.tb; if (use_goto_tb(s, n, dest)) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4b8a473fad..e3dc0cb4cb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2664,7 +2664,7 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) /* QEMU specific operations. */ -void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx) +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) { uintptr_t val = (uintptr_t)tb + idx; From patchwork Mon Dec 14 14:02:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343505 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3024529jai; Mon, 14 Dec 2020 06:08:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJwGmAZHEbz96u2CDwhfyP7pL/wyYCvaeyp5unj2XkcvG4hFTuakXUBJRcZHxRUeAmV6Nlb+ X-Received: by 2002:a25:bdc7:: with SMTP id g7mr35157557ybk.427.1607954879923; Mon, 14 Dec 2020 06:07:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954879; cv=none; d=google.com; s=arc-20160816; b=Cc0xXMqvQGxcsYj8v4zRO0TOMP8RMVYAgLWEALi6NKC3Y7Zj3KufH9aOvPzovCjU4I a22a+pa/tF+fBOB5YQLqZ6E8VTwzOcTV+3R/JAcvPLbR50uXon9etVjXsoyvKnwhddWF BN6ZPmTyq0nQ+Rijw7ijLrieLkUyRiCBkQYhUXpOIftf/1Eq0jTzCBYf7dSyNIF2P44e nG61VYbX43g0UxVA2tPs51OV5T0ejr3y8odMKFuv38s209Jhjvy+b1ah1dKdaXZt82qd ejBEljxRWBwcfZLasEVgxdEXLG3awANQtpY/ScVhMlAHUH44Vx6sQu7tyv8xCzJlZcJ6 FUiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L3KSYgTID8lxe/3Pvx+7FaZP4H7EiUhUFytfizdwcH0=; b=jNSYfIIwHytAZvoNtjE9bjR7dSU4CQf3dAV7a3HS5H/enkffxJc3Ttt81z4KDLocs6 1qERUxMgqJMUlI0zsYSglJ1fyv1el/dmTGtAXMoZ8BktfjBfY5jk5ngnqNrxA/kgdq8Q mAoQc4ygn6uwe0itiGzcl1BGQuLRGxlxLyLR04QC12/PCCQAof898vZN5y8KrxI32hpK zisKPp4dq2gJgNX4GHmtQegpV+L7v0bTL5zUt0PZPfU0kVe+kkXVGpjGY5HzO9MFlwsn pEU7V25F1UKw59Bi7YmiyCphFvzZNjBaG8gZmtkJAKPaEImb+ERzoXK155SZ275tubMb QXuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kny7zWOy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/43] tcg: Make tb arg to synchronize_from_tb const Date: Mon, 14 Dec 2020 08:02:46 -0600 Message-Id: <20201214140314.18544-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 ++- target/arm/cpu.c | 3 ++- target/avr/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/riscv/cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 2 +- 12 files changed, 23 insertions(+), 12 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3d92c967ff..44c336a96a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -189,7 +189,8 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); + void (*synchronize_from_tb)(CPUState *cpu, + const struct TranslationBlock *tb); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d6188f6566..62e319eb6a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -54,7 +54,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } -static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d9c4ad5bf..6f3d5a9e4a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -41,7 +41,8 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } -static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void avr_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { AVRCPU *cpu = AVR_CPU(cs); CPUAVRState *env = &cpu->env; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 71b6aca45d..e28f047d10 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -35,7 +35,8 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iaoq_b = value + 4; } -static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void hppa_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6c11feeb92..258b0d6148 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7047,7 +7047,8 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip = value; } -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void x86_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b2482159d..c8e754cfb1 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -83,7 +83,8 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iflags = 0; } -static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void mb_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..79eee215cf 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -44,7 +44,8 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } -static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void mips_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..1b2f40de47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -285,7 +285,8 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) env->pc = value; } -static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 23ee17a701..2bb14144a7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -33,7 +33,8 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } -static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void rx_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RXCPU *cpu = RX_CPU(cs); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3c68021c56..1e0f05a15b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -34,7 +34,8 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } -static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void superh_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SuperHCPU *cpu = SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 701e794eac..57db14548c 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -691,7 +691,8 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.npc = value + 4; } -static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void sparc_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SPARCCPU *cpu = SPARC_CPU(cs); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 2f2e5b029f..4bff1d4718 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -42,7 +42,7 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) } static void tricore_cpu_synchronize_from_tb(CPUState *cs, - TranslationBlock *tb) + const TranslationBlock *tb) { TriCoreCPU *cpu = TRICORE_CPU(cs); CPUTriCoreState *env = &cpu->env; From patchwork Mon Dec 14 14:02:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343514 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3032207jai; Mon, 14 Dec 2020 06:15:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJxKZtmBYysj3e87K4X66R3ZQUpuGXLf8Gb+0KLplfnboY1mAUDGvlbBk8wcE0F95gT3XE6T X-Received: by 2002:a25:ab31:: with SMTP id u46mr35487857ybi.179.1607955344893; Mon, 14 Dec 2020 06:15:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955344; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/43] tcg: Use Error with alloc_code_gen_buffer Date: Mon, 14 Dec 2020 08:02:47 -0600 Message-Id: <20201214140314.18544-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Report better error messages than just "could not allocate". Let alloc_code_gen_buffer set ctx->code_gen_buffer_size and ctx->code_gen_buffer, and simply return bool. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 60 ++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7b85ddacd2..2824b3e387 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -59,6 +59,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" +#include "qapi/error.h" /* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_FLUSH */ @@ -963,7 +964,7 @@ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) -static inline size_t size_code_gen_buffer(size_t tb_size) +static size_t size_code_gen_buffer(size_t tb_size) { /* Size the buffer. */ if (tb_size == 0) { @@ -1014,7 +1015,7 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) { void *buf = static_code_gen_buffer; void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); @@ -1027,9 +1028,8 @@ static inline void *alloc_code_gen_buffer(void) size = end - buf; /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx->code_gen_buffer_size) { - size = QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size, - qemu_real_host_page_size); + if (size > tb_size) { + size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } tcg_ctx->code_gen_buffer_size = size; @@ -1041,31 +1041,43 @@ static inline void *alloc_code_gen_buffer(void) #endif if (qemu_mprotect_rwx(buf, size)) { - abort(); + error_setg_errno(errp, errno, "mprotect of jit buffer"); + return false; } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); - return buf; + tcg_ctx->code_gen_buffer = buf; + return true; } #elif defined(_WIN32) -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t size, Error **errp) { - size_t size = tcg_ctx->code_gen_buffer_size; - return VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, - PAGE_EXECUTE_READWRITE); + void *buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + PAGE_EXECUTE_READWRITE); + if (buf == NULL) { + error_setg_win32(errp, GetLastError(), + "allocate %zu bytes for jit buffer", size); + return false; + } + + tcg_ctx->code_gen_buffer = buf; + tcg_ctx->code_gen_buffer_size = size; + return true; } #else -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t size, Error **errp) { int prot = PROT_WRITE | PROT_READ | PROT_EXEC; int flags = MAP_PRIVATE | MAP_ANONYMOUS; - size_t size = tcg_ctx->code_gen_buffer_size; void *buf; buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { - return NULL; + error_setg_errno(errp, errno, + "allocate %zu bytes for jit buffer", size); + return false; } + tcg_ctx->code_gen_buffer_size = size; #ifdef __mips__ if (cross_256mb(buf, size)) { @@ -1104,20 +1116,11 @@ static inline void *alloc_code_gen_buffer(void) /* Request large pages for the buffer. */ qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); - return buf; + tcg_ctx->code_gen_buffer = buf; + return true; } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ -static inline void code_gen_alloc(size_t tb_size) -{ - tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); - tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(); - if (tcg_ctx->code_gen_buffer == NULL) { - fprintf(stderr, "Could not allocate dynamic translator buffer\n"); - exit(1); - } -} - static bool tb_cmp(const void *ap, const void *bp) { const TranslationBlock *a = ap; @@ -1144,11 +1147,16 @@ static void tb_htable_init(void) size. */ void tcg_exec_init(unsigned long tb_size) { + bool ok; + tcg_allowed = true; cpu_gen_init(); page_init(); tb_htable_init(); - code_gen_alloc(tb_size); + + ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), &error_fatal); + assert(ok); + #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ From patchwork Mon Dec 14 14:02:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343541 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3043422jai; Mon, 14 Dec 2020 06:28:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJxbevMPnT5yjxo4aNAqVKVckIKRUBahRZeR6RbPb4Ca9FeDkYaEsyK6wgFaZGNueqg3Ymud X-Received: by 2002:a25:7452:: with SMTP id p79mr3234213ybc.23.1607956138058; Mon, 14 Dec 2020 06:28:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/43] tcg: Add --accel tcg,split-wx property Date: Mon, 14 Dec 2020 08:02:48 -0600 Message-Id: <20201214140314.18544-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Signed-off-by: Richard Henderson --- include/sysemu/tcg.h | 3 ++- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/riscv/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 1 + accel/tcg/tcg-all.c | 26 +++++++++++++++++++++++++- accel/tcg/translate-all.c | 35 +++++++++++++++++++++++++++-------- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- 14 files changed, 65 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index d9d3ca8559..00349fb18a 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,7 +8,8 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H -void tcg_exec_init(unsigned long tb_size); +void tcg_exec_init(unsigned long tb_size, int splitwx); + #ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 6ba248f447..92aefc32d3 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -154,5 +154,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6ca4537ca6..7e04755428 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,5 +141,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0dcaed7fe6..04eefbfb90 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -231,5 +231,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d23baf7cda..d6dff897bf 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -200,6 +200,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_SUPPORT_MIRROR 0 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c41d10142b..8fc2672bf0 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -184,5 +184,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 3d0745c70c..785fe37f9b 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -170,5 +170,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3750952598..fed3329e51 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -158,5 +158,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 9c15c91d39..21e7e2f56f 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -171,5 +171,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index fcec2e70db..768153fd02 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -197,6 +197,7 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_SUPPORT_MIRROR 0 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 1ac0b76515..2eea8c32ee 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ struct TCGState { AccelState parent_obj; bool mttcg_enabled; + int splitwx_enabled; unsigned long tb_size; }; typedef struct TCGState TCGState; @@ -94,6 +95,13 @@ static void tcg_accel_instance_init(Object *obj) TCGState *s = TCG_STATE(obj); s->mttcg_enabled = default_mttcg_enabled(); + + /* If debugging enabled, default "auto on", otherwise off. */ +#ifdef CONFIG_DEBUG_TCG + s->splitwx_enabled = -1; +#else + s->splitwx_enabled = 0; +#endif } bool mttcg_enabled; @@ -102,7 +110,7 @@ static int tcg_init(MachineState *ms) { TCGState *s = TCG_STATE(current_accel()); - tcg_exec_init(s->tb_size * 1024 * 1024); + tcg_exec_init(s->tb_size * 1024 * 1024, s->splitwx_enabled); mttcg_enabled = s->mttcg_enabled; /* @@ -179,6 +187,18 @@ static void tcg_set_tb_size(Object *obj, Visitor *v, s->tb_size = value; } +static bool tcg_get_splitwx(Object *obj, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + return s->splitwx_enabled; +} + +static void tcg_set_splitwx(Object *obj, bool value, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + s->splitwx_enabled = value; +} + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -196,6 +216,10 @@ static void tcg_accel_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "tb-size", "TCG translation block cache size"); + object_class_property_add_bool(oc, "split-wx", + tcg_get_splitwx, tcg_set_splitwx); + object_class_property_set_description(oc, "split-wx", + "Map jit pages into separate RW and RX regions"); } static const TypeInfo tcg_accel_type = { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2824b3e387..a29cb4a42e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1015,13 +1015,19 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) +static bool alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) { - void *buf = static_code_gen_buffer; - void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); + void *buf, *end; size_t size; + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + /* page-align the beginning and end of the buffer */ + buf = static_code_gen_buffer; + end = static_code_gen_buffer + sizeof(static_code_gen_buffer); buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); @@ -1050,9 +1056,16 @@ static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) return true; } #elif defined(_WIN32) -static bool alloc_code_gen_buffer(size_t size, Error **errp) +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { - void *buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + void *buf; + + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + + buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, PAGE_EXECUTE_READWRITE); if (buf == NULL) { error_setg_win32(errp, GetLastError(), @@ -1065,12 +1078,17 @@ static bool alloc_code_gen_buffer(size_t size, Error **errp) return true; } #else -static bool alloc_code_gen_buffer(size_t size, Error **errp) +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { int prot = PROT_WRITE | PROT_READ | PROT_EXEC; int flags = MAP_PRIVATE | MAP_ANONYMOUS; void *buf; + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { error_setg_errno(errp, errno, @@ -1145,7 +1163,7 @@ static void tb_htable_init(void) /* Must be called before using the QEMU cpus. 'tb_size' is the size (in bytes) allocated to the translation buffer. Zero means default size. */ -void tcg_exec_init(unsigned long tb_size) +void tcg_exec_init(unsigned long tb_size, int splitwx) { bool ok; @@ -1154,7 +1172,8 @@ void tcg_exec_init(unsigned long tb_size) page_init(); tb_htable_init(); - ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), &error_fatal); + ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), + splitwx, &error_fatal); assert(ok); #if defined(CONFIG_SOFTMMU) diff --git a/bsd-user/main.c b/bsd-user/main.c index 0a918e8f74..086351fc6f 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -908,7 +908,7 @@ int main(int argc, char **argv) } /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu_type = parse_cpu_option(cpu_model); cpu = cpu_create(cpu_type); diff --git a/linux-user/main.c b/linux-user/main.c index 24d1eb73ad..5ff8100770 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -703,7 +703,7 @@ int main(int argc, char **argv, char **envp) cpu_type = parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu = cpu_create(cpu_type); env = cpu->env_ptr; From patchwork Mon Dec 14 14:02:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343520 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3034756jai; Mon, 14 Dec 2020 06:18:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwcFnl891U2XpPNT2okQ+1k0DZfx1ancDauKW1/XlvrQDJUhBHI1RDAW0Y7DG5QOK4Dfrby X-Received: by 2002:a25:76c3:: with SMTP id r186mr22481694ybc.226.1607955516931; Mon, 14 Dec 2020 06:18:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955516; cv=none; d=google.com; s=arc-20160816; b=EbvkeHALJPkuQKBc3N11JDxSvQcl7ZYEAblUHFUJTbkgVZH934IWX7kpR8iWemtDS1 OITrVnaZUysXm2Uc/hsnrYbn8gwnCZegL9eWYElfrfIoKEWTOwMsnvRmPVH31JchJ9ew apHTf4U60OXSLulvKYry5guPQfjlLbIJGCs39UCpzM1l+zumu/Mb7fNfumU/JJ+a3GyV ubT4SPyoceWvSXtLqiP7K78RVhZGVv56NhtRpu71hocoIxFSU4q06gjiAiulUJt0At1L byYE8v3pAwDZ1A15Ee6spyH8ERfQypWsLAHI0HVTGkyf0zWZhBZnEJT7dehtuLm5i2ry q/tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QxiqvQ209wXHxoJuZyW/ayX9Rmszqy3dKezpaxev5Pc=; b=Zr0ZhCcBSHQ/NgtGcA4Yv2w2mRlUgftOfLlTs0iCt0sxFUjdxNyEgaEmypVBYEhdrk VIdFZJ5h9TudexzHBg93QIOLyAisFaRqg9DdtFhXICcQ6kq35YwAThh3gHESa+5SzJaw +Z0+1eZoT+7J2DxefZRSmUEx3MyIvS9q4GcJgGPMDcWEFFvz/EfgXpF+JhYcjWXWcqPo KQ0DaPAc2UJhplsHXX12xR89IL95egWrdBtl48PC0JvqPagJQrdtG628s+Smu8Erxztw bPxankxGYgdxRxNf/OWYB198eAe1Li/AB7q0NVTtv+f2pI02yw173cGroPNbOcYhQYFQ b0pQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q+eUyja2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/43] accel/tcg: Support split-wx for linux with memfd Date: Mon, 14 Dec 2020 08:02:49 -0600 Message-Id: <20201214140314.18544-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 84 +++++++++++++++++++++++++++++++++++---- 1 file changed, 76 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a29cb4a42e..1931e65365 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1078,17 +1078,11 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) return true; } #else -static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) +static bool alloc_code_gen_buffer_anon(size_t size, int prot, + int flags, Error **errp) { - int prot = PROT_WRITE | PROT_READ | PROT_EXEC; - int flags = MAP_PRIVATE | MAP_ANONYMOUS; void *buf; - if (splitwx > 0) { - error_setg(errp, "jit split-wx not supported"); - return false; - } - buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { error_setg_errno(errp, errno, @@ -1137,6 +1131,80 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) tcg_ctx->code_gen_buffer = buf; return true; } + +#ifdef CONFIG_POSIX +#include "qemu/memfd.h" + +static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) +{ + void *buf_rw, *buf_rx; + int fd = -1; + + buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); + if (buf_rw == NULL) { + return false; + } + + buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); + if (buf_rx == MAP_FAILED) { + error_setg_errno(errp, errno, + "failed to map shared memory for execute"); + munmap(buf_rw, size); + close(fd); + return false; + } + close(fd); + + tcg_ctx->code_gen_buffer = buf_rw; + tcg_ctx->code_gen_buffer_size = size; + tcg_splitwx_diff = buf_rx - buf_rw; + + /* Request large pages for the buffer and the splitwx. */ + qemu_madvise(buf_rw, size, QEMU_MADV_HUGEPAGE); + qemu_madvise(buf_rx, size, QEMU_MADV_HUGEPAGE); + return true; +} +#endif /* CONFIG_POSIX */ + +static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) +{ + if (TCG_TARGET_SUPPORT_MIRROR) { +#ifdef CONFIG_POSIX + return alloc_code_gen_buffer_splitwx_memfd(size, errp); +#endif + } + error_setg(errp, "jit split-wx not supported"); + return false; +} + +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) +{ + ERRP_GUARD(); + int prot, flags; + + if (splitwx) { + if (alloc_code_gen_buffer_splitwx(size, errp)) { + return true; + } + /* + * If splitwx force-on (1), fail; + * if splitwx default-on (-1), fall through to splitwx off. + */ + if (splitwx > 0) { + return false; + } + error_free_or_abort(errp); + } + + prot = PROT_READ | PROT_WRITE | PROT_EXEC; + flags = MAP_PRIVATE | MAP_ANONYMOUS; +#ifdef CONFIG_TCG_INTERPRETER + /* The tcg interpreter does not need execute permission. */ + prot = PROT_READ | PROT_WRITE; +#endif + + return alloc_code_gen_buffer_anon(size, prot, flags, errp); +} #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ static bool tb_cmp(const void *ap, const void *bp) From patchwork Mon Dec 14 14:02:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343508 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3027661jai; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/43] accel/tcg: Support split-wx for darwin/iOS with vm_remap Date: Mon, 14 Dec 2020 08:02:50 -0600 Message-Id: <20201214140314.18544-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cribbed from code posted by Joelle van Dyne , and rearranged to a cleaner structure. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 65 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1931e65365..17df6c94fa 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1166,9 +1166,71 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) } #endif /* CONFIG_POSIX */ +#ifdef CONFIG_DARWIN +#include + +extern kern_return_t mach_vm_remap(vm_map_t target_task, + mach_vm_address_t *target_address, + mach_vm_size_t size, + mach_vm_offset_t mask, + int flags, + vm_map_t src_task, + mach_vm_address_t src_address, + boolean_t copy, + vm_prot_t *cur_protection, + vm_prot_t *max_protection, + vm_inherit_t inheritance); + +static bool alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp) +{ + kern_return_t ret; + mach_vm_address_t buf_rw, buf_rx; + vm_prot_t cur_prot, max_prot; + + /* Map the read-write portion via normal anon memory. */ + if (!alloc_code_gen_buffer_anon(size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, errp)) { + return false; + } + + buf_rw = (mach_vm_address_t)tcg_ctx->code_gen_buffer; + buf_rx = 0; + ret = mach_vm_remap(mach_task_self(), + &buf_rx, + size, + 0, + VM_FLAGS_ANYWHERE, + mach_task_self(), + buf_rw, + false, + &cur_prot, + &max_prot, + VM_INHERIT_NONE); + if (ret != KERN_SUCCESS) { + /* TODO: Convert "ret" to a human readable error message. */ + error_setg(errp, "vm_remap for jit splitwx failed"); + munmap((void *)buf_rw, size); + return false; + } + + if (mprotect((void *)buf_rx, size, PROT_READ | PROT_EXEC) != 0) { + error_setg_errno(errp, errno, "mprotect for jit splitwx"); + munmap((void *)buf_rx, size); + munmap((void *)buf_rw, size); + return false; + } + + tcg_splitwx_diff = buf_rx - buf_rw; + return true; +} +#endif /* CONFIG_DARWIN */ + static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) { if (TCG_TARGET_SUPPORT_MIRROR) { +#ifdef CONFIG_DARWIN + return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +#endif #ifdef CONFIG_POSIX return alloc_code_gen_buffer_splitwx_memfd(size, errp); #endif @@ -1201,6 +1263,9 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) #ifdef CONFIG_TCG_INTERPRETER /* The tcg interpreter does not need execute permission. */ prot = PROT_READ | PROT_WRITE; +#elif defined(CONFIG_DARWIN) + /* Applicable to both iOS and macOS (Apple Silicon). */ + flags |= MAP_JIT; #endif return alloc_code_gen_buffer_anon(size, prot, flags, errp); From patchwork Mon Dec 14 14:02:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343532 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3037166jai; Mon, 14 Dec 2020 06:21:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJyEddxov72LP9vRdDwH5kZyMLM284BgOavfxuEPbaZNKJ0a6WkKSjgrA/i1Ygb8DZuJkTOx X-Received: by 2002:a25:df8b:: with SMTP id w133mr38313994ybg.491.1607955674026; Mon, 14 Dec 2020 06:21:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955674; cv=none; d=google.com; s=arc-20160816; b=CNq2YsEj/TC1fa/PluKg9yfEc+JAe02gUz+IPwO2OojBIL7arq6Uh3ic9vfvyprY3c tuf9c2BlAPhVjELCagEk53goKFcxBlJkeDTZOw+uUHkkdQHLCm+Ah2+1utm7bC5RJIdo Zy/4lj4iBz1Q9P3iBFRe3R1MWGrVWcxRGWHOMCWpmy8pv1NGap3Kic8e20ooLfktfyd5 66yz1xJb/XStmaAreZAOlVObtRgfo2OTvnHTJJPhW1svUtB6h79xeEBS36uXLZp7Efvy v7/094xAPTqvgqYYYjy6MtRo8OuzRBpAiFZ5euUSV3+7rDPt1oSdqacXr6b0a670yXzl 0rhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PE5zDJYupwBF6LFLJEA3Vgnp30HPDgVW1boJkF7byFo=; b=OwpR8DvL92Dm/etaXItkKxhvJPw9H1NZ5deftYDWPGT9QLbsicaL734pQcr77FKDo5 YBVwChr+lSePgwWJS0moP/Ej8/ciN1ia+BGze0fA6i+/jr3VL9hCnWSxyG7Ik1X15A/8 tQYNM0YeildAisjBoJ4gdpbtK8XJEzzE5O84PjqoPnpV5eLM1h9E5FO+2zs9k/kIEjLq kzUnEbVlU72i/cXQ0yfidkxm1yCVWq/0+fcd3MnGsdes0o923MFitFhBo9bjg+CQhkVv Ex8lIn5Rjuuz9AjCuGLIVUCAvC9gJstu9v5WIK/KImydQB1vO+Lz1ca9t7rLuiNi/Ws3 aGEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wa68fek1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/43] tcg: Return the TB pointer from the rx region from exit_tb Date: Mon, 14 Dec 2020 08:02:51 -0600 Message-Id: <20201214140314.18544-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 35 ++++++++++++++++++++++------------- tcg/tcg-op.c | 13 ++++++++++++- 2 files changed, 34 insertions(+), 14 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 272d596e0c..8df0a1782e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -144,12 +144,13 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) #endif /* CONFIG USER ONLY */ /* Execute a TB, and fix up the CPU state afterwards if necessary */ -static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) +static inline TranslationBlock *cpu_tb_exec(CPUState *cpu, + TranslationBlock *itb, + int *tb_exit) { CPUArchState *env = cpu->env_ptr; uintptr_t ret; TranslationBlock *last_tb; - int tb_exit; const void *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, @@ -177,11 +178,20 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) ret = tcg_qemu_tb_exec(env, tb_ptr); cpu->can_do_io = 1; - last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - tb_exit = ret & TB_EXIT_MASK; - trace_exec_tb_exit(last_tb, tb_exit); + /* + * TODO: Delay swapping back to the read-write region of the TB + * until we actually need to modify the TB. The read-only copy, + * coming from the rx region, shares the same host TLB entry as + * the code that executed the exit_tb opcode that arrived here. + * If we insist on touching both the RX and the RW pages, we + * double the host TLB pressure. + */ + last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK)); + *tb_exit = ret & TB_EXIT_MASK; - if (tb_exit > TB_EXIT_IDX1) { + trace_exec_tb_exit(last_tb, *tb_exit); + + if (*tb_exit > TB_EXIT_IDX1) { /* We didn't start executing this TB (eg because the instruction * counter hit zero); we must restore the guest PC to the address * of the start of the TB. @@ -199,7 +209,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) cc->set_pc(cpu, last_tb->pc); } } - return ret; + return last_tb; } #ifndef CONFIG_USER_ONLY @@ -210,6 +220,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, { TranslationBlock *tb; uint32_t cflags = curr_cflags() | CF_NOCACHE; + int tb_exit; if (ignore_icount) { cflags &= ~CF_USE_ICOUNT; @@ -227,7 +238,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, /* execute the generated code */ trace_exec_tb_nocache(tb, tb->pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); mmap_lock(); tb_phys_invalidate(tb, -1); @@ -244,6 +255,7 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags; uint32_t cflags = 1; uint32_t cf_mask = cflags & CF_HASH_MASK; + int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { start_exclusive(); @@ -260,7 +272,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); cc->cpu_exec_exit(cpu); } else { /* @@ -653,13 +665,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, TranslationBlock **last_tb, int *tb_exit) { - uintptr_t ret; int32_t insns_left; trace_exec_tb(tb, tb->pc); - ret = cpu_tb_exec(cpu, tb); - tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - *tb_exit = ret & TB_EXIT_MASK; + tb = cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit != TB_EXIT_REQUESTED) { *last_tb = tb; return; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e3dc0cb4cb..56bb8db040 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2666,7 +2666,18 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) { - uintptr_t val = (uintptr_t)tb + idx; + /* + * Let the jit code return the read-only version of the + * TranslationBlock, so that we minimize the pc-relative + * distance of the address of the exit_tb code to TB. + * This will improve utilization of pc-relative address loads. + * + * TODO: Move this to translator_loop, so that all const + * TranslationBlock pointers refer to read-only memory. + * This requires coordination with targets that do not use + * the translator_loop. + */ + uintptr_t val = (uintptr_t)tcg_splitwx_to_rx((void *)tb) + idx; if (tb == NULL) { tcg_debug_assert(idx == 0); From patchwork Mon Dec 14 14:02:52 2020 Content-Type: text/plain; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/43] tcg/i386: Support split-wx code generation Date: Mon, 14 Dec 2020 08:02:52 -0600 Message-Id: <20201214140314.18544-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 04eefbfb90..2e57e95ac2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -231,6 +231,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7f74c77d7f..23c7a8a383 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -165,7 +165,7 @@ static bool have_lzcnt; # define have_lzcnt 0 #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) @@ -173,7 +173,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, value += addend; switch(type) { case R_386_PC32: - value -= (uintptr_t)code_ptr; + value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); if (value != (int32_t)value) { return false; } @@ -182,7 +182,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, tcg_patch32(code_ptr, value); break; case R_386_PC8: - value -= (uintptr_t)code_ptr; + value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); if (value != (int8_t)value) { return false; } @@ -1006,7 +1006,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } /* Try a 7 byte pc-relative lea before the 10 byte movq. */ - diff = arg - ((uintptr_t)s->code_ptr + 7); + diff = tcg_pcrel_diff(s, (const void *)arg) - 7; if (diff == (int32_t)diff) { tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); @@ -1615,7 +1615,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) tcg_out_branch(s, 1, dest); } -static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 0, dest); } @@ -1786,7 +1786,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { label->label_ptr[1] = label_ptr[1]; @@ -2280,7 +2281,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* jump displacement must be aligned for atomic patching; * see if we need to add extra nops before jump */ - gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4)); + gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; if (gap != 1) { tcg_out_nopn(s, gap - 1); } @@ -3825,11 +3826,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); From patchwork Mon Dec 14 14:02:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343544 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3045350jai; Mon, 14 Dec 2020 06:31:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJyfM8HNOx/0BQl9TBYtHjJ4YLJ7+2Ce+VYMM7n6OQZ954WF8ITk6eD7rGoVk0JcwCVxm1a0 X-Received: by 2002:ab0:7811:: with SMTP id x17mr22907744uaq.51.1607956269499; Mon, 14 Dec 2020 06:31:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956269; cv=none; d=google.com; s=arc-20160816; b=sx/g+qr3VLyn//pCwmyyLBefU7PcH9NDX+VxeW+AfA1IVP7PoaaMNjC8E24u1Rg/v2 QsSv77BGa2CqbCzjcBm8nznXPzaHOX1ccV5x5aGEp3nwWQ6cEwxKT8GTVa8hBfB6eeqT ++osEALyWUmQ43d2TK3ofhutLPRzI5P2+szIGH5cIMSs0+klj5VM8uXnmqIQstAJOx2K +Tb86y3vDczVu1oamWUk+UiZxyZjcnHfB9IYYAAwFto9Wkj2MfCsf7ipaXD1NqSpxNPo PWusg3kI0dpyFiRlC8IE0c9hetZOUhPlToTQ/4IO2D7FXd63EzsG6lNvTwgn4h9QEuYc 0a7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YKIoLTi5ySgzCVvhycZMdw7nP6Jv58IFUwkqltF23wU=; b=PaltkV7lMStFfTt/0rnH0Zyto7KZy8jRegnkE9OjI80qv6Or4ierQ+MBVgm8d3RT0f iDd8wO+GGuahTA99adq/x9+lDX5wZiZJr71fJ3ceIYdwpu5AdkPdduXIM2xNi3D9LeNo 3iIlH/dhG8y2orVDGiiPbE1SsBg9EHXJX5BjLtbxHdl6zLAzYZAcR9Z9hoAm3KFqSSyh 5gUrZBm/vlUkqiKHDJRM6KKMI6rHUdZ/oX8E4OofR3xhZbphm4RVJUCBSMwvD4OfpEAj ozvGVFaM5ChSOXEAAepSN3QIn3tyJJMqke1zppjG1d+iLqizW+45u9zN9f/1erwIJZVx LKVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NWB61TiI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/43] tcg/aarch64: Use B not BL for tcg_out_goto_long Date: Mon, 14 Dec 2020 08:02:53 -0600 Message-Id: <20201214140314.18544-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A typo generated a branch-and-link insn instead of plain branch. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fea784cf75..bd888bc66d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1317,7 +1317,7 @@ static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); + tcg_out_insn(s, 3206, B, offset); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); tcg_out_insn(s, 3207, BR, TCG_REG_TMP); From patchwork Mon Dec 14 14:02:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343536 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3039068jai; Mon, 14 Dec 2020 06:23:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJzCH0CPNFz0w0bGneqqfwkoXf1FcPdS+4oRX6HTXe+zw9mgfRx4nzqf4OObK1Os07cSiKx7 X-Received: by 2002:a25:c74e:: with SMTP id w75mr34869561ybe.520.1607955813759; Mon, 14 Dec 2020 06:23:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955813; cv=none; d=google.com; s=arc-20160816; b=cI8Yu86hxBp4ELT0OEt0HgPLkTT+LSvs/1rZRg2sNZF0sRV2v3iBZ+sM9aEfcbmNkR xHREv+tnOMrvD9IzTmaletEjOM4LOUVcn7di0FvTy7Tj4bi6kq4CpUApjHhAfs5nykEz w0nyZymbyPLcIOt1O6FVvC68xB6KL5qb6MAkcbE0XXNR9NCoIMqBCEMkRe2BEhpEnTEi O8m1S1ZNYdUMWv3Yoe6GJhFvJscZx64/GM3+rZ87Io4Rt4pJO5BEIWexP4QRlHLJfEVH GUDdt1mO4FrwBX4cPBgb1m+F16JVPZG5v9k3+lXdv0B/ojv8n0ksxkBuYuZRT/AZoaUG 7l0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qjl1QspWlOuJ+/D2vJaBwH05ftTGSnNZLxwMR0hFvkY=; b=ZIcgPT+evJ+/Oq0Y1fsebXyOBpexeCDOQGqPJ3zRMgwwbrzd893GIsnussPpg6oN3O iF4YqFNMt2mJg2lC5I4iTPdo9cv49CylaO2R7KORdwbZm/az8Du7pwWO8lfTQfx7pLJC FG3JktutsQVs3pTNjkmIgl3C/X0qL2Xo77ZBKMjXF5K1cPLtMsgFS4dMlNB61wqJ5c4J pqgx2B7GQkash/GP8N679UjdrLe7OcNDQaJ2zaEuqkyN2p4j7sWQ5niYghZu+uUd5xZf N8vdUhxA1e5Zr0KticMIIfZ4EPCEpMv90kRC1EU7tPhFujhG6c8xOIdjTsQYVR2/0yxZ 6bkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SLG3pl8I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 23/43] tcg/aarch64: Support split-wx code generation Date: Mon, 14 Dec 2020 08:02:54 -0600 Message-Id: <20201214140314.18544-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 57 ++++++++++++++++++++---------------- 2 files changed, 33 insertions(+), 26 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 92aefc32d3..81778e3a9c 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -154,6 +154,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bd888bc66d..2e33162c03 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -78,38 +78,42 @@ static const int tcg_target_call_oarg_regs[1] = { #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif -static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = target - code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = target - src_rx; + if (offset == sextract64(offset, 0, 26)) { /* read instruction, mask away previous PC_REL26 parameter contents, set the proper offset, then write back the instruction. */ - *code_ptr = deposit32(*code_ptr, 0, 26, offset); + *src_rw = deposit32(*src_rw, 0, 26, offset); return true; } return false; } -static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc19(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = target - code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = target - src_rx; + if (offset == sextract64(offset, 0, 19)) { - *code_ptr = deposit32(*code_ptr, 5, 19, offset); + *src_rw = deposit32(*src_rw, 5, 19, offset); return true; } return false; } -static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); switch (type) { case R_AARCH64_JUMP26: case R_AARCH64_CALL26: - return reloc_pc26(code_ptr, (tcg_insn_unit *)value); + return reloc_pc26(code_ptr, (const tcg_insn_unit *)value); case R_AARCH64_CONDBR19: - return reloc_pc19(code_ptr, (tcg_insn_unit *)value); + return reloc_pc19(code_ptr, (const tcg_insn_unit *)value); default: g_assert_not_reached(); } @@ -1050,12 +1054,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, /* Look for host pointer values within 4G of the PC. This happens often when loading pointers to QEMU's own data structures. */ if (type == TCG_TYPE_I64) { - tcg_target_long disp = value - (intptr_t)s->code_ptr; + intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); + tcg_target_long disp = value - src_rx; if (disp == sextract64(disp, 0, 21)) { tcg_out_insn(s, 3406, ADR, rd, disp); return; } - disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); + disp = (value >> 12) - (src_rx >> 12); if (disp == sextract64(disp, 0, 21)) { tcg_out_insn(s, 3406, ADRP, rd, disp); if (value & 0xfff) { @@ -1308,14 +1313,14 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; tcg_debug_assert(offset == sextract64(offset, 0, 26)); tcg_out_insn(s, 3206, B, offset); } -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, B, offset); } else { @@ -1329,9 +1334,9 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg) tcg_out_insn(s, 3207, BLR, reg); } -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { @@ -1393,7 +1398,7 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); offset = tcg_in32(s) >> 5; } else { - offset = l->u.value_ptr - s->code_ptr; + offset = tcg_pcrel_diff(s, l->u.value_ptr) >> 2; tcg_debug_assert(offset == sextract64(offset, 0, 19)); } @@ -1568,7 +1573,7 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) +static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) { ptrdiff_t offset = tcg_pcrel_diff(s, target); tcg_debug_assert(offset == sextract64(offset, 0, 21)); @@ -1581,7 +1586,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1606,7 +1611,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1631,7 +1636,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->type = ext; label->datalo_reg = data_reg; label->addrlo_reg = addr_reg; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1849,7 +1855,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #endif /* CONFIG_SOFTMMU */ } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], @@ -2894,11 +2900,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); /* Remove TCG locals stack space. */ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, From patchwork Mon Dec 14 14:02:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343516 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3032593jai; Mon, 14 Dec 2020 06:16:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJww5o6dGrZjc/t2WwbsUOcEo2peaFygUz7Hn/kFRQKou4WmjFfA1avxQm4ZxIXNWvhCgDxG X-Received: by 2002:a25:68cc:: with SMTP id d195mr33234389ybc.424.1607955364470; Mon, 14 Dec 2020 06:16:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955364; cv=none; d=google.com; s=arc-20160816; b=kpd07WQuXJHBz0/c5jDl9OWixSq2yIrp4+yN6FVkKvyGLYQ0DSjIrqL+552ioQXIQK oGPtgrZ65E9pbIojXXYbmHLBGcsvcTQiB+J+eX7geTh/Zp+0a7FijW4PgGisgKwMy8sl rGgkF7kYeXfk8kKnXeuJqzDXNcrPIWAkjJsqnCHyd061DRMlBGWBDSEVNbMXgirxbUIG SXtJlet0DapuRip0WyO8NX+1pYPsBH5fmZSKPihA9g3R5lbKd+4n+MAaw76M/wtgk47W zpvUyqm38+J2D39S1UuH+M+7uzI/k78QYQeaXc1q5NYEs+T1ue0Mh6la2yva/ScNfuNI flJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GhRqALWf9y48BIzmwb6ec/JDv3hDJBRmMXBLeIk5tow=; b=B8u9I6ynHEADTivzHylzYHPQTcLyZt37esZUfjv8Q/ZC2YL6u1JB1iFjb6UyOe9X8w meYNQOpDaAGxvq7XmxlpEVOQwzSGz8m3BrIagXcU9869OrCiStbBFUjvSLwQeBVmrM4f Hn46dxd+JzKWsNNeGNu/oBRHc0f2yO7eMtdk3rbby52EsqlkPVinFu4xgKiXxUfu6Lly OaRkAgUa5uyWZnE0whXkfm5/abAgqabUYveXEBCjBOWqetzIfX3kPuYqld9yBmJdDX9W 1Ya310PsG+Gfrw0f9H6F2R/zkwKlWqLrbJOxq15m7ESgrAP2VSJfAek3HZS8znLn5RKK AMug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gh0oVxRD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/43] disas: Push const down through host disasassembly Date: Mon, 14 Dec 2020 08:02:55 -0600 Message-Id: <20201214140314.18544-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/disas/dis-asm.h | 4 ++-- disas.c | 4 +--- disas/capstone.c | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joelle van Dyne diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 2164762b46..d1133a4e04 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -358,7 +358,7 @@ typedef struct disassemble_info { (bfd_vma addr, struct disassemble_info * info); /* These are for buffer_read_memory. */ - bfd_byte *buffer; + const bfd_byte *buffer; bfd_vma buffer_vma; int buffer_length; @@ -462,7 +462,7 @@ int print_insn_rx(bfd_vma, disassemble_info *); #ifdef CONFIG_CAPSTONE bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); -bool cap_disas_host(disassemble_info *info, void *code, size_t size); +bool cap_disas_host(disassemble_info *info, const void *code, size_t size); bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count); bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); #else diff --git a/disas.c b/disas.c index de1de7be94..a61f95b580 100644 --- a/disas.c +++ b/disas.c @@ -299,10 +299,8 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t size) } /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, const void *ccode, unsigned long size) +void disas(FILE *out, const void *code, unsigned long size) { - /* TODO: Push constness through the disas backends. */ - void *code = (void *)ccode; uintptr_t pc; int count; CPUDebug s; diff --git a/disas/capstone.c b/disas/capstone.c index 7462c0e305..20bc8f9669 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -229,7 +229,7 @@ bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size) } /* Disassemble SIZE bytes at CODE for the host. */ -bool cap_disas_host(disassemble_info *info, void *code, size_t size) +bool cap_disas_host(disassemble_info *info, const void *code, size_t size) { csh handle; const uint8_t *cbuf; From patchwork Mon Dec 14 14:02:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343504 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3024468jai; Mon, 14 Dec 2020 06:07:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJzuWnXZ7Y75l5J5yDP2IOEgYlU1emDabiSbL426brnu+8fDD1gmmAjYch24L9AiHSugLNp3 X-Received: by 2002:a67:f14f:: with SMTP id t15mr23190501vsm.0.1607954876479; Mon, 14 Dec 2020 06:07:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607954876; cv=none; d=google.com; s=arc-20160816; b=UJjPh6SIU62jG+Q/BurLNKQLaFXYYW5HY9yUh5rx2LH8ZGU8h7C38uAKaRrxRu/QQK qeR03Q/8GEhmQNP4HMI1mWW4C+15EpWuidk8GhBbXRofd/RYsa+fLLfEWIiz+dWjTRi8 PDT8IslZ9nyGpdGdQ/EPmapGP8cPkNvNHs0M69Te4c+g8BpchsAPrOwMwITyfvFYIscj Fc2boWQY8uixxxqJQ8ppP0cLw9joEw3x5vbWjOtxt5hk7Kz10oV1NdjCl5XDWdWjlA/n sh7MAuseY4uEGzmHTCSrUyFlzV9nPYgzAGewiLsy/PTZ/iyQGCRLv5Zdb47qjaFGrkjg PPwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oktQi4LY/JF34qnZTuyLsQ8kBIo/j/CH/m+PcKBIxn4=; b=oIQ9liiSf3mXIWM+qjAEqawoVrJHkOEEq+wYAaME0hp2M81rjzU4dtVWzqjvIjtnJ7 r1UKRGWemfY3anGj1K0aBbUIN1Ei6VBl8cue/P8rNdiZqpQj2neGuKoBKLCN04BBLKKh 581KqaS4IZF3i4Gi5kRVSaQsNd1c7VbmH0xp/FpocnSt8t7qR2aVXS9TewLTugmIrK2H IO8e//osqUZj8uvLI3eHvUIqvIz3l1tN/axl6UZx19Jk10sItv+f09/Y6Uo0X5RyaV7f sWeuGR9l77h1Us8h8wLlBxXk2+wjibv96fcmhsmkIPqk67iioC7SQwlgFNy/GCPma3Bw VAXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dxrkOMX4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/43] tcg/tci: Push const down through bytecode reading Date: Mon, 14 Dec 2020 08:02:56 -0600 Message-Id: <20201214140314.18544-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::344; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +++++++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/tci.c b/tcg/tci.c index 262a2b39ce..388c1dbee8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -163,34 +163,34 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) #endif /* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(uint8_t **tb_ptr) +static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { - tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr); + tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } /* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(uint8_t **tb_ptr) +static uint32_t tci_read_i32(const uint8_t **tb_ptr) { - uint32_t value = *(uint32_t *)(*tb_ptr); + uint32_t value = *(const uint32_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } /* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(uint8_t **tb_ptr) +static int32_t tci_read_s32(const uint8_t **tb_ptr) { - int32_t value = *(int32_t *)(*tb_ptr); + int32_t value = *(const int32_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } #if TCG_TARGET_REG_BITS == 64 /* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(uint8_t **tb_ptr) +static uint64_t tci_read_i64(const uint8_t **tb_ptr) { - uint64_t value = *(uint64_t *)(*tb_ptr); + uint64_t value = *(const uint64_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } @@ -198,7 +198,7 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); *tb_ptr += 1; @@ -206,7 +206,7 @@ tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { uint8_t value = tci_read_reg8(regs, **tb_ptr); *tb_ptr += 1; @@ -215,7 +215,7 @@ static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { int8_t value = tci_read_reg8s(regs, **tb_ptr); *tb_ptr += 1; @@ -224,7 +224,8 @@ static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) #endif /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint16_t value = tci_read_reg16(regs, **tb_ptr); *tb_ptr += 1; @@ -233,7 +234,8 @@ static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { int16_t value = tci_read_reg16s(regs, **tb_ptr); *tb_ptr += 1; @@ -242,7 +244,8 @@ static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_ptr) #endif /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t value = tci_read_reg32(regs, **tb_ptr); *tb_ptr += 1; @@ -251,14 +254,16 @@ static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t low = tci_read_r32(regs, tb_ptr); return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { int32_t value = tci_read_reg32s(regs, **tb_ptr); *tb_ptr += 1; @@ -266,7 +271,8 @@ static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint64_t value = tci_read_reg64(regs, **tb_ptr); *tb_ptr += 1; @@ -276,7 +282,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) /* Read indexed register(s) with target address from bytecode. */ static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { target_ulong taddr = tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS @@ -287,7 +293,7 @@ tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) /* Read indexed register or constant (native size) from bytecode. */ static tcg_target_ulong -tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r = **tb_ptr; @@ -301,7 +307,8 @@ tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t value; TCGReg r = **tb_ptr; @@ -316,14 +323,16 @@ static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t low = tci_read_ri32(regs, tb_ptr); return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint64_t value; TCGReg r = **tb_ptr; @@ -337,7 +346,7 @@ static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) } #endif -static tcg_target_ulong tci_read_label(uint8_t **tb_ptr) +static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { tcg_target_ulong label = tci_read_i(tb_ptr); tci_assert(label != 0); @@ -477,8 +486,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - /* TODO: Propagate const through this file. */ - uint8_t *tb_ptr = (uint8_t *)v_tb_ptr; + const uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); @@ -492,7 +500,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) TCGOpcode opc = tb_ptr[0]; #if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) uint8_t op_size = tb_ptr[1]; - uint8_t *old_code_ptr = tb_ptr; + const uint8_t *old_code_ptr = tb_ptr; #endif tcg_target_ulong t0; tcg_target_ulong t1; From patchwork Mon Dec 14 14:02:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343538 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3040199jai; Mon, 14 Dec 2020 06:24:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJztNg3VbyyMECezB1tBVkyVPGUvRYBLXZKHydbHRvpGRzRWCtrycaaKaxhYv7bu3I5W+b+4 X-Received: by 2002:a25:3897:: with SMTP id f145mr34400593yba.2.1607955898398; Mon, 14 Dec 2020 06:24:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955898; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/43] tcg: Introduce tcg_tbrel_diff Date: Mon, 14 Dec 2020 08:02:57 -0600 Message-Id: <20201214140314.18544-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 67d57695c2..90ec7c1445 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1141,6 +1141,19 @@ static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); } +/** + * tcg_tbrel_diff + * @s: the tcg context + * @target: address of the target + * + * Produce a difference, from the beginning of the current TB code + * to the destination address. + */ +static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) +{ + return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); +} + /** * tcg_current_code_size * @s: the tcg context From patchwork Mon Dec 14 14:02:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343543 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3044348jai; Mon, 14 Dec 2020 06:30:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMSDj4OPduqRzoukkutprz+P2EGRljtRcWX9HdOCetivx1dGz7oEkfObcFPvrR00BmMXVG X-Received: by 2002:a25:253:: with SMTP id 80mr10442873ybc.385.1607956212450; Mon, 14 Dec 2020 06:30:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956212; cv=none; d=google.com; s=arc-20160816; b=HyqrgdfUt9iDt/gkUEp/3VYZfLkGyQb2s7A3dx+56V3NxteEqUc24jXJJ+u/GeMr/J 4fKbxP2Kyb2Ful3biQ3yxkR28OdpinJVu5iIP38/7W3TNtV6Yf4QTdXgfOtOh5h5gUOR c/kZ/IhJF91aFp+qRFWfcxzG+3MWnF7EED0aKYlfSc+drr97J/aW+LXv9V+g3lmRnJy9 LIwwAbrJ9yWID53QMvgh6Z5viFzMblh5aV82yTTo995GS/6TQaX5cv4BF7uiE+qYNyn7 FRJKtjC0KQ/T3mLTstM/SCIlM/E5MINkR2XXT2l+MW/XjUDXATdNEJ3/TytLprz58Woo Jhfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qay0jNTmpyZq4ULzg3vkr0em7pJVaOqPAuzaBx5paoU=; b=MfMtIP29V1LKFlwngo11mngOA8n1qAW009/j/2EFhyiWeuKiYP57qtf1wmEODNZfFf SHuExK1z6s6u7tQrTVJ4tLGJT5J6LNdaQGyan1XON7XLU2AVI4SARIDQqQM5AUIwM4FX zedpBAtPtq9koCW4B1zTrnNicH5LcTOhxTrZ5bAFiClSYcUBUvHcM/kGfUGb08dZHCic DmHHV0vCAWGbKm/HADW7Um3tVF7lx6Bt0IhdwAUcxGKO0S6RxiYHh+QoG7ytJk46Teob fbRxBkXlDZmqvOuTrvVqrSMwBZUptQxnepx9eOc0ufBPv/T7PD2Jr8aHH+bKWkcukFDz KP7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WMMeYOtD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.03.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:03:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/43] tcg/ppc: Use tcg_tbrel_diff Date: Mon, 14 Dec 2020 08:02:58 -0600 Message-Id: <20201214140314.18544-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 0eb9c4ebe2..ed7a201578 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -837,7 +837,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Load addresses within the TB with one insn. */ - tb_diff = arg - (intptr_t)s->code_gen_ptr; + tb_diff = tcg_tbrel_diff(s, (void *)arg); if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); return; @@ -890,7 +890,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* Use the constant pool, if possible. */ if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } @@ -940,7 +940,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, */ if (USE_REG_TB) { rel = R_PPC_ADDR16; - add = -(intptr_t)s->code_gen_ptr; + add = tcg_tbrel_diff(s, NULL); } else { rel = R_PPC_ADDR32; add = 0; From patchwork Mon Dec 14 14:02:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343546 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3047745jai; Mon, 14 Dec 2020 06:34:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyACJRK9IzXJn4BFB2q2DYxLcTfmext9VT/HvKVP2hWycIVrYKHmCaM+gP71uHYexEVhhu2 X-Received: by 2002:a25:7083:: with SMTP id l125mr37746942ybc.250.1607956445078; Mon, 14 Dec 2020 06:34:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956445; cv=none; d=google.com; s=arc-20160816; b=C0ps7BUTNP0j3uqPLKX14BErS0PxPklSmDjdjrJUYxX3DZ2xD/v+hOJhIXvDl9TGy0 K2UPavgjr6iaDtsEWKLUW1NDkVDXjs3HWgsBYLpXE63HExrAA6lr6uQPTS+IJaglDFKE I+uWuqz5orzjJTYfzWPvNkmq6Adw8+s1ENAS3tLXedp83WgSPgR48cFTea8rRwLMeuq+ Hu3TGO+yoskVL3EGEvnfxxYZ6CJhGII9BNwqq28KteZ31PCXR11GPlr336akRtMoDsE2 eB9JchVZGnALvUTQhzDKcqQgTd5S+Fl+A4r3iFYA4xVIvZgCKYo3u+Pi54/ww+ZOc0T6 BWDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ASquR/6BxZoSVQzDtOnOXOHE8jLTrkcyVCDT0iJkP14=; b=F16Te1XNAUuH3yKUSNXTuJ+AyfJv1E3v8Orkyra5ZdlhrzgR4mUP1mH9ivr/ehTBCn IfsbJENkjC8bdPiohC4YGm8jGIpGbydxBwy0ltf0ZPmPZC1O4OCrhWRY0ljUzPSh173R KH8kzA3+DlI2r0gD5ltsNMAghKUZLdbHPDhX11P9IlLy6TKNRDu5m9Nscb5vqGyzr0Qg pdnhH8E7ihaxqc5KwpJ7aRikWTHgVR1S6W6QrgtIj3wRChw9YFNkGiLLMaYkLtyPF4/7 PWJBADUjBpI6AvibhYAdbLMuJcox20cYtgjOm5nYdyVM1I8ZQENM76/dD7hiH65nbmvG feDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z705s80x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/43] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB Date: Mon, 14 Dec 2020 08:02:59 -0600 Message-Id: <20201214140314.18544-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The maximum TB code gen size is UINT16_MAX, which the current code does not support. Use our utility function to optimally add an arbitrary constant. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index ed7a201578..1f8a446b90 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2392,9 +2392,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, set_jmp_reset_offset(s, args[0]); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ - c = -tcg_current_code_size(s); - assert(c == (int16_t)c); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); + tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); } break; case INDEX_op_goto_ptr: From patchwork Mon Dec 14 14:03:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343540 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3042372jai; Mon, 14 Dec 2020 06:27:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwNusvkuV/+fjlPF8yLrf+e9xYuuUViY24Qv2uoguxJf2mnd/dVkp/u5VFBatEojvswCJT X-Received: by 2002:a25:e0c3:: with SMTP id x186mr37557503ybg.431.1607956058458; Mon, 14 Dec 2020 06:27:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956058; cv=none; d=google.com; s=arc-20160816; b=TL3L4Ybin9+tTeRw6yzqouhNXJGY9emINjiaqTuc3Sf9TwxdMWxqnyVGJMzVaCk8FP byMNXISDSjEiJlc/x0LGDQCcpAW4wW2LSF2//Ij2Uk+xqigC7xh1RV8mwDaCn9eo/IMh 8AVoVu2oPnRBJevetsisUeVmg5NvAhDG/H6U8rhH0DbU5u9mjVhSSLsXoQX5u90cZmBk fGki4I40rbkcY2FAPZP3MUzEa0xXwgppY+wSg1niVvTsliRgJtoynMh9LRtfxxXCa9FE XoEis82UItYIBo0DQMUFh7TaH+6EBzEvWINOGxcfUn0zyRKBqwQxUgWl3nfM37JCG9uf 3xCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=etR78lk9NSenLd9LAIcHz8gvX9UzEYAUELnLLKVO9+E=; b=VQsOFWbfarlv5iHQjUO+JLOQ7JolQT0jr33vJROTEDWSL1HFK/MpzOQlHu/K7NihSp jmGPG/NC/G8+6mcKlZ+pN1Nu7ydGD8E4U8GAsx+C3IGF2hRHJ6pqroes5uy+/2wHvUrP bmzVss8DuT2dSheYOn8zVNkgONQkTzUa/q8zIu4hHcxU8ejmas1S6fOZ3qX8YpJWoURq zn71PUmQn7icqJq0k7MS79sulpqHn4BdWnmF51aDe731G0uJMXEAAbkdlXL8cf70uP6L LgGsY/wPpIg2GrAidt/rJsPDbyYVcXl/4EYbDEJsR4cl1IUSazLfDwrp2FtOOxHEveZp la2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hi8HltkA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/43] tcg/ppc: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:00 -0600 Message-Id: <20201214140314.18544-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 53 +++++++++++++++++++++++----------------- 2 files changed, 31 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 8fc2672bf0..b3361b8abc 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -184,6 +184,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1f8a446b90..33b5915005 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -62,8 +62,6 @@ #define TCG_CT_CONST_MONE 0x2000 #define TCG_CT_CONST_WSZ 0x4000 -static tcg_insn_unit *tb_ret_addr; - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -184,35 +182,41 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, const tcg_insn_unit *target) +static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); return disp & 0x3fffffc; } -static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); + if (in_range_b(disp)) { - *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); return true; } return false; } -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, const tcg_insn_unit *target) +static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); return disp & 0xfffc; } -static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); + if (disp == (int16_t) disp) { - *pc = (*pc & ~0xfffc) | (disp & 0xfffc); + *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); return true; } return false; @@ -673,12 +677,12 @@ static const uint32_t tcg_to_isel[] = { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_insn_unit *target; + const tcg_insn_unit *target; int16_t lo; int32_t hi; value += addend; - target = (tcg_insn_unit *)value; + target = (const tcg_insn_unit *)value; switch (type) { case R_PPC_REL14: @@ -1544,7 +1548,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) { if (l->has_value) { - bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr); + bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); } @@ -1997,7 +2001,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi_reg; label->addrlo_reg = addrlo_reg; label->addrhi_reg = addrhi_reg; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = lptr; } @@ -2007,7 +2012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -2055,7 +2060,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp s_bits = opc & MO_SIZE; TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -2306,10 +2311,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) int i; #ifdef _CALL_AIX - void **desc = (void **)s->code_ptr; - desc[0] = desc + 2; /* entry point */ - desc[1] = 0; /* environment pointer */ - s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ + const void **desc = (const void **)s->code_ptr; + desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ + desc[1] = 0; /* environment pointer */ + s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ #endif tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, @@ -2341,7 +2346,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - tcg_code_gen_epilogue = tb_ret_addr = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { @@ -2362,7 +2368,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out_b(s, 0, tb_ret_addr); + tcg_out_b(s, 0, tcg_code_gen_epilogue); break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { @@ -2410,7 +2416,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, uint32_t insn = B; if (l->has_value) { - insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr); + insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), + l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); } From patchwork Mon Dec 14 14:03:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343521 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3034804jai; Mon, 14 Dec 2020 06:18:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJzb8ciZhTcuje7B9PmJN7pKG6gLWMc6izSdLfDBLu5w2XtHyUOYMbQ64CY2/XEocsK//xW/ X-Received: by 2002:a25:d014:: with SMTP id h20mr38880283ybg.149.1607955520028; Mon, 14 Dec 2020 06:18:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955520; cv=none; d=google.com; s=arc-20160816; b=zfrC56weP5CdUdzlo2tZJlbubXBTk3uMSLK++iZeljGM7QKbUUfz/oveIKi0REz/xX jid0felnQq95zfuM+qkhOrKitULkJb8tZ4GgO1XMbNnqadfHG0HoDqNzZVMrHwgTOEEC P/eDOd2RBgeWgX+HncOFFaFzQiZIbrqaTcNbLowIOg5SI82iT7wLYPYjAKnz2YRcRSiw 8zMyqSktlwdd2J1oh6cz+oc/DwF+2aW6l6TWJ3UA7Bd67c4dFe6gwzcdmuVoA1ooElGR 0u7wpQ92dqUs8e7ol2rE2xQ3geIb37YF8DZqU3CTw1gdaGU4NC2mqI3U2J3QH4N81e/U nYbQ== ARC-Message-Signature: i=1; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/43] tcg/sparc: Use tcg_tbrel_diff Date: Mon, 14 Dec 2020 08:03:01 -0600 Message-Id: <20201214140314.18544-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index d599ae27b5..8f04fdf981 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -440,7 +440,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* A 13-bit constant relative to the TB. */ if (!in_prologue && USE_REG_TB) { - test = arg - (uintptr_t)s->code_gen_ptr; + test = tcg_tbrel_diff(s, (void *)arg); if (check_fit_ptr(test, 13)) { tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); return; @@ -537,15 +537,15 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } -static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) +static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, const void *arg) { - intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; + intptr_t diff = tcg_tbrel_diff(s, arg); if (USE_REG_TB && check_fit_ptr(diff, 13)) { tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); return; } - tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); - tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); + tcg_out_movi(s, TCG_TYPE_PTR, ret, (uintptr_t)arg & ~0x3ff); + tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff); } static inline void tcg_out_sety(TCGContext *s, TCGReg rs) @@ -1313,7 +1313,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi_imm13(s, TCG_REG_O0, a0); break; } else if (USE_REG_TB) { - intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; + intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); if (check_fit_ptr(tb_diff, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* Note that TCG_REG_TB has been unwound to O1. */ @@ -1345,8 +1345,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } else { /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_TB, - (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_ld_ptr(s, TCG_REG_TB, s->tb_jmp_target_addr + a0); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); tcg_out_nop(s); } From patchwork Mon Dec 14 14:03:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343506 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3027190jai; Mon, 14 Dec 2020 06:10:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJyHLcYR661lQKAvYFVhBn+4izczyf8ZJB7MEoZ/yC2lFcZFUI+mBU6X029kGCh4L91Y0lmF X-Received: by 2002:a25:8545:: with SMTP id f5mr32540137ybn.112.1607955034507; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/43] tcg/sparc: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:02 -0600 Message-Id: <20201214140314.18544-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 2 +- tcg/sparc/tcg-target.c.inc | 24 +++++++++++++----------- 2 files changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 21e7e2f56f..54b9da9aeb 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -171,6 +171,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 8f04fdf981..182124b96c 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -291,14 +291,15 @@ static inline int check_fit_i32(int32_t val, unsigned int bits) # define check_fit_ptr check_fit_i32 #endif -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) { - uint32_t insn = *code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + uint32_t insn = *src_rw; intptr_t pcrel; value += addend; - pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); switch (type) { case R_SPARC_WDISP16: @@ -315,7 +316,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, g_assert_not_reached(); } - *code_ptr = insn; + *src_rw = insn; return true; } @@ -868,8 +869,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } #ifdef CONFIG_SOFTMMU -static tcg_insn_unit *qemu_ld_trampoline[16]; -static tcg_insn_unit *qemu_st_trampoline[16]; +static const tcg_insn_unit *qemu_ld_trampoline[16]; +static const tcg_insn_unit *qemu_st_trampoline[16]; static void emit_extend(TCGContext *s, TCGReg r, int op) { @@ -930,7 +931,7 @@ static void build_trampolines(TCGContext *s) while ((uintptr_t)s->code_ptr & 15) { tcg_out_nop(s); } - qemu_ld_trampoline[i] = s->code_ptr; + qemu_ld_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr); if (SPARC64 || TARGET_LONG_BITS == 32) { ra = TCG_REG_O3; @@ -958,7 +959,7 @@ static void build_trampolines(TCGContext *s) while ((uintptr_t)s->code_ptr & 15) { tcg_out_nop(s); } - qemu_st_trampoline[i] = s->code_ptr; + qemu_st_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr); if (SPARC64) { emit_extend(s, TCG_REG_O2, i); @@ -1038,7 +1039,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); @@ -1163,7 +1165,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; - tcg_insn_unit *func; + const tcg_insn_unit *func; tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, @@ -1245,7 +1247,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; - tcg_insn_unit *func; + const tcg_insn_unit *func; tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, From patchwork Mon Dec 14 14:03:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343548 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3049737jai; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/43] tcg/s390: Use tcg_tbrel_diff Date: Mon, 14 Dec 2020 08:03:03 -0600 Message-Id: <20201214140314.18544-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 1444914428..e4c61fc014 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -630,7 +630,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } } else if (USE_REG_TB && !in_prologue) { - ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; + ptrdiff_t off = tcg_tbrel_diff(s, (void *)sval); if (off == sextract64(off, 0, 20)) { /* This is certain to be an address within TB, and therefore OFF will be negative; don't try RX_LA. */ @@ -655,7 +655,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } else if (USE_REG_TB && !in_prologue) { tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, sval, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { TCGReg base = ret ? ret : TCG_TMP0; tcg_out_insn(s, RIL, LARL, base, 0); @@ -746,7 +746,7 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) } } if (USE_REG_TB) { - ptrdiff_t disp = abs - (void *)s->code_gen_ptr; + ptrdiff_t disp = tcg_tbrel_diff(s, abs); if (disp == sextract64(disp, 0, 20)) { tcg_out_ld(s, type, dest, TCG_REG_TB, disp); return; @@ -956,7 +956,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); return; } } else { @@ -1015,7 +1015,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } else if (USE_REG_TB) { tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit @@ -1050,7 +1050,7 @@ static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } else if (USE_REG_TB) { tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { /* Perform the xor by parts. */ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); @@ -1108,12 +1108,12 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, op = (is_unsigned ? RXY_CLY : RXY_CY); tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, - 4 - (intptr_t)s->code_gen_ptr); + 4 - tcg_tbrel_diff(s, NULL)); } else { op = (is_unsigned ? RXY_CLG : RXY_CG); tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, c2, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } goto exit; } else { From patchwork Mon Dec 14 14:03:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343550 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3050746jai; Mon, 14 Dec 2020 06:37:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJyIVFREFSjMZZWwtw5oY+7cvuPuE+rL5Qjj/9x141M85hWhG66E69Cka3fd7HPjd1gUUexf X-Received: by 2002:a25:4081:: with SMTP id n123mr27391274yba.237.1607956660695; Mon, 14 Dec 2020 06:37:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956660; cv=none; d=google.com; s=arc-20160816; b=wg+Nkt/aNEaRaN8Ezl2THG99MRp0aA6g87JmRgNIlEbhGq+6fW+DoGqoplK0/zSIhW jVQUe3Ud/jMbP6Td3F+Q9rZ9fc3zDnt4cnuC1Ogc18/NIRs3dvOy38QupeIV12GmT+ty Z9jIO2lF8ECwXDr2wZYUFeVwr6s7EqhK3VOgoohkyG5SppEaO+5iT32KOqGPaLyeHqf0 4SQAkreSvXh5TNV1WWIz73xXbVUQH5spw9poYL1afvMXF1ovKEEVBI0WO+Qny+KiemVH cokoDB/yFYYsFRUq9UCFydJHmGoFCCKxYqwSUrKr8fv55AUMBmIiXwyFplJ+k9sLrtF3 +rlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dcqt/mgICWsadeLmqExwcaSBKbyWpQDlM1YBo4lkUJg=; b=zDgyLrdCmWG1lcCU8UKUfQ8eLdUEoJGTrnoF4IV0cNCL0f4a6AxKfHkslj8rESwzA6 7AFxkuluI5ETSg452YLEdFpH88r72nWk8h+U39dOSF42NyNsCwn1KKsUU9uvWmvTGWrZ ZG0PMo6vxBBpjFVWQU0oJXSYvtdzWIIP4xrD99NrVQQJYW5B+zUVYznnV5dDYtmODIWJ CXCMZpCumxsHc8UJULEWBpU8CRsJBv3IxnrZ3CsgfEgpBkga1NTMmYF6fuS7vnYD4QTr vSifbvkYdSDjRqW6X7KEwWYzermu9zj6eAUigUhHL6Sox93tXOz/GvkEZffD4oiEv6GG O3Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J4FKI4XM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/43] tcg/s390: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:04 -0600 Message-Id: <20201214140314.18544-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.c.inc | 69 +++++++++++++++++---------------------- 2 files changed, 31 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index fed3329e51..fc65f42650 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -158,6 +158,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index e4c61fc014..582a8ef941 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -363,36 +363,37 @@ static void * const qemu_st_helpers[16] = { }; #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) { + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); intptr_t pcrel2; uint32_t old; value += addend; - pcrel2 = (tcg_insn_unit *)value - code_ptr; + pcrel2 = (tcg_insn_unit *)value - src_rx; switch (type) { case R_390_PC16DBL: if (pcrel2 == (int16_t)pcrel2) { - tcg_patch16(code_ptr, pcrel2); + tcg_patch16(src_rw, pcrel2); return true; } break; case R_390_PC32DBL: if (pcrel2 == (int32_t)pcrel2) { - tcg_patch32(code_ptr, pcrel2); + tcg_patch32(src_rw, pcrel2); return true; } break; case R_390_20: if (value == sextract64(value, 0, 20)) { - old = *(uint32_t *)code_ptr & 0xf00000ff; + old = *(uint32_t *)src_rw & 0xf00000ff; old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); + tcg_patch32(src_rw, old); return true; } break; @@ -730,7 +731,8 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, } /* load data from an absolute host address */ -static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) +static void tcg_out_ld_abs(TCGContext *s, TCGType type, + TCGReg dest, const void *abs) { intptr_t addr = (intptr_t)abs; @@ -1304,7 +1306,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) { - ptrdiff_t off = dest - s->code_ptr; + ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; if (off == (int16_t)off) { tcg_out_insn(s, RI, BRC, cc, off); } else if (off == (int32_t)off) { @@ -1333,34 +1335,18 @@ static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, TCGReg r1, TCGReg r2, TCGLabel *l) { - intptr_t off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); - tcg_out16(s, off); + tcg_out16(s, 0); tcg_out16(s, cc << 12 | (opc & 0xff)); } static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, TCGReg r1, int i2, TCGLabel *l) { - tcg_target_long off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); - tcg_out16(s, off); + tcg_out16(s, 0); tcg_out16(s, (i2 << 8) | (opc & 0xff)); } @@ -1417,7 +1403,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { - ptrdiff_t off = dest - s->code_ptr; + ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; if (off == (int32_t)off) { tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); } else { @@ -1601,7 +1587,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->oi = oi; label->datalo_reg = data; label->addrlo_reg = addr; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1613,7 +1600,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } @@ -1638,7 +1625,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } @@ -1766,7 +1753,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: a0 = args[0]; if (s->tb_jmp_insn_offset) { - /* branch displacement must be aligned for atomic patching; + /* + * branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch */ if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { @@ -1779,7 +1767,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } else { /* load address stored at s->tb_jmp_target_addr + a0 */ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, - s->tb_jmp_target_addr + a0); + tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0)); /* and go there */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); } @@ -1789,8 +1777,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCG_REG_TB to the beginning of this TB. */ if (USE_REG_TB) { int ofs = -tcg_current_code_size(s); - assert(ofs == (int16_t)ofs); - tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); + /* All TB are restricted to 64KiB by unwind info. */ + tcg_debug_assert(ofs == sextract64(ofs, 0, 20)); + tcg_out_insn(s, RXY, LAY, TCG_REG_TB, + TCG_REG_TB, TCG_REG_NONE, ofs); } break; @@ -2561,11 +2551,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, From patchwork Mon Dec 14 14:03:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343519 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3034748jai; Mon, 14 Dec 2020 06:18:36 -0800 (PST) X-Google-Smtp-Source: ABdhPJzPyiwRKRcA8CODhXpSgO2dg1Q+CvbHgxh//Qn0YElvtkZBvIEf0DI0Ne+5v8oas7D9nPax X-Received: by 2002:a25:afca:: with SMTP id d10mr34591011ybj.508.1607955516537; Mon, 14 Dec 2020 06:18:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955516; cv=none; d=google.com; s=arc-20160816; b=T9NaRNSHt7FtfpigTrK2TnOvgf3MxKuQxBpjl/L9jmMjoM8waCHr9oV3Rg0WXLwKah zsVl+AWvSm6mA3uMAVivsKMJqXmyvcWSaE7D4/ASV09kqYdnlBHX50tb5ZzcphQl3glY dp3OlyfyL5lMmlTJxF1rh7lZsm058c7r7+Ui/MrNTV3oWxOv9eV9xmB2xdBfX7IpN97t dLkhsM2BoIi0pYYTi0aVFT7+800WQbciNRlLVto7MiIcdLdNmz1ODX6tRis/IB+BzzvT vM+hfoXuLpzH8NiJ4Lo703iyS0olcxWwnDWTeGqgWk+/r0+65/sT265bGYbqa7L3ij2O 8/Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cOhvs0ghq8muGX3iEeRtFXrjJiLy3u5yfl5gf+ftseU=; b=1Kn6EbMqd5iSBNPK7SRGPmyLx2V6WhsnQU8U+Ww2zPJ4xgR8XqwyYgpakofPkGu9kN MigaIEED78+lvpgDlTZDDv3S5OMSpk6PQP1yxLTuad5SsENoinFzE14f3dA5lAYPzz9h a/TFpRxNVTWE6d6mw6yZ4rkuL2mcPJK3/ZjJgWO2d7GvJL8Tb90WLWI8HUeLdKclPl3v +g+m/kGa0g5ufh1cqNte1HxNko9jDlOZ5af6Tay0B8FCWpd0/xwq6LLAPKxo1TvGRebU wwvn9fykQCCxGSyVFjHnuFodSkHLNWXT34VKZgmmyweLIgkf8B3ZQZvw8yUrcOf9hSzI vOCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DugRX87t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/43] tcg/riscv: Fix branch range checks Date: Mon, 14 Dec 2020 08:03:05 -0600 Message-Id: <20201214140314.18544-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The offset even checks were folded into the range check incorrectly. By offsetting by 1, and not decrementing the width, we silently allowed out of range branches. Assert that the offset is always even instead. Move tcg_out_goto down into the CONFIG_SOFTMMU block so that it is not unused. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 025e3cd0bb..195c3eff03 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -429,7 +429,8 @@ static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - if (offset == sextreg(offset, 1, 12) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 12)) { code_ptr[0] |= encode_sbimm12(offset); return true; } @@ -441,7 +442,8 @@ static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - if (offset == sextreg(offset, 1, 20) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 20)) { code_ptr[0] |= encode_ujimm20(offset); return true; } @@ -854,28 +856,21 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, g_assert_not_reached(); } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); -} - static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); int ret; - if (offset == sextreg(offset, 1, 20) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS == 32 || - offset == sextreg(offset, 1, 31) << 1) { + } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); - ret = reloc_call(s->code_ptr - 2, arg);\ + ret = reloc_call(s->code_ptr - 2, arg); tcg_debug_assert(ret == true); } else if (TCG_TARGET_REG_BITS == 64) { /* far jump: 64-bit */ @@ -962,6 +957,13 @@ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); +static void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +{ + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); + bool ok = reloc_jimm20(s->code_ptr - 1, target); + tcg_debug_assert(ok); +} + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) From patchwork Mon Dec 14 14:03:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343545 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3046203jai; Mon, 14 Dec 2020 06:32:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJz8kSyl/+q4S19OPGAh1goK3dY3IZprZdByR9BxovDHiMTuZtCrD/r4y325c6C78U0VR3Nf X-Received: by 2002:a25:e6c2:: with SMTP id d185mr16504319ybh.304.1607956326247; Mon, 14 Dec 2020 06:32:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956326; cv=none; d=google.com; s=arc-20160816; b=RObtFMxkajtEw0k1MoDZMJHwgti0Kb2V97/99pC2SxPO3Zkpm19ux0dP0zua1Wr5Rd 2vsaXkli6cEOaxQQ0cJ9faXicqRi1n2LCTmmPqmM2L00yzfhBG/jT1uZEZnxeAnVSAZv jhFyd4rJR5C/Y79FmdL1qgC7X0HD8J1+WTJ7cbwR4zSkvleFLn/i76w3u6mUzr0Gfm48 CaxuKPq2o1bo+fi+Ty5Nn6JaGAw4xuL4MWU34PXaPnmlxWUkHMn7viYHn3k7VAq/ZW3n PnarBlJzTyiyHg8ZyjvihcVXFVHoShDDcNVn9JvoVePzUKK2mKP/bGhLh1spw8p/CE8p YspA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LiVRLDdLRLwNh3EAfOwsqGZsrXFOtm3LiOx00UdIraE=; b=WNPtB8AIv5MMP4plHvJIRKPlUFty1t1HGwwttcA5qBWY3Io5UaJiLsvipLNPwJxd0k gq1qOW5x3PdefpOEF7G8ANKHj1xaiPCLi7ao0bBOJ7pQ0jqhF1yz6llqdaxGC9mHJY15 X3Vhh4/MrUo1DQLlZBvVAeIJFqlxDCLnuOkdrJTtqrFEzzw+DBVCe+zN3UxKCjvTTSJh YVHbvI+EYJ+wsDUd0+HQI/Q1aOl5Ve5X0N5ws13RDsREQPhnOOPWEExtEVxFyWUOTGv/ 5S8XHY4r2B9gIxZQpzn9/X8fUGkN4agSSWctTeTMhHCaiWacykJccBWyWcwTNdz6Jxga OBYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yp539SXc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/43] tcg/riscv: Remove branch-over-branch fallback Date: Mon, 14 Dec 2020 08:03:06 -0600 Message-Id: <20201214140314.18544-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since 7ecd02a06f8, we are prepared to re-start code generation with a smaller TB if a relocation is out of range. We no longer need to leave a nop in the stream Just In Case. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 56 ++++---------------------------------- 1 file changed, 6 insertions(+), 50 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 195c3eff03..02beb86977 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -469,43 +469,16 @@ static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - uint32_t insn = *code_ptr; - intptr_t diff; - bool short_jmp; - tcg_debug_assert(addend == 0); - switch (type) { case R_RISCV_BRANCH: - diff = value - (uintptr_t)code_ptr; - short_jmp = diff == sextreg(diff, 0, 12); - if (short_jmp) { - return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); - } else { - /* Invert the condition */ - insn = insn ^ (1 << 12); - /* Clear the offset */ - insn &= 0x01fff07f; - /* Set the offset to the PC + 8 */ - insn |= encode_sbimm12(8); - - /* Move forward */ - code_ptr[0] = insn; - - /* Overwrite the NOP with jal x0,value */ - diff = value - (uintptr_t)(code_ptr + 1); - insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); - code_ptr[1] = insn; - - return true; - } - break; + return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); case R_RISCV_JAL: return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); case R_RISCV_CALL: return reloc_call(code_ptr, (tcg_insn_unit *)value); default: - tcg_abort(); + g_assert_not_reached(); } } @@ -779,21 +752,8 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, arg2 = t; } - if (l->has_value) { - intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); - if (diff == sextreg(diff, 0, 12)) { - tcg_out_opc_branch(s, op, arg1, arg2, diff); - } else { - /* Invert the conditional branch. */ - tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); - } - } else { - tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); - tcg_out_opc_branch(s, op, arg1, arg2, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); - } + tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); + tcg_out_opc_branch(s, op, arg1, arg2, 0); } static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, @@ -1009,8 +969,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, /* Compare masked address with the TLB entry. */ label_ptr[0] = s->code_ptr; tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); /* TLB Hit - translate address using addend. */ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { @@ -1054,8 +1012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { + if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { return false; } @@ -1089,8 +1046,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { + if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { return false; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/43] tcg/riscv: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:07 -0600 Message-Id: <20201214140314.18544-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 41 +++++++++++++++++++++----------------- 2 files changed, 24 insertions(+), 19 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 785fe37f9b..60b6a1a3fc 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -170,6 +170,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 02beb86977..5c1e0f8fc1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -425,41 +425,44 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) * Relocations */ -static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; tcg_debug_assert((offset & 1) == 0); if (offset == sextreg(offset, 0, 12)) { - code_ptr[0] |= encode_sbimm12(offset); + *src_rw |= encode_sbimm12(offset); return true; } return false; } -static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; tcg_debug_assert((offset & 1) == 0); if (offset == sextreg(offset, 0, 20)) { - code_ptr[0] |= encode_ujimm20(offset); + *src_rw |= encode_ujimm20(offset); return true; } return false; } -static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) +static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; int32_t lo = sextreg(offset, 0, 12); int32_t hi = offset - lo; if (offset == hi + lo) { - code_ptr[0] |= encode_uimm20(hi); - code_ptr[1] |= encode_imm12(lo); + src_rw[0] |= encode_uimm20(hi); + src_rw[1] |= encode_imm12(lo); return true; } @@ -532,7 +535,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, if (tmp == (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); - ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); + ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); tcg_debug_assert(ret == true); return; } @@ -917,7 +920,7 @@ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); -static void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); bool ok = reloc_jimm20(s->code_ptr - 1, target); @@ -993,7 +996,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; } @@ -1012,7 +1016,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1046,7 +1050,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1232,7 +1236,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) @@ -1780,11 +1784,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], TCG_REG_SP, SAVE_OFS + i * REG_SIZE); From patchwork Mon Dec 14 14:03:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343551 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3052746jai; Mon, 14 Dec 2020 06:40:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJzqW0JeFm9tzX9EpRr40buxn+WFZAhOEBoBtPstqzdTvx3+ToazAOmzZ9AhoMnTWiE5psUD X-Received: by 2002:a25:3d7:: with SMTP id 206mr38381937ybd.31.1607956804803; Mon, 14 Dec 2020 06:40:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956804; cv=none; d=google.com; s=arc-20160816; b=E18T8rzDm5c5ENq5foBjeka/FZawwtjnWQcepLV5OdSNKZB8lNHAwZvumyeVXj2lH6 SeInAi2NmrV7skOtQNqJHL1YnqzBi7APxXdJhCVB8qPMa3pFwM6Tqx8ofLRS7pDlC4z2 EbeUf1hJhN7uEWcy2xRL3VHu0xKKgM3sGtC/Ms9rnc9BXA3oUOGXJEWlC/703ylNMMIF WxVyVXl9sDJmDtY5a4h6IUwx+LTsiY8Xs9l7S6SBjnW1+P/4Yo7bCFz6gxrYV/nOJU+1 IxtwvF7J+bZVd9JgMVZVRXwd0x68JRjGvhbsdeIIOB5Ru6wPI5qEz54GfbHX1mlmw3yB u2Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vrSqwZKXMyaSyRVRtm4Hh+vS+LTe1orOUMFlnbJhADM=; b=fpUDHqFmluGkh9LpfUqLipJyBy5m9ZKG9hN9QeZ77MG5KRDFsXwegKSSrR67ZaiBgw nou8FT6KnHagtU/xFh7o7RmgOuzrKusdSxmvPMamJy5bMJqcwrjEcU5C9kefL4ME51Hn xlIEBuRU7j8rZkRoB+mOxawuQeb89Z5i6KZ7NOWc6M+jgh8ifLuKoTR52yMdbxvQTEtS ouK7Z0IKUtZEj4LO6rMeSNkjahlvk9F+zk6MWoue91gDcGhwq8rp3DShvzSFij0yNNHP jpqkEHgqT8I/Syjtgt9+syEgAUi8JkGMI0loAkIK7mnlK/sAJBdF1zwhTIgHNh1PEAqZ 7O2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZTrJ9csE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/43] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd Date: Mon, 14 Dec 2020 08:03:08 -0600 Message-Id: <20201214140314.18544-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::344; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Re-use the 256MiB region handling from alloc_code_gen_buffer_anon, and replace that with the shared file mapping. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 46 ++++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 17df6c94fa..b49aaf1026 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1137,24 +1137,40 @@ static bool alloc_code_gen_buffer_anon(size_t size, int prot, static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) { - void *buf_rw, *buf_rx; + void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; +#ifdef __mips__ + /* Find space for the RX mapping, vs the 256MiB regions. */ + if (!alloc_code_gen_buffer_anon(size, PROT_NONE, + MAP_PRIVATE | MAP_ANONYMOUS | + MAP_NORESERVE, errp)) { + return false; + } + /* The size of the mapping may have been adjusted. */ + size = tcg_ctx->code_gen_buffer_size; + buf_rx = tcg_ctx->code_gen_buffer; +#endif + buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw == NULL) { - return false; + goto fail; } +#ifdef __mips__ + void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, + MAP_SHARED | MAP_FIXED, fd, 0); + if (tmp != buf_rx) { + goto fail_rx; + } +#else buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx == MAP_FAILED) { - error_setg_errno(errp, errno, - "failed to map shared memory for execute"); - munmap(buf_rw, size); - close(fd); - return false; + goto fail_rx; } - close(fd); +#endif + close(fd); tcg_ctx->code_gen_buffer = buf_rw; tcg_ctx->code_gen_buffer_size = size; tcg_splitwx_diff = buf_rx - buf_rw; @@ -1163,6 +1179,20 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) qemu_madvise(buf_rw, size, QEMU_MADV_HUGEPAGE); qemu_madvise(buf_rx, size, QEMU_MADV_HUGEPAGE); return true; + + fail_rx: + error_setg_errno(errp, errno, "failed to map shared memory for execute"); + fail: + if (buf_rx != MAP_FAILED) { + munmap(buf_rx, size); + } + if (buf_rw) { + munmap(buf_rw, size); + } + if (fd >= 0) { + close(fd); + } + return false; } #endif /* CONFIG_POSIX */ From patchwork Mon Dec 14 14:03:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343515 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3032277jai; Mon, 14 Dec 2020 06:15:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiJRZeKPSm6Yg7W7lPQ+A2QE4x2zNHgegjwvJ2WhBYVMlKsNdF7+vJ9z+RgZRoz+p37R9f X-Received: by 2002:a25:4686:: with SMTP id t128mr35857299yba.109.1607955348192; Mon, 14 Dec 2020 06:15:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955348; cv=none; d=google.com; s=arc-20160816; b=E0hDqVl035NiX2LEu505cWrClziIApWtmR8XsPvsx1ZsJURf3VB/+0/+iesr/TaSlm pYByt7P+8fwy61qeqMgbEHaOh24yk1MEdCxkPJlf2ziCCT6Cj/ug5LMm4sk6eQR8Am+p GCVVha6imkyK75dSwYIZ5/rQfK6h6R5weUSIpASTQl5oi36xG5FphmQj+0wefBF3YyF3 RUsOUuXk9j8s3lLQpjjBYb9hktZcwusXfdTohhWdZhHsHU/TEhtFZeRRsgFBlVQLtZEA ualy3NFzoIG9HfGflSlMz6Ox82om5aQ0EWkeK/52GB87xwGQ/w5NCCJasHDkg3MpyO6D qTcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9/TRkK1ohPG7NzFVdGar1E3FliGdhxt5t+NNXefLhVw=; b=dzE91XjmDQzNzDT0A4ZgxgCbx8eY9J/YkDFN8yEJ4w+gLdcvAl6qxard+4xt5P5V+2 JUYSiOU+BXRDAW1iPg3Js1cM3F088XNKDMnmnkGDU5Q/VMRW4hqTGSYTVSmiTixbFf7a E6cOe3qOc4hVeYVhmCQypNuEUW7Mjb74UwMCKD7Evh4TbmRLngCgHxV94jcIlK4yXm8I gMKHtLqVuSnQiqgbuY69NFb9+MZvlwxSnsS6vy7rjoOK6QJAbHSduiD6Gg4hA3SOcadt 4Zigl5XW5FYTG07mkkfjVTw0dRjzzhYU7NTEqlznpg8/rmG+mmjOFRukg21uX6bgG8a8 k+Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MZYjn4RB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 38/43] tcg/mips: Do not assert on relocation overflow Date: Mon, 14 Dec 2020 08:03:09 -0600 Message-Id: <20201214140314.18544-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This target was not updated with 7ecd02a06f8, and so did not allow re-compilation with relocation overflow. Remove reloc_26 and reloc_26_val as unused. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 53 ++++++++++++++------------------------- 1 file changed, 19 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 52638e920c..37faf1356c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -144,29 +144,15 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, - const tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); - tcg_debug_assert(disp == (int16_t)disp); - return disp & 0xffff; -} - -static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); -} - -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); - return ((uintptr_t)target >> 2) & 0x3ffffff; -} - -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); + if (disp == (int16_t)disp) { + *pc = deposit32(*pc, 0, 16, disp); + return true; + } + return false; } static bool patch_reloc(tcg_insn_unit *code_ptr, int type, @@ -174,8 +160,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, { tcg_debug_assert(type == R_MIPS_PC16); tcg_debug_assert(addend == 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); - return true; + return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); } #define TCG_CT_CONST_ZERO 0x100 @@ -925,11 +910,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, } tcg_out_opc_br(s, b_opc, arg1, arg2); - if (l->has_value) { - reloc_pc16(s->code_ptr - 1, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); - } + tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); tcg_out_nop(s); } @@ -1316,9 +1297,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS + && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + return false; } i = 1; @@ -1346,7 +1328,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); - reloc_pc16(s->code_ptr - 1, l->raddr); + if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { + return false; + } /* delay slot */ if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { @@ -1366,9 +1350,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS + && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + return false; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/43] tcg/mips: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:10 -0600 Message-Id: <20201214140314.18544-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 43 ++++++++++++++++++++++----------------- 2 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d6dff897bf..c200ac02ea 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -200,7 +200,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 37faf1356c..a2201bd1dd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -139,17 +139,18 @@ static const TCGReg tcg_target_call_oarg_regs[2] = { TCG_REG_V1 }; -static tcg_insn_unit *tb_ret_addr; -static tcg_insn_unit *bswap32_addr; -static tcg_insn_unit *bswap32u_addr; -static tcg_insn_unit *bswap64_addr; +static const tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *bswap32_addr; +static const tcg_insn_unit *bswap32u_addr; +static const tcg_insn_unit *bswap64_addr; -static bool reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ - ptrdiff_t disp = target - (pc + 1); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = target - (src_rx + 1); if (disp == (int16_t)disp) { - *pc = deposit32(*pc, 0, 16, disp); + *src_rw = deposit32(*src_rw, 0, 16, disp); return true; } return false; @@ -505,7 +506,7 @@ static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) { uintptr_t dest = (uintptr_t)target; - uintptr_t from = (uintptr_t)s->code_ptr + 4; + uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; int32_t inst; /* The pc-region branch happens within the 256MB region of @@ -617,7 +618,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) +static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); tcg_debug_assert(ok); @@ -1282,7 +1283,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { label->label_ptr[1] = label_ptr[1]; @@ -1291,15 +1293,16 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { + const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); TCGMemOpIdx oi = l->oi; MemOp opc = get_memop(oi); TCGReg v0; int i; /* resolve label address */ - if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + if (!reloc_pc16(l->label_ptr[0], tgt_rx) || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } @@ -1344,15 +1347,16 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { + const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); TCGMemOpIdx oi = l->oi; MemOp opc = get_memop(oi); MemOp s_bits = opc & MO_SIZE; int i; /* resolve label address */ - if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + if (!reloc_pc16(l->label_ptr[0], tgt_rx) || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } @@ -2469,11 +2473,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], TCG_REG_SP, SAVE_OFS + i * REG_SIZE); @@ -2493,7 +2498,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. */ - bswap32_addr = align_code_ptr(s); + bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t3 = (ssss)d000 */ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); /* t1 = 000a */ @@ -2521,7 +2526,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. */ - bswap32u_addr = align_code_ptr(s); + bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t1 = (0000)000d */ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); /* t3 = 000a */ @@ -2547,7 +2552,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap64 -- 64-bit swap. a0 = abcdefgh */ - bswap64_addr = align_code_ptr(s); + bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t3 = h0000000 */ tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); /* t1 = 0000000a */ From patchwork Mon Dec 14 14:03:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343547 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3048300jai; Mon, 14 Dec 2020 06:34:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJw13SZMYzPOthETRBgCMpDGzpGqMbKCJcGrzRlI0RECdgrhxkICPHUsH/rNOw45VYU+id+l X-Received: by 2002:a25:4f0a:: with SMTP id d10mr36245985ybb.100.1607956482089; Mon, 14 Dec 2020 06:34:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956482; cv=none; d=google.com; s=arc-20160816; b=irmk2ibiBRrZ4/NeCMR1UUdneOMUGlAhB4cnHngCL7cAmFEu26Tbsz50EpF0ILw6FB 4TXG2+xFqIbZUmA2h2Q/3cpailQdGVY10GmSdr0/GK22/RdjKiD713Pmnwn61bcuAJ+d x0nv7uSlVj5kO7+qv+0uYBbghqTRNuM8J8YmRt7o6K0ljuUWfXQqnO2MzxhY10AwihKX wZnBjDf/fZrI0Si2vsttwstmTuvyVhwORkmdDErzQ8rv8bNpL1WWlEUP8S30vVTPT6Xo rpG/7Vm8/vbNAL0OWp8R/5VfFuporqtCD/zIMwQ4l6vMVlr9qTwEs3ON0t1+08PxAcMi Q6CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=746olrr4Rbmh5ZNHTyxNWXv98LGv+Z4R3bTpMGSCzAU=; b=dWq4jZ/9WnzzmMAKELD8sENhBhSQbwvTXA4GEpLsL/WH58GekCwtpNACIHgMCZhgzm 5VzjF3WTzKeaCH2BX4wRV+7YshHFQNRgZy9WtujDzRiCTXU63tkx5CNi2pHc9xduv2n3 Jx13xoN1l2XPEdrJMF4lHLkaeAb6qOYuuW4pdqrRx3kM3+Gsp8tJFGH+/Y9sbXhUBA2U Hge/9G6o4X9+WeQoUoIpU56KrS0fiFNDsfZ19HEA8S2fMskxeesWqNP10gYhaOuglPzz HcbjXxZwvZ9NETRbp83rnt/kyrQOabzDjU9b7VbIfjHm7U/EXXxTbe7AsABPg9vAZ/xz zqcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uFZRB6fh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 40/43] tcg/arm: Support split-wx code generation Date: Mon, 14 Dec 2020 08:03:11 -0600 Message-Id: <20201214140314.18544-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 37 +++++++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 7e04755428..856d6dd4b0 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,6 +141,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9b9400f164..3d2717aeb0 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -187,29 +187,32 @@ static const uint8_t tcg_cond_to_arm_cond[] = { [TCG_COND_GTU] = COND_HI, }; -static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; + if (offset == sextract32(offset, 0, 24)) { - *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + *src_rw = deposit32(*src_rw, 0, 24, offset); return true; } return false; } -static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; if (offset >= -0xfff && offset <= 0xfff) { - tcg_insn_unit insn = *code_ptr; + tcg_insn_unit insn = *src_rw; bool u = (offset >= 0); if (!u) { offset = -offset; } insn = deposit32(insn, 23, 1, u); insn = deposit32(insn, 0, 12, offset); - *code_ptr = insn; + *src_rw = insn; return true; } return false; @@ -221,9 +224,9 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, tcg_debug_assert(addend == 0); if (type == R_ARM_PC24) { - return reloc_pc24(code_ptr, (tcg_insn_unit *)value); + return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); } else if (type == R_ARM_PC13) { - return reloc_pc13(code_ptr, (tcg_insn_unit *)value); + return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); } else { g_assert_not_reached(); } @@ -617,7 +620,7 @@ static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) /* Check for a pc-relative address. This will usually be the TB, or within the TB, which is immediately before the code block. */ - diff = arg - ((intptr_t)s->code_ptr + 8); + diff = tcg_pcrel_diff(s, (void *)arg) - 8; if (diff >= 0) { rot = encode_imm(diff); if (rot >= 0) { @@ -1337,7 +1340,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1348,7 +1352,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); void *func; - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1411,7 +1415,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; MemOp opc = get_memop(oi); - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1762,8 +1766,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGReg base = TCG_REG_PC; tcg_debug_assert(s->tb_jmp_insn_offset == 0); - ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]); - dif = ptr - ((intptr_t)s->code_ptr + 8); + ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + args[0]); + dif = tcg_pcrel_diff(s, (void *)ptr) - 8; dil = sextract32(dif, 0, 12); if (dif != dil) { /* The TB is close, but outside the 12 bits addressable by @@ -2297,7 +2301,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } From patchwork Mon Dec 14 14:03:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343531 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3036973jai; Mon, 14 Dec 2020 06:21:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyj+Zs8/p8yYbwW7jgTbQK9hf4Qstja5Vs1USFuyUytvRRYiSHgdMQrVrDSn6cceP3dILGy X-Received: by 2002:a25:107:: with SMTP id 7mr21219187ybb.337.1607955665425; Mon, 14 Dec 2020 06:21:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607955665; cv=none; d=google.com; s=arc-20160816; b=YAPorpxZawT9j5eOk8Hvb+KWalyFGf32JF+UVoGurfRYAOlFSx58o7apwd/BdJRDns Pu7oxo4UMVtRXb/c+r2TI/Ifcc5rl6i9cygHkMBvHW+dXQYfg9XWyiJ2v8YbLEZimcO/ ir34fcDP3k209qFpsdSwkMP918XTvkh2+m9rt1QdKkpDcSqfCPp+leK60+u7IEeIjxNM YrpPif5a6FTDHXYrn/0i/Wmut1tmU0aevZcNMiBYxf135QZ7CGSrHUfhA5+l0frDHWZk W8cSm4yrPmUDgSYSX4vJQ26neG9ruBLRt1HOLxXowK6yA6/xFtzlCqdJ0Tz1YkkP+irT Q7RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qmq9iNdZ5Znmtjd43X4+7pjV8Eyd2wTluaWBrB9Hxcc=; b=SbxEkrrDqdR9rCITcPoi/oEaxfdBnhqIHxnkpmjPTc81CGNQngR+dRlVHYzkiw4q// tuY1zSnQXNL1e/itjWgqyVTpe2shmFEa9py/IxkTdyxs5A5ZqEMfr7GSD1diRd++4YUD 7UftDjiv3BG0nAQmAwVCEwRkD2K3pTxS1KAiSEKh2TLKanaNSbDezi+DrsRojI5gyp6R 5Lhzlc+Xi0wM3x3lDel5j8yALWmXdNWGqkIRf0Z0zsPRT4T9kkZ94Yul5usue14W6HDE OqoFc4FWPfnv4ikoWllEufgVP+ZNSCHYP8/WsSEu2gInZfyNHwWPLfLM6Fyl5WtjB53k ofQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wrfKBOPk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 41/43] tcg: Remove TCG_TARGET_SUPPORT_MIRROR Date: Mon, 14 Dec 2020 08:03:12 -0600 Message-Id: <20201214140314.18544-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 1 - accel/tcg/translate-all.c | 16 +++++++++------- 10 files changed, 9 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 81778e3a9c..6ba248f447 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -154,6 +154,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 856d6dd4b0..6ca4537ca6 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,6 +141,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2e57e95ac2..0dcaed7fe6 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -231,6 +231,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c200ac02ea..d23baf7cda 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -200,7 +200,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 1 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index b3361b8abc..c41d10142b 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -184,6 +184,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 60b6a1a3fc..3d0745c70c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -170,6 +170,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index fc65f42650..3750952598 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -158,6 +158,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 54b9da9aeb..9c15c91d39 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -171,6 +171,5 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 768153fd02..fcec2e70db 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -197,7 +197,6 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 0 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b49aaf1026..21a20fed42 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1132,6 +1132,7 @@ static bool alloc_code_gen_buffer_anon(size_t size, int prot, return true; } +#ifndef CONFIG_TCG_INTERPRETER #ifdef CONFIG_POSIX #include "qemu/memfd.h" @@ -1254,17 +1255,18 @@ static bool alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp) return true; } #endif /* CONFIG_DARWIN */ +#endif /* CONFIG_TCG_INTERPRETER */ static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) { - if (TCG_TARGET_SUPPORT_MIRROR) { -#ifdef CONFIG_DARWIN - return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +#ifndef CONFIG_TCG_INTERPRETER +# ifdef CONFIG_DARWIN + return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +# endif +# ifdef CONFIG_POSIX + return alloc_code_gen_buffer_splitwx_memfd(size, errp); +# endif #endif -#ifdef CONFIG_POSIX - return alloc_code_gen_buffer_splitwx_memfd(size, errp); -#endif - } error_setg(errp, "jit split-wx not supported"); return false; } From patchwork Mon Dec 14 14:03:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343535 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3038618jai; Mon, 14 Dec 2020 06:22:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJzTF9BjZsLXSHsWdbklojAuuuChzSbqgG/mRcN/q8V3RE/RPyM5E7pwGlAxQBq5i4KEtzlr X-Received: by 2002:a25:3b47:: with SMTP id i68mr3532976yba.159.1607955779022; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 42/43] tcg: Constify tcg_code_gen_epilogue Date: Mon, 14 Dec 2020 08:03:13 -0600 Message-Id: <20201214140314.18544-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::344; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, make this pointer const. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc | 3 +-- tcg/mips/tcg-target.c.inc | 3 +-- tcg/ppc/tcg-target.c.inc | 3 +-- tcg/riscv/tcg-target.c.inc | 3 +-- tcg/s390/tcg-target.c.inc | 3 +-- tcg/sparc/tcg-target.c.inc | 3 +-- 10 files changed, 10 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 90ec7c1445..477919aeb6 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -677,7 +677,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; -extern void *tcg_code_gen_epilogue; +extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; extern TCGv_env cpu_env; diff --git a/tcg/tcg.c b/tcg/tcg.c index 5f585c2ed2..d961ebcecb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -161,7 +161,7 @@ static int tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; -void *tcg_code_gen_epilogue; +const void *tcg_code_gen_epilogue; uintptr_t tcg_splitwx_diff; #ifndef CONFIG_TCG_INTERPRETER diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 2e33162c03..0b7eb09a27 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2900,8 +2900,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3d2717aeb0..d6cb19ca9f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2301,8 +2301,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 23c7a8a383..be57d2330a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3826,8 +3826,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a2201bd1dd..18fd474593 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2473,8 +2473,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 33b5915005..5f191c03d9 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2346,8 +2346,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5c1e0f8fc1..7b4ee4a084 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1784,8 +1784,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 582a8ef941..b3660ffedf 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2551,8 +2551,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 182124b96c..922ae96481 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1039,8 +1039,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); From patchwork Mon Dec 14 14:03:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 343549 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3050608jai; Mon, 14 Dec 2020 06:37:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxuVtHYZHQGapVmT/sFLLU+LvrDMWIh+L/Xl7D3qXHpNKRVMN72Gx0CSHUwVPJxQHru+GOE X-Received: by 2002:a25:1f82:: with SMTP id f124mr26878446ybf.175.1607956651439; Mon, 14 Dec 2020 06:37:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607956651; cv=none; d=google.com; s=arc-20160816; b=FZ0BssxCnMPK5K2q4YGUAHDKfVb/D2jPcsxTOG8kE4cVyM1uPnwU0fDkXnV8LmA7Gl jeGCJ0fNFMt9kM/N8mPR58CGfVqSVywsTu3rJEwrcIkjwo855JQ8xxJkkOVaSKjLBkjH rUd+8pBa7oeKUyTUX4LvYR/6h6MwuG1o4a9YPSUikHSnR3jph1MbDrepM7NzHm7dnbSj 5Gg0Q0RNu5DObUPszM1niIRhwqJjebVxneFz3nwGQWTFwrRqyYaABsF20BzahK6Jr67b 1eUTTp/VGj6diQwACfzvDCBzH3tc/ju/opexILaw8W6AAx53LCKyr5q9h3ayr0tnbDab niyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=N6wN/s3cc8J4fe6ZTQ6/bUXQAJNTNrqoJE7CR9wrYBA=; b=IsZmUVWZXdnPem/wOklMo/uAPDbIyTz5/9nSMdTvyxlrQrrCKvMkuH3qotrl9tHh1F HJkt4/rh1G6guSMttogyzAXyma49xEnz5pnp2K9OJBNWl5PJWFeHNpSO8OfvBBBDJrwJ oNbVTfapNGTdsb1mcDgvIkYPI91lSzBER4zBDEELqe7eQK5Y/q4ZJ4UJ4ERB5WyPDIxb t04Bu07YCa28mo0UoB1fMXBIhJGIeLLKVMF96CblaLnr3nMBPNZidKCfbzvbed5NaEFB 57fFILzU2h7f/mHd7P54LnKSWDbeaI2huf+HomssVwih3zrR2RtHshBQt8BMJaaTTqiA Mp8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DxdpOyKK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id t24sm3940146oou.4.2020.12.14.06.04.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 06:04:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 43/43] tcg: Constify TCGLabelQemuLdst.raddr Date: Mon, 14 Dec 2020 08:03:14 -0600 Message-Id: <20201214140314.18544-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214140314.18544-1-richard.henderson@linaro.org> References: <20201214140314.18544-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, make this pointer const. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc | 3 +-- tcg/mips/tcg-target.c.inc | 3 +-- tcg/ppc/tcg-target.c.inc | 3 +-- tcg/riscv/tcg-target.c.inc | 3 +-- tcg/s390/tcg-target.c.inc | 3 +-- tcg/tcg-ldst.c.inc | 2 +- 8 files changed, 8 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: Joelle van Dyne diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 0b7eb09a27..ab199b143f 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1636,8 +1636,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->type = ext; label->datalo_reg = data_reg; label->addrlo_reg = addr_reg; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index d6cb19ca9f..0fd1126454 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1340,8 +1340,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index be57d2330a..18a3af53bb 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1786,8 +1786,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { label->label_ptr[1] = label_ptr[1]; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 18fd474593..add157f6c3 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1283,8 +1283,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { label->label_ptr[1] = label_ptr[1]; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5f191c03d9..19a4a12f15 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2001,8 +2001,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi_reg; label->addrlo_reg = addrlo_reg; label->addrhi_reg = addrhi_reg; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = lptr; } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7b4ee4a084..f48a028dac 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -996,8 +996,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index b3660ffedf..d7ef079055 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1587,8 +1587,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->oi = oi; label->datalo_reg = data; label->addrlo_reg = addr; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 05f9b3ccd6..c3ce88e69d 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -28,7 +28,7 @@ typedef struct TCGLabelQemuLdst { TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ - tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; } TCGLabelQemuLdst;