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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:10 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:08:56 +0000 Message-Id: <20180206170903.30637-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 1/8] ARM: VGIC: drop unneeded gic_restore_pending_irqs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In gic_restore_pending_irqs() we push our pending virtual IRQs into the list registers. This function is called once from gic_inject(), just before we return to the guest, but also in gic_restore_state(), when we context-switch a VCPU. Having a closer look it turns out that the later call is not needed, since we will always call gic_inject() anyway. So remove that call (and the forward declaration) to streamline this interface and make separating the GIC from the VGIC world later. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bac8ada2bb..721a17a9d7 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,8 +36,6 @@ #include #include -static void gic_restore_pending_irqs(struct vcpu *v); - static DEFINE_PER_CPU(uint64_t, lr_mask); #define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) @@ -91,8 +89,6 @@ void gic_restore_state(struct vcpu *v) gic_hw_ops->restore_state(v); isb(); - - gic_restore_pending_irqs(v); } /* desc->irq needs to be disabled before calling this function */ From patchwork Tue Feb 6 17:08:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127064 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107992ljc; Tue, 6 Feb 2018 09:11:43 -0800 (PST) X-Google-Smtp-Source: AH8x2256ohGKcBcKDI20B37IkxAEqw7gQS4F9VaGE03bYdLOKGodlRCuylc/2R8PsWQXQFOapRIL X-Received: by 10.36.118.21 with SMTP id z21mr3966648itb.116.1517937102906; Tue, 06 Feb 2018 09:11:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937102; cv=none; d=google.com; s=arc-20160816; b=xxQSJTtIt2fRRG7c7drtQJtDzowfqhJgKxxyE7bLGrsXgyonbQYoxZcs7q1t4g/WAn VUwQJFjb+Tk07eQeNuWUWV7PHQSp1JV3K3sisBmWFxwod+pUDMmooo/p3CMiliBT5mZh Z41KaAjj/AguVz6eF8Rky2NexWb3Ciz+Tf2hyM5P8SymfMi846aLq81DQgE8sgKbdjwq drty4bHVeKLhMOSTtAm6cLNdNZFi9aNm3zhKkKesOQlLmLGHPLLflfg5dMskAcwpBdly ioZojFUVoDgZO1yq6ga4p+D0Js4eJw5k5x49/OWUU3FqNBI13mfX/rpSp58M4guggsm/ Aixg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=h4eUgWn3nY2ojln65no62/i4zEquHuU8DuDVyIlsp/k=; b=JIyifac2QoWDNfxpJrsigNI7407jEWUl1Yo+l6PCPPRpVtCAe8X1FtMuSZOZTlyeO5 a+jjtks3BaqUfh8qDN62PW8nLgINiaswS7pRASdwBQAqPECwY2jN6hH/7ZVolNUHdBI5 zF4jjqiNm4835xrHB2DnLHkZcglod699JHEtHeTfj6O2jI2T363CgsWXDkKlYIX163sb CWaowBR0gF5Dh010jZVlsP+kH/uXnwXg1OXAhk33ypzKJWgXL7A3STcaQBKGTifcZQub pBGqG1MZQv91qGJRSl8QlTZN2m5twfWZc48fjMCe/X1rqi3Q5Nef+Mbst7bAzT+z0EaW ruRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ChDojVRV; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:11 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:08:57 +0000 Message-Id: <20180206170903.30637-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 2/8] ARM: VGIC: split gic.c to observe hardware/virtual GIC separation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic.c holds code to handle hardware IRQs as well as code to bridge VGIC requests to the GIC virtualization hardware. Despite being named gic.c, this file reaches into the VGIC and uses data structures describing virtual IRQs. To improve abstraction, move the VGIC functions into a separate file, so that gic.c does what it says on the tin. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/Makefile | 1 + xen/arch/arm/gic-vgic.c | 396 ++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 363 +----------------------------------------- xen/include/asm-arm/gic.h | 3 + 4 files changed, 402 insertions(+), 361 deletions(-) create mode 100644 xen/arch/arm/gic-vgic.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 30a2a6500a..41d7366527 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,6 +16,7 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o +obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c new file mode 100644 index 0000000000..74d8ea7c96 --- /dev/null +++ b/xen/arch/arm/gic-vgic.c @@ -0,0 +1,396 @@ +/* + * xen/arch/arm/gic-vgic.c + * + * ARM Generic Interrupt Controller virtualization support + * + * Tim Deegan + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) + +#undef GIC_DEBUG + +static void gic_update_one_lr(struct vcpu *v, int i); + +static inline void gic_set_lr(int lr, struct pending_irq *p, + unsigned int state) +{ + ASSERT(!local_irq_is_enabled()); + + clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); + + gic_hw_ops->update_lr(lr, p, state); + + set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + p->lr = lr; +} + +static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) +{ + struct pending_irq *iter; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( !list_empty(&n->lr_queue) ) + return; + + list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) + { + if ( iter->priority > n->priority ) + { + list_add_tail(&n->lr_queue, &iter->lr_queue); + return; + } + } + list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); +} + +void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + list_del_init(&p->lr_queue); +} + +void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) +{ + struct pending_irq *n = irq_to_pending(v, virtual_irq); + + /* If an LPI has been removed meanwhile, there is nothing left to raise. */ + if ( unlikely(!n) ) + return; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + /* Don't try to update the LR if the interrupt is disabled */ + if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) + return; + + if ( list_empty(&n->lr_queue) ) + { + if ( v == current ) + gic_update_one_lr(v, n->lr); + } +#ifdef GIC_DEBUG + else + gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", + virtual_irq, v->domain->domain_id, v->vcpu_id); +#endif +} + +/* + * Find an unused LR to insert an IRQ into, starting with the LR given + * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to + * avoid inserting the same IRQ twice. This situation can occur when an + * event gets discarded while the LPI is in an LR, and a new LPI with the + * same number gets mapped quickly afterwards. + */ +static unsigned int gic_find_unused_lr(struct vcpu *v, + struct pending_irq *p, + unsigned int lr) +{ + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + unsigned int used_lr; + + for_each_set_bit(used_lr, lr_mask, nr_lrs) + { + gic_hw_ops->read_lr(used_lr, &lr_val); + if ( lr_val.virq == p->irq ) + return used_lr; + } + } + + lr = find_next_zero_bit(lr_mask, nr_lrs, lr); + + return lr; +} + +void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, + unsigned int priority) +{ + int i; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + struct pending_irq *p = irq_to_pending(v, virtual_irq); + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(!p) ) + /* An unmapped LPI does not need to be raised. */ + return; + + if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) + { + i = gic_find_unused_lr(v, p, 0); + + if (i < nr_lrs) { + set_bit(i, &this_cpu(lr_mask)); + gic_set_lr(i, p, GICH_LR_PENDING); + return; + } + } + + gic_add_to_lr_pending(v, p); +} + +static void gic_update_one_lr(struct vcpu *v, int i) +{ + struct pending_irq *p; + int irq; + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + ASSERT(!local_irq_is_enabled()); + + gic_hw_ops->read_lr(i, &lr_val); + irq = lr_val.virq; + p = irq_to_pending(v, irq); + /* + * An LPI might have been unmapped, in which case we just clean up here. + * If that LPI is marked as PRISTINE, the information in the LR is bogus, + * as it belongs to a previous, already unmapped LPI. So we discard it + * here as well. + */ + if ( unlikely(!p || + test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + ASSERT(is_lpi(irq)); + + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + return; + } + + if ( lr_val.state & GICH_LR_ACTIVE ) + { + set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) + { + if ( p->desc == NULL ) + { + lr_val.state |= GICH_LR_PENDING; + gic_hw_ops->write_lr(i, &lr_val); + } + else + gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); + } + } + else if ( lr_val.state & GICH_LR_PENDING ) + { + int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); +#ifdef GIC_DEBUG + if ( q ) + gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); +#endif + } + else + { + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + if ( p->desc != NULL ) + clear_bit(_IRQ_INPROGRESS, &p->desc->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + p->lr = GIC_INVALID_LR; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && + !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + gic_raise_guest_irq(v, irq, p->priority); + else { + list_del_init(&p->inflight); + /* + * Remove from inflight, then change physical affinity. It + * makes sure that when a new interrupt is received on the + * next pcpu, inflight is already cleared. No concurrent + * accesses to inflight. + */ + smp_wmb(); + if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + { + struct vcpu *v_target = vgic_get_target_vcpu(v, irq); + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); + clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); + } + } + } +} + +void gic_clear_lrs(struct vcpu *v) +{ + int i = 0; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + + /* The idle domain has no LRs to be cleared. Since gic_restore_state + * doesn't write any LR registers for the idle domain they could be + * non-zero. */ + if ( is_idle_vcpu(v) ) + return; + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), + nr_lrs, i)) < nr_lrs ) { + gic_update_one_lr(v, i); + i++; + } + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +static void gic_restore_pending_irqs(struct vcpu *v) +{ + int lr = 0; + struct pending_irq *p, *t, *p_r; + struct list_head *inflight_r; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + int lrs = nr_lrs; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + if ( list_empty(&v->arch.vgic.lr_pending) ) + goto out; + + inflight_r = &v->arch.vgic.inflight_irqs; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + { + lr = gic_find_unused_lr(v, p, lr); + if ( lr >= nr_lrs ) + { + /* No more free LRs: find a lower priority irq to evict */ + list_for_each_entry_reverse( p_r, inflight_r, inflight ) + { + if ( p_r->priority == p->priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && + !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) + goto found; + } + /* We didn't find a victim this time, and we won't next + * time, so quit */ + goto out; + +found: + lr = p_r->lr; + p_r->lr = GIC_INVALID_LR; + set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); + gic_add_to_lr_pending(v, p_r); + inflight_r = &p_r->inflight; + } + + gic_set_lr(lr, p, GICH_LR_PENDING); + list_del_init(&p->lr_queue); + set_bit(lr, &this_cpu(lr_mask)); + + /* We can only evict nr_lrs entries */ + lrs--; + if ( lrs == 0 ) + break; + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +void gic_clear_pending_irqs(struct vcpu *v) +{ + struct pending_irq *p, *t; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + v->arch.lr_mask = 0; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + gic_remove_from_lr_pending(v, p); +} + +int gic_events_need_delivery(void) +{ + struct vcpu *v = current; + struct pending_irq *p; + unsigned long flags; + const unsigned long apr = gic_hw_ops->read_apr(0); + int mask_priority; + int active_priority; + int rc = 0; + + mask_priority = gic_hw_ops->read_vmcr_priority(); + active_priority = find_next_bit(&apr, 32, 0); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + /* TODO: We order the guest irqs by priority, but we don't change + * the priority of host irqs. */ + + /* find the first enabled non-active irq, the queue is already + * ordered by priority */ + list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) + { + if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) + goto out; + if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + rc = 1; + goto out; + } + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + return rc; +} + +void gic_inject(void) +{ + ASSERT(!local_irq_is_enabled()); + + gic_restore_pending_irqs(current); + + if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 721a17a9d7..04e6d66b69 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,15 +36,11 @@ #include #include -static DEFINE_PER_CPU(uint64_t, lr_mask); - -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +DEFINE_PER_CPU(uint64_t, lr_mask); #undef GIC_DEBUG -static void gic_update_one_lr(struct vcpu *v, int i); - -static const struct gic_hw_operations *gic_hw_ops; +const struct gic_hw_operations *gic_hw_ops; void register_gic_ops(const struct gic_hw_operations *ops) { @@ -366,361 +362,6 @@ void gic_disable_cpu(void) gic_hw_ops->disable_interface(); } -static inline void gic_set_lr(int lr, struct pending_irq *p, - unsigned int state) -{ - ASSERT(!local_irq_is_enabled()); - - clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - - gic_hw_ops->update_lr(lr, p, state); - - set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); - p->lr = lr; -} - -static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) -{ - struct pending_irq *iter; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( !list_empty(&n->lr_queue) ) - return; - - list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) - { - if ( iter->priority > n->priority ) - { - list_add_tail(&n->lr_queue, &iter->lr_queue); - return; - } - } - list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); -} - -void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) -{ - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - list_del_init(&p->lr_queue); -} - -void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) -{ - struct pending_irq *n = irq_to_pending(v, virtual_irq); - - /* If an LPI has been removed meanwhile, there is nothing left to raise. */ - if ( unlikely(!n) ) - return; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - /* Don't try to update the LR if the interrupt is disabled */ - if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) - return; - - if ( list_empty(&n->lr_queue) ) - { - if ( v == current ) - gic_update_one_lr(v, n->lr); - } -#ifdef GIC_DEBUG - else - gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", - virtual_irq, v->domain->domain_id, v->vcpu_id); -#endif -} - -/* - * Find an unused LR to insert an IRQ into, starting with the LR given - * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to - * avoid inserting the same IRQ twice. This situation can occur when an - * event gets discarded while the LPI is in an LR, and a new LPI with the - * same number gets mapped quickly afterwards. - */ -static unsigned int gic_find_unused_lr(struct vcpu *v, - struct pending_irq *p, - unsigned int lr) -{ - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - unsigned int used_lr; - - for_each_set_bit(used_lr, lr_mask, nr_lrs) - { - gic_hw_ops->read_lr(used_lr, &lr_val); - if ( lr_val.virq == p->irq ) - return used_lr; - } - } - - lr = find_next_zero_bit(lr_mask, nr_lrs, lr); - - return lr; -} - -void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, - unsigned int priority) -{ - int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - struct pending_irq *p = irq_to_pending(v, virtual_irq); - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(!p) ) - /* An unmapped LPI does not need to be raised. */ - return; - - if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) - { - i = gic_find_unused_lr(v, p, 0); - - if (i < nr_lrs) { - set_bit(i, &this_cpu(lr_mask)); - gic_set_lr(i, p, GICH_LR_PENDING); - return; - } - } - - gic_add_to_lr_pending(v, p); -} - -static void gic_update_one_lr(struct vcpu *v, int i) -{ - struct pending_irq *p; - int irq; - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - ASSERT(!local_irq_is_enabled()); - - gic_hw_ops->read_lr(i, &lr_val); - irq = lr_val.virq; - p = irq_to_pending(v, irq); - /* - * An LPI might have been unmapped, in which case we just clean up here. - * If that LPI is marked as PRISTINE, the information in the LR is bogus, - * as it belongs to a previous, already unmapped LPI. So we discard it - * here as well. - */ - if ( unlikely(!p || - test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - ASSERT(is_lpi(irq)); - - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - return; - } - - if ( lr_val.state & GICH_LR_ACTIVE ) - { - set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) - { - if ( p->desc == NULL ) - { - lr_val.state |= GICH_LR_PENDING; - gic_hw_ops->write_lr(i, &lr_val); - } - else - gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); - } - } - else if ( lr_val.state & GICH_LR_PENDING ) - { - int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); -#ifdef GIC_DEBUG - if ( q ) - gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); -#endif - } - else - { - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - if ( p->desc != NULL ) - clear_bit(_IRQ_INPROGRESS, &p->desc->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - p->lr = GIC_INVALID_LR; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && - !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - gic_raise_guest_irq(v, irq, p->priority); - else { - list_del_init(&p->inflight); - /* - * Remove from inflight, then change physical affinity. It - * makes sure that when a new interrupt is received on the - * next pcpu, inflight is already cleared. No concurrent - * accesses to inflight. - */ - smp_wmb(); - if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - { - struct vcpu *v_target = vgic_get_target_vcpu(v, irq); - irq_set_affinity(p->desc, cpumask_of(v_target->processor)); - clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); - } - } - } -} - -void gic_clear_lrs(struct vcpu *v) -{ - int i = 0; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - - /* The idle domain has no LRs to be cleared. Since gic_restore_state - * doesn't write any LR registers for the idle domain they could be - * non-zero. */ - if ( is_idle_vcpu(v) ) - return; - - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), - nr_lrs, i)) < nr_lrs ) { - gic_update_one_lr(v, i); - i++; - } - - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -static void gic_restore_pending_irqs(struct vcpu *v) -{ - int lr = 0; - struct pending_irq *p, *t, *p_r; - struct list_head *inflight_r; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - int lrs = nr_lrs; - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - if ( list_empty(&v->arch.vgic.lr_pending) ) - goto out; - - inflight_r = &v->arch.vgic.inflight_irqs; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - { - lr = gic_find_unused_lr(v, p, lr); - if ( lr >= nr_lrs ) - { - /* No more free LRs: find a lower priority irq to evict */ - list_for_each_entry_reverse( p_r, inflight_r, inflight ) - { - if ( p_r->priority == p->priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && - !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) - goto found; - } - /* We didn't find a victim this time, and we won't next - * time, so quit */ - goto out; - -found: - lr = p_r->lr; - p_r->lr = GIC_INVALID_LR; - set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); - gic_add_to_lr_pending(v, p_r); - inflight_r = &p_r->inflight; - } - - gic_set_lr(lr, p, GICH_LR_PENDING); - list_del_init(&p->lr_queue); - set_bit(lr, &this_cpu(lr_mask)); - - /* We can only evict nr_lrs entries */ - lrs--; - if ( lrs == 0 ) - break; - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -void gic_clear_pending_irqs(struct vcpu *v) -{ - struct pending_irq *p, *t; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - v->arch.lr_mask = 0; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - gic_remove_from_lr_pending(v, p); -} - -int gic_events_need_delivery(void) -{ - struct vcpu *v = current; - struct pending_irq *p; - unsigned long flags; - const unsigned long apr = gic_hw_ops->read_apr(0); - int mask_priority; - int active_priority; - int rc = 0; - - mask_priority = gic_hw_ops->read_vmcr_priority(); - active_priority = find_next_bit(&apr, 32, 0); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - /* TODO: We order the guest irqs by priority, but we don't change - * the priority of host irqs. */ - - /* find the first enabled non-active irq, the queue is already - * ordered by priority */ - list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) - { - if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) - goto out; - if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - { - rc = 1; - goto out; - } - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return rc; -} - -void gic_inject(void) -{ - ASSERT(!local_irq_is_enabled()); - - gic_restore_pending_irqs(current); - - if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); -} - static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) { /* Lower the priority */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 587a14f8b9..71e5354427 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -220,6 +220,8 @@ enum gic_version { GIC_V3, }; +DECLARE_PER_CPU(uint64_t, lr_mask); + extern enum gic_version gic_hw_version(void); /* Program the IRQ type into the GIC */ @@ -372,6 +374,7 @@ struct gic_hw_operations { void (*do_LPI)(unsigned int lpi); }; +extern const struct gic_hw_operations *gic_hw_ops; void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, From patchwork Tue Feb 6 17:08:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127058 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107671ljc; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:12 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:08:58 +0000 Message-Id: <20180206170903.30637-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 3/8] ARM: VGIC: split up gic_dump_info() to cover virtual part separately X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic_dump_info() not only dumps the hardware state of the GIC, but also the VGIC internal virtual IRQ lists. Split the latter off and move it into gic-vgic.c to observe the abstraction. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain.c | 1 + xen/arch/arm/gic-vgic.c | 11 +++++++++++ xen/arch/arm/gic.c | 12 ------------ xen/include/asm-arm/gic.h | 1 + 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index eb8c8f6176..a010443bfd 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -941,6 +941,7 @@ long arch_do_vcpu_op(int cmd, struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) void arch_dump_vcpu_info(struct vcpu *v) { gic_dump_info(v); + gic_dump_vgic_info(v); } void vcpu_mark_events_pending(struct vcpu *v) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 74d8ea7c96..8221ae557c 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -386,6 +386,17 @@ void gic_inject(void) gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct pending_irq *p; + + list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) + printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); + + list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) + printk("Pending irq=%d\n", p->irq); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 04e6d66b69..4cb74d449e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -443,20 +443,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r void gic_dump_info(struct vcpu *v) { - struct pending_irq *p; - printk("GICH_LRs (vcpu %d) mask=%"PRIx64"\n", v->vcpu_id, v->arch.lr_mask); gic_hw_ops->dump_state(v); - - list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) - { - printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); - } - - list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) - { - printk("Pending irq=%d\n", p->irq); - } } void init_maintenance_interrupt(void) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 71e5354427..1a142d6e9f 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -287,6 +287,7 @@ extern void send_SGI_allbutself(enum gic_sgi sgi); /* print useful debug info */ extern void gic_dump_info(struct vcpu *v); +extern void gic_dump_vgic_info(struct vcpu *v); /* Number of interrupt lines */ extern unsigned int gic_number_lines(void); From patchwork Tue Feb 6 17:08:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127061 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107843ljc; Tue, 6 Feb 2018 09:11:33 -0800 (PST) X-Google-Smtp-Source: AH8x227iefkUmYcmp4NAYYLSRdbYQf2YG7f7V3uy9lxBolAIlmyIzlHKZWNUUe93pAs3nghRj//G X-Received: by 10.36.124.1 with SMTP id a1mr4064763itd.92.1517937093467; Tue, 06 Feb 2018 09:11:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937093; cv=none; d=google.com; s=arc-20160816; b=t+HRZb+JI43hWUiTTe807SD1z/v3qx3CX7F0NF6cG1ATCrYZJZ+jKhCle0eh3u8+Pq g7d2+VSP6EM9eyv1lLB9EYwEbbtT8GDi0HCmd7aXtqrpRsJ/ZzzlOITIPgqFo6eV2d67 G18WYsbn2DKzwy8rt8k5xtg7dmOgLCLiGqbnLat99IxENKe3ieWd94nMb7HM3Dl3IQ27 Bld8xHhK3aTnH3XTOGiRuROlTrCFR5VIByJ77swZH2+Jof8PIe2XS2RQiAHn9DghrrDy QRdWFUcpC8jvnPTJHZG8FJyusCqgb+gXc10mue+pH7ioIaqbrsP9Qglxc/6LGF92GiNw So4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=M0RCpKwN/V9R1duxlG4gsDoAC2FZQSNCAaGEUvP/jEc=; b=OEMPxO3mAq21Ai7MEVO8/H7L3hGKWF39PHGfh7NTeDErpP+NFEcrh0fW/hB9V0xF72 1ZHkSgmmdplbI1NxF7qgrDAxrGzkpaKUjpzIJ6axJiwlvVFQltxAY8mWbjJZGYAtvWNm i9auSX63DbhG8GjDBkZ0kPdC/zXNzIbxu6WD7JcMSJH6OOySE3VzfSrG6Y9plopuOtCM NJZk8BvCOUVsWhs5ZYSgPeH7LyFxEi2a/k14xH5iU7rIYFY7IkVtdKSb9A4tMQDCxIXP T7Z+sMB1ZnaHT9Sob5dQYaBIQObhI0lXYBzgcztGOk9QOYn9nAENRPy5wa9mh4Rbd7XB LkMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MmS8uvYs; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:13 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:08:59 +0000 Message-Id: <20180206170903.30637-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 4/8] ARM: VGIC: rework events_need_delivery() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In event.h we very deeply dive into the VGIC to learn if an event for a guest is pending. Rework that function to abstract the VGIC specific part out. Also reorder the queries there, as we only actually need to check for the event channel if there are no other pending IRQs. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/vgic.c | 11 +++++++++++ xen/include/asm-arm/event.h | 13 +++---------- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 6e933a86d3..9921769b15 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -593,6 +593,17 @@ void arch_evtchn_inject(struct vcpu *v) vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); } +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct pending_irq *p; + + p = irq_to_pending(v, v->domain->arch.evtchn_irq); + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + return list_empty(&p->inflight); +} + bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) { struct vcpu *v = current; diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index 2b20d1aa15..e8c2a6cb44 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -16,12 +16,6 @@ static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) static inline int local_events_need_delivery_nomask(void) { - struct pending_irq *p = irq_to_pending(current, - current->domain->arch.evtchn_irq); - - /* Does not work for LPIs. */ - ASSERT(!is_lpi(current->domain->arch.evtchn_irq)); - /* XXX: if the first interrupt has already been delivered, we should * check whether any other interrupts with priority higher than the * one in GICV_IAR are in the lr_pending queue or in the LR @@ -33,11 +27,10 @@ static inline int local_events_need_delivery_nomask(void) if ( gic_events_need_delivery() ) return 1; - if ( vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - return 1; + if ( !vcpu_info(current, evtchn_upcall_pending) ) + return 0; - return 0; + return vgic_evtchn_irq_pending(current); } static inline int local_events_need_delivery(void) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 2a93a7bef9..22c8502c95 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -218,6 +218,8 @@ extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); +bool vgic_evtchn_irq_pending(struct vcpu *v); + extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, From patchwork Tue Feb 6 17:09:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127063 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107919ljc; Tue, 6 Feb 2018 09:11:38 -0800 (PST) X-Google-Smtp-Source: AH8x227i9PDMincV7mqkf8NUMpFyEytvgfA3GvgoFk8eakS6LCEkzdVI1OgA3sjrM48WuPKbK9Lp X-Received: by 10.36.17.208 with SMTP id 199mr3963782itf.103.1517937098516; Tue, 06 Feb 2018 09:11:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937098; cv=none; d=google.com; s=arc-20160816; b=xjX+k+RCwl1j3wx7YvgnFO3fxWqix/Rq2zPw6PvjI5PDWu5ynX1vcn/AtS9xcIrlg1 ca51ZsSIN44l8hUJijXvVD54P2+xb5MoRtdMR17pZ4VS+VPxJ/opHQ34fm/golI4hXZT 1bfMss7KwhhIrOtaPcfMWj5kzT7FAZQSHsEHQKmGs6VqR8Q6QiLMzaM4SZ20SCCzodqt Z5BwFGCHaSR1SEeH+kSArPjdKCFPmX3O+LzaCJBjm2H6+A3c2QQiWzG3WIfE8NS5gqMp RcsseKzvF/tjXbL47oSurEOcZIfNfigfq4Hos/N+DRsh+A90q91rvEETjBKFuRTy0Kqc LV+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=k7OGHahqTUm7JHm7ZkTkSArW+dpo43MZXAVMVHZq+bA=; b=UJNKhLBrernBw0dYJ3VG4ueWuUE4o90mQHz9h7O3iKZS1NVR8q762Y+ddzCJbHdiiV D01FbWRduwYZ/5lGcGAtBGEGg/4EhKDnvrpJBmwuISUNMq+gtoOg09YIManLDme++jV0 Aen+g69t7CV/QGPTTUa4WzJCBqX/ELFEtew5Tf2WgY5G9+DYQTYubRHzVm/L2IfpZM1I qgAuIZvg8TyC52X4Fo+VtFD9jlKP+8ErOcD+VmpVae3FLPMalm0rrM9HRVCSem48h/VX ro9SigcXHmXqHetfalpFUXLbiU0LUVJ2HXDsdxr5M2b93KOzqeJmz6i7RbqX1y/yvs4f BY9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=I5u1J7wu; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:14 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:09:00 +0000 Message-Id: <20180206170903.30637-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 5/8] ARM: VGIC: factor out vgic_connect_hw_irq() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access VGIC internal data structures like the rank and struct pending_irq in gic.c, which should be VGIC agnostic. Factor out a new function vgic_connect_hw_irq(), which allows a virtual IRQ to be connected to a hardware IRQ (using the hw bit in the LR). This removes said accesses to VGIC data structures and improves abstraction. One thing to note is that this changes the locking scheme slightly: we hold the rank lock for a shorter period of time, not covering some of the later lines, which deal with the "irq_desc" structure only. This should not have any adverse effect, but is a change in locking anyway. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/gic-vgic.c | 41 +++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 44 ++++++++++---------------------------------- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 53 insertions(+), 34 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 8221ae557c..820e464fc0 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -397,6 +397,47 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc, bool connect) +{ + unsigned long flags; + /* + * Use vcpu0 to retrieve the pending_irq struct. Given that we only + * route SPIs to guests, it doesn't make any difference. + */ + struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); + struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); + struct pending_irq *p = irq_to_pending(v_target, virq); + int ret = 0; + + /* "desc" is optional when we disconnect an IRQ. */ + ASSERT(connect && desc); + + /* We are taking to rank lock to prevent parallel connections. */ + vgic_lock_rank(v_target, rank, flags); + + if ( connect ) + { + /* The VIRQ should not be already enabled by the guest */ + if ( !p->desc && + !test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + p->desc = desc; + else + ret = -EBUSY; + } + else + { + if ( desc && p->desc != desc ) + ret = -EINVAL; + else + p->desc = NULL; + } + + vgic_unlock_rank(v_target, rank, flags); + + return ret; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 4cb74d449e..968e46fabb 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -128,13 +128,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) int gic_route_irq_to_guest(struct domain *d, unsigned int virq, struct irq_desc *desc, unsigned int priority) { - unsigned long flags; - /* Use vcpu0 to retrieve the pending_irq struct. Given that we only - * route SPIs to guests, it doesn't make any difference. */ - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - int res = -EBUSY; + int ret; ASSERT(spin_is_locked(&desc->lock)); /* Caller has already checked that the IRQ is an SPI */ @@ -142,12 +136,9 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, ASSERT(virq < vgic_num_irqs(d)); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - - if ( p->desc || - /* The VIRQ should not be already enabled by the guest */ - test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - goto out; + ret = vgic_connect_hw_irq(d, NULL, virq, desc, true); + if ( ret ) + return ret; desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); @@ -156,31 +147,19 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, gic_set_irq_type(desc, desc->arch.type); gic_set_irq_priority(desc, priority); - p->desc = desc; - res = 0; - -out: - vgic_unlock_rank(v_target, rank, flags); - - return res; + return 0; } /* This function only works with SPIs for now */ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc) { - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - unsigned long flags; + int ret; ASSERT(spin_is_locked(&desc->lock)); ASSERT(test_bit(_IRQ_GUEST, &desc->status)); - ASSERT(p->desc == desc); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - if ( d->is_dying ) { desc->handler->shutdown(desc); @@ -198,19 +177,16 @@ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, */ if ( test_bit(_IRQ_INPROGRESS, &desc->status) || !test_bit(_IRQ_DISABLED, &desc->status) ) - { - vgic_unlock_rank(v_target, rank, flags); return -EBUSY; - } } + ret = vgic_connect_hw_irq(d, NULL, virq, desc, false); + if ( ret ) + return ret; + clear_bit(_IRQ_GUEST, &desc->status); desc->handler = &no_irq_type; - p->desc = NULL; - - vgic_unlock_rank(v_target, rank, flags); - return 0; } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 22c8502c95..fda082395b 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc, bool connect); extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); From patchwork Tue Feb 6 17:09:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127060 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107791ljc; Tue, 6 Feb 2018 09:11:31 -0800 (PST) X-Google-Smtp-Source: AH8x225yaQNCUp99O7Qg9sdxUGVGLBHhRpkj+lA87J3QhoIh2le5NpKqDBNnQaY8NWrlz2pGAFx+ X-Received: by 10.36.105.17 with SMTP id e17mr4098682itc.84.1517937091033; Tue, 06 Feb 2018 09:11:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937091; cv=none; d=google.com; s=arc-20160816; b=qh6IZJFfby2GwFgy7pkzHktdJx37kgKt5kBc1CoGl5VVWpQAhk53v9LBzJzWWT03kD B0piOoMG8VoxGDDXktLxgvZT9SxpHfzp16aBR/Cndx0hphvw7v3F8pbntHOlO7pNokhP lyev9hGhh/FV1FeYzkSUPpQZ1hc5C6vii24Em70fNW2/IH7CGqySwZSswwrqlRo99Ybz RsHdtKDZC2TZTZzyIMXNJwTBrh/zeYs3+Wb/dDtRMIXt6TJQvWYrxxzKqg8PdLYWQTU1 bpeSqH1JCp4taxMF3PDxVRpec6SYZWGR3r9gQXh3Z4ABeLKZ1d+YhyXUueCeicukrDg1 R6Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Ju4skTQ07eEnflgvHOSORv5hPztMz+kO9GIamJ/4ptw=; b=tjPEaNfnFnZ2FmgE+CFSshgVxLHhTVyEHf3AOs13grPhXW2e+v77HPGXZXkpYucvWe MhxbPYGDDtCf7hnpk901ylONAZRkxLFTN+orIHF4uf/d19/8DIL4I47GQpeR+KlNpTA7 q1otzKGwW99fny62faoVimX/8at2Z2I129WQEnZcU9+q8xUk3j+f6nU8lyr6kmyNfiFu jByoQf0ALBLADzCP0UfyMB6Ek2Nq50/R9rUIW1TPrhEo5exZVzhhgkcS2dTVgO0uN8yj 9/RYm6UUvp9M6bHMCF5K2pQPrZSnIpKZ/YnCtAlyXpcSbnapRAIK/sobbdLtzcSAP/1l bAqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kogpuByt; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:15 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:09:01 +0000 Message-Id: <20180206170903.30637-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 6/8] ARM: VGIC: factor out vgic_get_hw_irq_desc() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access the VGIC internal struct pending_irq (which describes a virtual IRQ) in irq.c. Factor out the actually needed functionality to learn the associated hardware IRQ and move that into gic-vgic.c to improve abstraction. Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini Reviewed-by: Julien Grall --- xen/arch/arm/gic-vgic.c | 17 +++++++++++++++++ xen/arch/arm/irq.c | 7 ++----- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 820e464fc0..72a904bbeb 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -397,6 +397,23 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct pending_irq *p; + + ASSERT(!v && virq >= 32); + + if ( !v ) + v = d->vcpu[0]; + + p = irq_to_pending(v, virq); + if ( !p ) + return NULL; + + return p->desc; +} + int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc, bool connect) { diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 7f133de549..62103a20e3 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -534,19 +534,16 @@ int release_guest_irq(struct domain *d, unsigned int virq) struct irq_desc *desc; struct irq_guest *info; unsigned long flags; - struct pending_irq *p; int ret; /* Only SPIs are supported */ if ( virq < NR_LOCAL_IRQS || virq >= vgic_num_irqs(d) ) return -EINVAL; - p = spi_to_pending(d, virq); - if ( !p->desc ) + desc = vgic_get_hw_irq_desc(d, NULL, virq); + if ( !desc ) return -EINVAL; - desc = p->desc; - spin_lock_irqsave(&desc->lock, flags); ret = -EINVAL; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index fda082395b..6ea9f140a7 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq); int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc, bool connect); From patchwork Tue Feb 6 17:09:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127065 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3108043ljc; Tue, 6 Feb 2018 09:11:46 -0800 (PST) X-Google-Smtp-Source: AH8x224sTYlZBTUaqgOFAfapGieBhQJz3adpmh8eA7ku1Lljtuuusw0dmV9xNWutgZjp74vCnW5s X-Received: by 10.36.204.139 with SMTP id x133mr4157715itf.75.1517937106652; Tue, 06 Feb 2018 09:11:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937106; cv=none; d=google.com; s=arc-20160816; b=HqqN77ZAxH/w7X+bdyU7jEkQJ8T+aw7sUwB7fGbXOAJ5UY3EU9jd9mDcFe2MdPNuzK D+5RxD+P9c79kB95Mlj5Vgwx7DfV18Mo9XWev/UKJox5KGE1DcIojGB8rZrubUUJc5lB QUu+i8gFJB7VkgoBSXAVpZXTWomwvRlWYScPUDyygg9xB0b6wFknOZ/5xfkRW74Iv/a+ vOmxqnHdypvAoz9NBfMHb5n9ACaDBDggOmUDRnY/Ll3v6Ss2OMts3LA4i+W+LXQYCBfr 7lvTBzo5WKHpMu8egxJiM16dl+kdpLtug8lx1mtiw2oH1wKGHIMdR6QX+x7geExjMFpL m7Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=fXze6vPPR48+AlFThPaLFqzyamrN3SROqxW0w99++OU=; b=vYZzLIF/1MQWpo1R49p5EclWLDxt6PyQ5grsrwJKzTBKHTfDb0+p/DsvZDmpYl9DcX /54QcokxL1X1uaHbm/9NWXmrOhp6EJjk67V6mtndHOybQFYizvP0pHs5WCHQgqJxkt+5 O+UOisPMqdF9b7e6maRrmC6Boxnprugn2M/WPEZFsg5OhEh35yVYFtXqgoodmIh+RG3F EcyUiRAeLiXc20H5GUzH1oqVNHIZtQPsWpwbdQ0LtsCvpTUB8B/Agy8mXadQaBdVmIGm NjBK8LsR0ho6NPiNnNtlP5zRh+Vnvm7RsciEFpIyCcnufYorBrRs+U3htsi6MikzjTCy JSyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gO9do563; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:16 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:09:02 +0000 Message-Id: <20180206170903.30637-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 7/8] ARM: VGIC: rework gicv[23]_update_lr to not use pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The functions to actually populate a list register were accessing the VGIC internal pending_irq struct, although they should be abstracting from that. Break the needed information down to remove the reference to pending_irq from gic-v[23].c. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 14 +++++++------- xen/arch/arm/gic-v3.c | 12 ++++++------ xen/arch/arm/gic-vgic.c | 3 ++- xen/include/asm-arm/gic.h | 4 ++-- xen/include/asm-arm/irq.h | 3 +++ 5 files changed, 20 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 511c8d7294..2b271ba322 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -428,8 +428,8 @@ static void gicv2_disable_interface(void) spin_unlock(&gicv2.lock); } -static void gicv2_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv2_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint32_t lr_reg; @@ -437,12 +437,12 @@ static void gicv2_update_lr(int lr, const struct pending_irq *p, BUG_ON(lr < 0); lr_reg = (((state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) | - ((GIC_PRI_TO_GUEST(p->priority) & GICH_V2_LR_PRIORITY_MASK) - << GICH_V2_LR_PRIORITY_SHIFT) | - ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); + ((GIC_PRI_TO_GUEST(priority) & GICH_V2_LR_PRIORITY_MASK) + << GICH_V2_LR_PRIORITY_SHIFT) | + ((virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); - if ( p->desc != NULL ) - lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK ) + if ( hw_irq != INVALID_IRQ ) + lr_reg |= GICH_V2_LR_HW | ((hw_irq & GICH_V2_LR_PHYSICAL_MASK ) << GICH_V2_LR_PHYSICAL_SHIFT); writel_gich(lr_reg, GICH_LR + lr * 4); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 072345c6f9..25c30bb9ea 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -966,8 +966,8 @@ static void gicv3_disable_interface(void) spin_unlock(&gicv3.lock); } -static void gicv3_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv3_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint64_t val = 0; @@ -983,11 +983,11 @@ static void gicv3_update_lr(int lr, const struct pending_irq *p, if ( current->domain->arch.vgic.version == GIC_V3 ) val |= GICH_LR_GRP1; - val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT; - val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; + val |= (uint64_t)priority << GICH_LR_PRIORITY_SHIFT; + val |= ((uint64_t)virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; - if ( p->desc != NULL ) - val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK) + if ( hw_irq != INVALID_IRQ ) + val |= GICH_LR_HW | (((uint64_t)hw_irq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT); gicv3_ich_write_lr(lr, val); diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 72a904bbeb..d273863556 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -38,7 +38,8 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - gic_hw_ops->update_lr(lr, p, state); + gic_hw_ops->update_lr(lr, p->irq, p->priority, + p->desc ? p->desc->irq : INVALID_IRQ, state); set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1a142d6e9f..497f195bc1 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -344,8 +344,8 @@ struct gic_hw_operations { /* Disable CPU physical and virtual interfaces */ void (*disable_interface)(void); /* Update LR register with state and priority */ - void (*update_lr)(int lr, const struct pending_irq *pending_irq, - unsigned int state); + void (*update_lr)(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state); /* Update HCR status register */ void (*update_hcr_status)(uint32_t flag, bool set); /* Clear LR register */ diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index abc8f06a13..0d110ecb08 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -31,6 +31,9 @@ struct arch_irq_desc { /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */ #define INVALID_LPI 0 +/* This is a spurious interrupt ID which never makes it into the GIC code. */ +#define INVALID_IRQ 1023 + extern unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS From patchwork Tue Feb 6 17:09:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127062 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3107862ljc; Tue, 6 Feb 2018 09:11:34 -0800 (PST) X-Google-Smtp-Source: AH8x224wZyRMcoOjfGA7PP0UwgrPU+1Ctv/oFogiRYhz2AWSkOVLEtPStaeceYEN/X8M8b71XJ0z X-Received: by 10.107.63.68 with SMTP id m65mr4129756ioa.107.1517937094393; Tue, 06 Feb 2018 09:11:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517937094; cv=none; d=google.com; s=arc-20160816; b=hLD4SyEeWD1ZRjwdLfSVRWVLteN5vgGUuC9GCRBCq6sKuLuQSE4GV0uIqWmlWUQjsQ gKWQF4a1egKhqbnHKAu892T55bc39GO0plIn00vevcu5AtSsH0tNAJFsl5dOzulK0MMq WnlAGx/uU5bob1lOCJlT4IjW0G6DJJCDIyUpNXiQY4C1EkQl6Tz2/DdP61cGbRfbpKRE +I+naXLrkzeOVD82BXdftbHzsRRGSOzfLvPfWDZ2LcBmfHFkq/2N7tXSqW+DDHCIk4A/ PO1r8K6jhI5YtQISuz5hRPA26ocL2P7Y086e9tvEBi19JImPS5OV1xu+xMcoMut5WQrV eIlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=+jnAzBIfl35oLjUphSsd4jABG68Ysk2ebm7X9U8luoM=; b=STC5Vw7Q/ABHaKs/ZHKPoiC4C8hRRc4JItwFciCn14szY4ZKWfczUgwa9XS09EGvDh K3liFlFiM9vbhPmzbWOo2sEGod5mBUyZ5xbqEUAzSJhOOtimKLqeuN4UnXksg2oDBV9p XfI+KK3ytBbsviuTKlApbOjyJ+/bqW8+VF3V6m1oZmqjatu0yVvaJA/zKzcoC3TRlJby CjdqqRhA2sRotqC/6WvxYd44l7YzjLmlZIH8Mx9LGWm/0EQ8kiNWkhs1JNPccs5wmF2/ +P1MJAitOcJ135vQemJrziUIDojOYngayAncno5WiMFxOV+BE4ZQBWzawRQaYXRErUwd 5cmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fzkcGpXR; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n2sm7885819wra.41.2018.02.06.09.09.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 09:09:17 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Tue, 6 Feb 2018 17:09:03 +0000 Message-Id: <20180206170903.30637-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180206170903.30637-1-andre.przywara@linaro.org> References: <20180206170903.30637-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v5 8/8] ARM: make nr_irqs a constant X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On ARM the maximum number of IRQs is a constant, but we share it being a variable to match x86. Since we are not supposed to alter it, let's mark it as "const" to avoid accidental change. Suggested-by: Julien Grall Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/irq.c | 2 +- xen/include/asm-arm/irq.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 62103a20e3..29af10e82c 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -27,7 +27,7 @@ #include #include -unsigned int __read_mostly nr_irqs = NR_IRQS; +const unsigned int nr_irqs = NR_IRQS; static unsigned int local_irqs_type[NR_LOCAL_IRQS]; static DEFINE_SPINLOCK(local_irqs_type_lock); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 0d110ecb08..9d55e9b122 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -34,7 +34,7 @@ struct arch_irq_desc { /* This is a spurious interrupt ID which never makes it into the GIC code. */ #define INVALID_IRQ 1023 -extern unsigned int nr_irqs; +extern const unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS