From patchwork Tue Feb 6 17:44:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127035 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3094189ljc; Tue, 6 Feb 2018 08:57:25 -0800 (PST) X-Google-Smtp-Source: AH8x2255Vfc8tXB1D4LlbS5GO5s8SMiljGHZlmpbH1GaIOsXuVQBIPlumoBP2KbEBYDcnzzfmh+j X-Received: by 10.98.68.91 with SMTP id r88mr3088996pfa.52.1517936245300; Tue, 06 Feb 2018 08:57:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936245; cv=none; d=google.com; s=arc-20160816; b=WT6lHi9IRXtMHC8EgnVJFX5zVuwhspcBtJNSbBF9ASqLV4OifnpFo2Tivp1ZsKprsp u9/JBV0tZlLSK1OFgMYw/je7IxgVw2YcV8OSSkOkD6GF1BUN/U/tMHFzvPkwTPZDa5JI tUQb1OLgtOpcXJHj+2hxU4vMhxYFDkgXGjzJTl9/bBsN6bdasrhqUIG5GtiC6Z/YROmh nEyToqJeuWIqoE7QaUs0xXiDDVg4pHWZJ7UOLy3rpDHPA20HyEOsBOHhF7Fz2AWv6Uuf zc7RK0U1UEKKS86rDVlJ7ljCljh6DnVIXxgJ1EnD++ba29VASgRWPx7JZLlOUrSITR5v vs7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rgi/1bWaBGY/7IhKminZ5Ivbocu3kgMaYGGO38k3C1E=; b=xyG3+duq6jkQMmHSTaWFFjcXVfVC98jbwL0f5XeOMdSgT0dMHUtdCBfQpGt05N8Nek 3lhcQaFb/hgSoAdKs3BoUq56eMXK4lU8CmmwJsi3Yoc8q5VvAdgu3BGQwEdZaRMIRk47 y49WRcH9HNy3i2E962FmbPKhzlbAtI1VRNe6jcRsAP0JKDCNp4JOO/il1L8LZRNDwiE4 3ufNA8ZeBCuFeaO2nUNr5tOriiCp5lnthaWOf72JGfhvD07TBjqQF2De0miECLzM8JDD o22VxNF2InPyy85llmyseF1zlHqU9chc9le6nJYPSP+VtTZwusk/0yz9WU/jWfgO52mD /Ekg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k29si4929543pgn.739.2018.02.06.08.57.24; Tue, 06 Feb 2018 08:57:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752621AbeBFQ5W (ORCPT + 21 others); Tue, 6 Feb 2018 11:57:22 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51532 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753136AbeBFQ4C (ORCPT ); Tue, 6 Feb 2018 11:56:02 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3D3C6B78CEEF2; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:50 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 1/9] perf vendor events: drop incomplete multiple mapfile support Date: Wed, 7 Feb 2018 01:44:56 +0800 Message-ID: <1517939104-230881-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently jevents supports multiple mapfiles, but this is only in the form where mapfile basename starts with 'mapfile.csv' At the moment, no architectures actually use multiple mapfiles, so drop the support for now. This patch also solves a nuisance where, when the mapfile is edited and the text editor may create a backup, jevents may use the backup, as shown: jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv Signed-off-by: John Garry --- tools/perf/pmu-events/README | 5 ++--- tools/perf/pmu-events/jevents.c | 10 ++-------- 2 files changed, 4 insertions(+), 11 deletions(-) -- 1.9.1 Acked-by: Jiri Olsa diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index c2ee3e4..2407abc 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - - Regular files with basename starting with 'mapfile.csv' are assumed - to be a CSV file that maps a specific CPU to its set of PMU events. - (see below for mapfile format) + - The CSV file that maps a specific CPU to its set of PMU events is to + be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored. diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index b578aa2..9e0a21e 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb, * after processing all JSON files (so we can write out the * mapping table after all PMU events tables). * - * TODO: Allow for multiple mapfiles? Punt for now. */ if (level == 1 && is_file) { - if (!strncmp(bname, "mapfile.csv", 11)) { - if (mapfile) { - pr_info("%s: Many mapfiles? Using %s, ignoring %s\n", - prog, mapfile, fpath); - } else { - mapfile = strdup(fpath); - } + if (!strcmp(bname, "mapfile.csv")) { + mapfile = strdup(fpath); return 0; } From patchwork Tue Feb 6 17:44:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127038 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3094605ljc; Tue, 6 Feb 2018 08:57:59 -0800 (PST) X-Google-Smtp-Source: AH8x225hCZai3dCdwvnq1k8f3pIsqnakFf2sIYyaoHqPBriy+YdTI5dH42pEkzxD7REZfZ+EgvLq X-Received: by 2002:a17:902:9306:: with SMTP id bc6-v6mr2974955plb.29.1517936279844; Tue, 06 Feb 2018 08:57:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936279; cv=none; d=google.com; s=arc-20160816; b=1B3RQLWGhkbzk/woki0Ksgs/tPpxbpARShb7CuvsD4JKwiFrGdwWq7TZVwY2Ip9L3k LEDTI3YTJqTyGLEvnLLtVkQzXDDlvTA+yqMnr1nCjrpUMTtqfiltsYHm/250Rv9/nHfp 28/zv40VkvqFnuYfHDa/NJSO5ruY3w2UpbW86y4DSK55uN1yqxvliaUrA/we1FS/hbHQ U9fHd4frUYmMl7xl7nsOGvzi/Gmq9hqGzLRATX90YNxua4nOsk7OXRrePHjrAyrkKrQg qLZRCOjy8ysyXLnEVYeUlgEOczv262zCck9MP4TvnPwwlJku3QRt6uaNJbQ0r66TUsrj io2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=xosBcxsOCe3AURc8SXBlveIzWFq9uQJfKBWIZpw0Koc=; b=DiXCGFUWp9+rTeQ/o6AF49kPD0N/s+UNZOVvOwbsNyzax7PLB00Z7qrU4jlmSQzxlF znULH9rHeh6TC9O+BdmW4xKWE2oelsLnmx9GNaLaSzQ95a5CArlV5Bfmb9OToZ6aByeV boyrQkHBGuroBAMbPO8tkwPJFNMa7nuE9ykK+DEIVxvoE4yITyenC8VvGT6+C0egBp9S qtHVfyFCE40y6rBVemyHWpmwuwdYB1rvgkAvnh8DpEq2KxfzSFVPVYE9SYFzlnTQB0LJ 4ZyJIC6c6KzebIqwT/E9E6QqQC1v59y6naMLVWJPmByeybBdDB0JIY0VRaAMaiymG1GD VTJA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h61-v6si1701971pld.816.2018.02.06.08.57.59; Tue, 06 Feb 2018 08:57:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753022AbeBFQ56 (ORCPT + 21 others); Tue, 6 Feb 2018 11:57:58 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51534 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752589AbeBFQ4D (ORCPT ); Tue, 6 Feb 2018 11:56:03 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4E74111ECF883; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:51 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 2/9] perf utils: add support for pmu events vendor sub-directory Date: Wed, 7 Feb 2018 01:44:57 +0800 Message-ID: <1517939104-230881-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some architectures (like arm), it is required to support a vendor sub-directory and not locate all the JSONs for a specific vendor in the same folder. This is because all the events for the same vendor will be placed in the same pmu events table, which may cause conflict. This conflict would be in the instance that a vendor's custom implemented events do have the same meaning on different platforms, so events in the pmu table would conflict. In addition, per list command may show events which are not even supported for a given platform. This patch adds support for a arch/vendor/platform directory hierarchy, while maintaining backwards-compatibility for existing arch/platform structure. In this, each platform would always have its own pmu events table. In generated file pmu_events.c, each platform table name is in the format pme{_vendor}_platform, like this: struct pmu_events_map pmu_events_map[] = { { .cpuid = "0x00000000420f5160", .version = "v1", .type = "core", .table = pme_cavium_thunderx2 }, { .cpuid = 0, .version = 0, .type = 0, .table = 0, }, }; Signed-off-by: John Garry --- tools/perf/pmu-events/README | 4 +++ tools/perf/pmu-events/jevents.c | 70 ++++++++++++++++++++++++++++++++++++++--- 2 files changed, 70 insertions(+), 4 deletions(-) -- 1.9.1 Acked-by: Jiri Olsa diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 2407abc..655286f 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU: Cache.json Memory.json Virtual-Memory.json Frontend.json Pipeline.json +The JSONs folder for a CPU model/family may be placed in the root arch +folder, or may be placed in a vendor sub-folder under the arch folder +for instances where the arch and vendor are not the same. + Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 9e0a21e..eb183b1 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -588,7 +588,7 @@ static char *file_name_to_table_name(char *fname) * Derive rest of table name from basename of the JSON file, * replacing hyphens and stripping out .json suffix. */ - n = asprintf(&tblname, "pme_%s", basename(fname)); + n = asprintf(&tblname, "pme_%s", fname); if (n < 0) { pr_info("%s: asprintf() error %s for file %s\n", prog, strerror(errno), fname); @@ -598,7 +598,7 @@ static char *file_name_to_table_name(char *fname) for (i = 0; i < strlen(tblname); i++) { c = tblname[i]; - if (c == '-') + if (c == '-' || c == '/') tblname[i] = '_'; else if (c == '.') { tblname[i] = '\0'; @@ -755,15 +755,65 @@ static int get_maxfds(void) static FILE *eventsfp; static char *mapfile; +static int is_leaf_dir(const char *fpath) +{ + DIR *d; + struct dirent *dir; + int res = 1; + + d = opendir(fpath); + if (!d) + return 0; + + while ((dir = readdir(d)) != NULL) { + if (dir->d_type == DT_DIR && dir->d_name[0] != '.') { + res = 0; + break; + } else if (dir->d_type == DT_UNKNOWN) { + char path[PATH_MAX]; + struct stat st; + + sprintf(path, "%s/%s", fpath, dir->d_name); + if (stat(path, &st)) + break; + + if (S_ISDIR(st.st_mode)) { + res = 0; + break; + } + } + } + + closedir(d); + + return res; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { - char *tblname, *bname = (char *) fpath + ftwbuf->base; + char *tblname, *bname; int is_dir = typeflag == FTW_D; int is_file = typeflag == FTW_F; int level = ftwbuf->level; int err = 0; + if (level == 2 && is_dir) { + /* + * For level 2 directory, bname will include parent name, + * like vendor/platform. So search back from platform dir + * to find this. + */ + bname = (char *) fpath + ftwbuf->base - 2; + for (;;) { + if (*bname == '/') + break; + bname--; + } + bname++; + } else + bname = (char *) fpath + ftwbuf->base; + pr_debug("%s %d %7jd %-20s %s\n", is_file ? "f" : is_dir ? "d" : "x", level, sb->st_size, bname, fpath); @@ -773,7 +823,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, return 0; /* model directory, reset topic */ - if (level == 1 && is_dir) { + if (level == 1 && is_dir && is_leaf_dir(fpath)) { if (close_table) print_events_table_suffix(eventsfp); @@ -791,6 +841,18 @@ static int process_one_file(const char *fpath, const struct stat *sb, print_events_table_prefix(eventsfp, tblname); return 0; + } else if (level == 2 && is_dir) { + if (close_table) + print_events_table_suffix(eventsfp); + + tblname = file_name_to_table_name(bname); + if (!tblname) { + pr_info("%s: Error determining table name for %s, exiting\n", + prog, bname); + return -1; + } + + print_events_table_prefix(eventsfp, tblname); } /* From patchwork Tue Feb 6 17:44:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127043 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096132ljc; Tue, 6 Feb 2018 09:00:02 -0800 (PST) X-Google-Smtp-Source: AH8x2258Xbf3xkTgpQ0vz9tblb1JwwxZZqbF7b05ONpJNFsXFKAH/RgxWh2AGujC+4Ok2WLlp6+O X-Received: by 2002:a17:902:32a2:: with SMTP id z31-v6mr3052115plb.345.1517936402206; Tue, 06 Feb 2018 09:00:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936402; cv=none; d=google.com; s=arc-20160816; b=iTyMe++C/6/ksFFQdWF3koHRt5DSIFskvgcppAMyeSH9gYngyRuyfEglepxENguI4s fiyBvCseREa752WpfIm8P97TIXhqU+VCa73H1x2lgU3HzxfB0mcs5qfiVdWo9LtSpNfW Iq0yPFRiJzt717r9Bc7MwOh9DqdBz6uZXe3sjV9w6Fb6tVV9kn2q8Ocafii40nUqps/G uAIKxzB+RcS5NYJSEIQ2+3LVuyYZ/Tuoh9AtGgY13nD0cTAOEVM50ucT+o+j1kmslNNr 1UUw2Duu/th3WNHG9XdXn8L1FGP6/YpjOEmLINHyjAeV+K0ywNMQHgIGeAB3+Rox3QWR /ccg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=J6/tFYf13WQCt1So7/MXhym348zN48aoGwv2ECJeIO8=; b=ycd1ktR9M+iB+Z+QzendAfPWkOxTmD0vZ2q2Vu0I7brah6zXRBlGgj02M4hCf5QmCn j79PGp4HPld0aj4/jQlFTwEKMjyhZtIukd+nfANv1Ht0P1K35GmfSOId0HkdI5frVHH7 hGS4tMans4R+KqIGTdTsrQ+EJ8JTELwAIBM+ToN9O9rSqjkbN0tXvSRrKwHeLNInDVWD j1qriI0uBUfdxx+FougtzNj5hLX3zy4B7U4S0DLkJyU1MTWR4wPfJl8D8MRvGFZYQuOM 5WrjBVR8xKyr4kJztXkqlDcEooRmu9gXmXW+Y93NPn/TRDqpBLe/zSN58Cy7WD5b5PVr /Xhw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s13-v6si9013984plq.557.2018.02.06.09.00.01; Tue, 06 Feb 2018 09:00:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752920AbeBFRAA (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:00 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51749 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753093AbeBFQ4M (ORCPT ); Tue, 6 Feb 2018 11:56:12 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id E1270386DB97F; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:51 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 3/9] perf vendor events arm64: Relocate ThunderX2 JSON Date: Wed, 7 Feb 2018 01:44:58 +0800 Message-ID: <1517939104-230881-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since jevents now supports vendor subdirectory, relocate the ThunderX2 JSON to Cavium subdirectory. Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---------------------- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 3 files changed, 63 insertions(+), 63 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json deleted file mode 100644 index 2db45c4..0000000 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json +++ /dev/null @@ -1,62 +0,0 @@ -[ - { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", - }, - { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", - }, - { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", - }, - { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json new file mode 100644 index 0000000..2db45c4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "l1d_cache_rd", + "BriefDescription": "L1D cache read", + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write ", + "EventCode": "0x41", + "EventName": "l1d_cache_wr", + "BriefDescription": "L1D cache write", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "l1d_cache_refill_rd", + "BriefDescription": "L1D cache refill read", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "l1d_cache_refill_wr", + "BriefDescription": "L1D refill write", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "l1d_tlb_refill_rd", + "BriefDescription": "L1D tlb refill read", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "l1d_tlb_refill_wr", + "BriefDescription": "L1D tlb refill write", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "l1d_tlb_rd", + "BriefDescription": "L1D tlb read", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "l1d_tlb_wr", + "BriefDescription": "L1D tlb write", + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "bus_access_rd", + "BriefDescription": "Bus access read", + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "bus_access_wr", + "BriefDescription": "Bus access write", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index e61c9ca..952a05c 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Tue Feb 6 17:44:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127047 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096898ljc; Tue, 6 Feb 2018 09:00:40 -0800 (PST) X-Google-Smtp-Source: AH8x2245ehX+HatFFVenRT5nkKtw4aDRuALU4/9jO/glf6U1WmIAzjqghO7tO45RvR8gBuQaQoRH X-Received: by 10.99.149.4 with SMTP id p4mr1048894pgd.0.1517936440173; Tue, 06 Feb 2018 09:00:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936440; cv=none; d=google.com; s=arc-20160816; b=YRS3yPlRFqE0CJbmntwCd0/K9N3kJEVxhkfrc3bX6q1AjGJzrsNad7EBxQbEiDfrks yUs821z4VfAN2KxPSYg8/TKN4nqRVXn3RcS/OGpFn6kgA8+zbCBGTJqOK+qP0mXCQyLw HVhly21B/ZZPByvbgtLF94qrHskR2LOFKIW4S/Rdj24+kIRvlRvolWQv+4RnxcKEVav1 rQM3slJy8cAr0fA4aVlynT97JmNSmaAXFsLgP3va4nktabAjlmrP4EQDvzDckAWfoWsh Pkzjif9w+hhLpWgXIalgpvwKmnsXAfHqPm2arii4qyExVGaGkYy0D4u2J7ZQqvrlnUj6 n54g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=JajFpS6VEwLGJ8U9cchmSwUR4q7hAK4USYb+7nb7Gpc=; b=tZf3J2zsBVSAJXsvosPIcQnPYGTjhcT+RnDU3bRQNeZa9YlxMt1KeaVqbrOxpzRZjV 0tXK62M5AS26D6I4Tx431SoKdNiFDdXhARAOGUvJyxCSx10ID7u1dmQcAdrQk4DlvHQA z5aZHDODAeciEt4sEFCLHHZ5lIwDYtVKnQzFaBQNG3ZR5ZuJrltefaKjEkncobcuFZ+F PJ2smJMyWk69/hu3YGNaF559XjGRaCNg0m11D0lxkNcpoBLlm+v+n2AKvSIIt4mMhCuw BTA3uNlgaAZJmW5ukGDnKkvrdz1EhhcsQFy0U1zuaUIBMIGqZzJ2lZCmhwhHzLRykD/e DXsg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18-v6si1544992plq.228.2018.02.06.09.00.39; Tue, 06 Feb 2018 09:00:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753250AbeBFRAh (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:37 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51640 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753141AbeBFQ4C (ORCPT ); Tue, 6 Feb 2018 11:56:02 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 84AF3B2D1190B; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:51 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 4/9] perf vendor events arm64: Relocate Cortex A53 JSONs Date: Wed, 7 Feb 2018 01:44:59 +0800 Message-ID: <1517939104-230881-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The arm64 pmu-events folder structure has become disorganised, since now we have core and also vendor folders at the same level folder. Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm vendor subdirectory. Signed-off-by: John Garry --- .../arch/arm64/arm/cortex-a53/branch.json | 27 +++++++++++ .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/cache.json | 27 +++++++++++ .../arch/arm64/arm/cortex-a53/memory.json | 22 +++++++++ .../arch/arm64/arm/cortex-a53/other.json | 32 +++++++++++++ .../arch/arm64/arm/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++ .../pmu-events/arch/arm64/cortex-a53/branch.json | 27 ----------- .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/cache.json | 27 ----------- .../pmu-events/arch/arm64/cortex-a53/memory.json | 22 --------- .../pmu-events/arch/arm64/cortex-a53/other.json | 32 ------------- .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ---------------------- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 13 files changed, 183 insertions(+), 183 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json new file mode 100644 index 0000000..3b62087 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0x7A", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed - Indirect branch" + }, + {, + "EventCode": "0xC9", + "EventName": "BR_COND", + "BriefDescription": "Conditional branch executed" + }, + {, + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MISPRED", + "BriefDescription": "Indirect branch mispredicted" + }, + {, + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_MISPRED_ADDR", + "BriefDescription": "Indirect branch mispredicted because of address miscompare" + }, + {, + "EventCode": "0xCC", + "EventName": "BR_COND_MISPRED", + "BriefDescription": "Conditional branch mispredicted" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json new file mode 100644 index 0000000..11baad6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -0,0 +1,27 @@ +[ + {, + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" + }, + {, + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" + }, + {, + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" + }, + {, + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" + }, + {, + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json new file mode 100644 index 0000000..480d9f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -0,0 +1,22 @@ +[ + {, + "EventCode": "0x60", + "EventName": "BUS_ACCESS_LD", + "BriefDescription": "Bus access - Read" + }, + {, + "EventCode": "0x61", + "EventName": "BUS_ACCESS_ST", + "BriefDescription": "Bus access - Write" + }, + {, + "EventCode": "0xC0", + "EventName": "EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + {, + "EventCode": "0xC1", + "EventName": "EXT_MEM_REQ_NC", + "BriefDescription": "Non-cacheable external memory request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json new file mode 100644 index 0000000..73a2240 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -0,0 +1,32 @@ +[ + {, + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + }, + {, + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + }, + {, + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" + }, + {, + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + }, + {, + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + }, + {, + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json new file mode 100644 index 0000000..3149fb9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -0,0 +1,52 @@ +[ + {, + "EventCode": "0xC7", + "EventName": "STALL_SB_FULL", + "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" + }, + {, + "EventCode": "0xE0", + "EventName": "OTHER_IQ_DEP_STALL", + "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" + }, + {, + "EventCode": "0xE1", + "EventName": "IC_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" + }, + {, + "EventCode": "0xE2", + "EventName": "IUTLB_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" + }, + {, + "EventCode": "0xE3", + "EventName": "DECODE_DEP_STALL", + "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" + }, + {, + "EventCode": "0xE4", + "EventName": "OTHER_INTERLOCK_STALL", + "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" + }, + {, + "EventCode": "0xE5", + "EventName": "AGU_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" + }, + {, + "EventCode": "0xE6", + "EventName": "SIMD_DEP_STALL", + "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." + }, + {, + "EventCode": "0xE7", + "EventName": "LD_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" + }, + {, + "EventCode": "0xE8", + "EventName": "ST_DEP_STALL", + "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json deleted file mode 100644 index 3b62087..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" - }, - {, - "EventCode": "0xC9", - "EventName": "BR_COND", - "BriefDescription": "Conditional branch executed" - }, - {, - "EventCode": "0xCA", - "EventName": "BR_INDIRECT_MISPRED", - "BriefDescription": "Indirect branch mispredicted" - }, - {, - "EventCode": "0xCB", - "EventName": "BR_INDIRECT_MISPRED_ADDR", - "BriefDescription": "Indirect branch mispredicted because of address miscompare" - }, - {, - "EventCode": "0xCC", - "EventName": "BR_COND_MISPRED", - "BriefDescription": "Conditional branch mispredicted" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json deleted file mode 100644 index 11baad6..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" - }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" - }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" - }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" - }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json deleted file mode 100644 index 480d9f7..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json deleted file mode 100644 index 73a2240..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json +++ /dev/null @@ -1,32 +0,0 @@ -[ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" - }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" - }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" - }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" - }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" - }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json deleted file mode 100644 index 3149fb9..0000000 --- a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json +++ /dev/null @@ -1,52 +0,0 @@ -[ - {, - "EventCode": "0xC7", - "EventName": "STALL_SB_FULL", - "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" - }, - {, - "EventCode": "0xE0", - "EventName": "OTHER_IQ_DEP_STALL", - "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" - }, - {, - "EventCode": "0xE1", - "EventName": "IC_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" - }, - {, - "EventCode": "0xE2", - "EventName": "IUTLB_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" - }, - {, - "EventCode": "0xE3", - "EventName": "DECODE_DEP_STALL", - "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" - }, - {, - "EventCode": "0xE4", - "EventName": "OTHER_INTERLOCK_STALL", - "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" - }, - {, - "EventCode": "0xE5", - "EventName": "AGU_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" - }, - {, - "EventCode": "0xE6", - "EventName": "SIMD_DEP_STALL", - "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." - }, - {, - "EventCode": "0xE7", - "EventName": "LD_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" - }, - {, - "EventCode": "0xE8", - "EventName": "ST_DEP_STALL", - "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 952a05c..cf14e23 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core -0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core From patchwork Tue Feb 6 17:45:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127048 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3097154ljc; Tue, 6 Feb 2018 09:00:52 -0800 (PST) X-Google-Smtp-Source: AH8x2270o+IORIfHqrRJSivw6GOEVutMb45N8XSDprRj0gIXMwAbTs0ejjYQz5kfmvP4VZSAKnhF X-Received: by 2002:a17:902:15c5:: with SMTP id a5-v6mr3021451plh.277.1517936452457; Tue, 06 Feb 2018 09:00:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936452; cv=none; d=google.com; s=arc-20160816; b=tY75uUsGf8aniwdc57wqaZl5kibx8VzGoGU8Ci8ruwDp3o8tt/4w42G6FYGcJF+YaQ 1Y1lqQCjnf+UFeRByjvBMMOApkfGuvxm/gqgbomu/JOi5mQn8Y875T1DicGe2TSgZ8w+ 5h3YQ6xROeyEax4pCfdJkfs3NJkokBGpbDjzGO7wzkPzpzcizuNqNzTEjiHROS7+Fae1 H8G22MiIJneiKmV9hgbL22cJ2tNPyWSxHqxSXtgwMtyFtfTQBrfsgFgvTOUYY/42529C 0qj6/kFn87KqEL2DL5NP+9FDOmTEFeV0FqpTCVL5cquiahQW8IOabp7LhrKwv28ElLo6 jxgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OAjTJDbZpp0wDegvpOwKwkZmOqNppgeCGvMzJELYaiU=; b=mOvAqH/SNwSJPfLOlAu3YlwfBjBcEdO7wbAPHC45FcbjbRe7ONUrWFLQXtydvfY/Jm o/GEhnt3KwVYTV8Op4abajuyyt1GI8dR3xnf4CqyjkhRAXHPOpTPq+iaa8uHTSE90uUC C/XlfTJsWWPnY2q5ssr6lVFDXK54NL02tK9VTiqEbqUNodBboPeq3qWNb4+mp2w3paQc cyPq7DDe2XYicGwsGni+zHOXSdsbHRYKArXWhFP+d2nwsSWzeHHc7s1vF0eW0yzZe6e5 ax2/mGw64jH4k5DLU07o2bW3LJXO0nnifGg72gj7rOj2gyQsmVgtBhttZxvjQ7m4AO9y kk9w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c17si1382757pgu.341.2018.02.06.09.00.52; Tue, 06 Feb 2018 09:00:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753354AbeBFRAu (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:50 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51560 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753086AbeBFQ4C (ORCPT ); Tue, 6 Feb 2018 11:56:02 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 6120C9A7346DF; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:52 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 5/9] perf utils: add support for arch standard events Date: Wed, 7 Feb 2018 01:45:00 +0800 Message-ID: <1517939104-230881-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some architectures (like arm), there are architecture- defined events. Sometimes these events may be "recommended" according to the architecture standard, in that the implementer is free ignore the "recommendation" and create its custom event. This patch adds support for parsing standard events from arch-defined JSONs, and fixing up vendor events when they have implemented these events as standard. Support is also ensured that the vendor may implement their own custom events. A new step is added to the pmu events parsing to fix up the vendor events with the arch-standard events. The arch-defined JSONs must be placed in the arch root folder for preprocessing prior to tree JSON processing. In the vendor JSON, to specify that the arch event is supported, the keyword "ArchStdEvent" should be used, like this: [ { "ArchStdEvent": "0x41", "BriefDescription": "L1D cache access, write" }, ] No other JSON objects are strictly required. However, for other objects added, these take precedence over architecture defined standard events, thus supporting separate events which have the same event code. Signed-off-by: John Garry --- tools/perf/pmu-events/Build | 1 + tools/perf/pmu-events/README | 6 ++ tools/perf/pmu-events/jevents.c | 185 +++++++++++++++++++++++++++++++++++++--- 3 files changed, 182 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 999a4e8..f9e8466 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -1,5 +1,6 @@ hostprogs := jevents +CHOSTFLAGS = -I$(srctree)/tools/include jevents-y += json.o jsmn.o jevents.o pmu-events-y += pmu-events.o JDIR = pmu-events/arch/$(SRCARCH) diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README index 655286f..cff4c91 100644 --- a/tools/perf/pmu-events/README +++ b/tools/perf/pmu-events/README @@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo. - Directories are traversed, but all other files are ignored. + - To reduce JSON event duplication per architecture, platform JSONs may + use "ArchStdEvent" keyword to dereference an "Architecture standard + events", defined in architecture standard JSONs. + Architecture standard JSONs must be located in the architecture root + folder. + The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index eb183b1..19e30cd 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -44,6 +44,7 @@ #include /* getrlimit */ #include #include +#include #include "jsmn.h" #include "json.h" #include "jevents.h" @@ -366,6 +367,67 @@ static int print_events_table_entry(void *data, char *name, char *event, return 0; } +struct event_struct { + char *name; + char *event; + char *desc; + char *long_desc; + char *pmu; + char *filter; + char *perpkg; + char *unit; + char *metric_expr; + char *metric_name; + char *metric_group; + struct list_head list; + char strings[]; +}; + +static LIST_HEAD(arch_std_events); + +#define ADD_EVENT_STRING(string) do { if (string) { \ + es->string = strings; \ + strings += snprintf(strings, len, "%s", string) + 1; \ +} } while (0) + +static int save_arch_std_events(void *data, char *name, char *event, + char *desc, char *long_desc, char *pmu, + char *unit, char *perpkg, char *metric_expr, + char *metric_name, char *metric_group) +{ + struct event_struct *es; + struct stat *sb = data; + int len; + char *strings; + + /* + * Lazily allocate size of the json file to hold the + * strings, which would be more than large enough. + */ + len = sb->st_size; + + es = malloc(sizeof(*es) + len); + if (!es) + return -ENOMEM; + memset(es, 0, sizeof(*es)); + list_add_tail(&es->list, &arch_std_events); + + strings = &es->strings[0]; + + ADD_EVENT_STRING(name); + ADD_EVENT_STRING(event); + ADD_EVENT_STRING(desc); + ADD_EVENT_STRING(long_desc); + ADD_EVENT_STRING(pmu); + ADD_EVENT_STRING(unit); + ADD_EVENT_STRING(perpkg); + ADD_EVENT_STRING(metric_expr); + ADD_EVENT_STRING(metric_name); + ADD_EVENT_STRING(metric_group); + + return 0; +} + static void print_events_table_suffix(FILE *outfp) { fprintf(outfp, "{\n"); @@ -407,6 +469,52 @@ static char *real_event(const char *name, char *event) return event; } +static void fixup_field(char *from, char **to) +{ + *to = malloc(strlen(from)); + + strcpy(*to, from); +} + +#define EVENT_PREFIX "event=" + +#define TRY_FIXUP_FIELD(string) do { if (es->string && !*string)\ + fixup_field(es->string, string); \ +} while (0) + +static int +try_fixup(const char *fn, char *arch_std, char **event, char **desc, + char **name, char **long_desc, char **pmu, char **filter, + char **perpkg, char **unit, char **metric_expr, char **metric_name, + char **metric_group) +{ + /* try to find matching event from arch standard values */ + struct event_struct *es; + + list_for_each_entry(es, &arch_std_events, list) { + if (!strcmp(arch_std, es->event+strlen(EVENT_PREFIX))) { + /* now fixup */ + fixup_field(es->event, event); + TRY_FIXUP_FIELD(desc); + TRY_FIXUP_FIELD(name); + TRY_FIXUP_FIELD(long_desc); + TRY_FIXUP_FIELD(pmu); + TRY_FIXUP_FIELD(filter); + TRY_FIXUP_FIELD(perpkg); + TRY_FIXUP_FIELD(unit); + TRY_FIXUP_FIELD(metric_expr); + TRY_FIXUP_FIELD(metric_name); + TRY_FIXUP_FIELD(metric_group); + + return 0; + } + } + + pr_err("%s: could not find matching %s for %s\n", + prog, arch_std, fn); + return -1; +} + /* Call func with each event in the json file */ int json_events(const char *fn, int (*func)(void *data, char *name, char *event, char *desc, @@ -442,6 +550,7 @@ int json_events(const char *fn, char *metric_expr = NULL; char *metric_name = NULL; char *metric_group = NULL; + char *arch_std = NULL; unsigned long long eventcode = 0; struct msrmap *msr = NULL; jsmntok_t *msrval = NULL; @@ -527,6 +636,10 @@ int json_events(const char *fn, addfield(map, &metric_expr, "", "", val); for (s = metric_expr; *s; s++) *s = tolower(*s); + } else if (json_streq(map, field, "ArchStdEvent")) { + addfield(map, &arch_std, "", "", val); + for (s = arch_std; *s; s++) + *s = tolower(*s); } /* ignore unknown fields */ } @@ -538,7 +651,7 @@ int json_events(const char *fn, addfield(map, &extra_desc, " ", "(Precise event)", NULL); } - snprintf(buf, sizeof buf, "event=%#llx", eventcode); + snprintf(buf, sizeof(buf), "%s%#llx", EVENT_PREFIX, eventcode); addfield(map, &event, ",", buf, NULL); if (desc && extra_desc) addfield(map, &desc, " ", extra_desc, NULL); @@ -550,9 +663,21 @@ int json_events(const char *fn, addfield(map, &event, ",", msr->pname, msrval); if (name) fixname(name); - - err = func(data, name, real_event(name, event), desc, long_desc, - pmu, unit, perpkg, metric_expr, metric_name, metric_group); + err = 0; + if (arch_std) { + /* + * An arch standard event is referenced, so try to + * fixup any unassigned values. + */ + err = try_fixup(fn, arch_std, &event, &desc, &name, + &long_desc, &pmu, &filter, &perpkg, + &unit, &metric_expr, &metric_name, + &metric_group); + } + if (!err) + err = func(data, name, real_event(name, event), desc, + long_desc, pmu, unit, perpkg, metric_expr, + metric_name, metric_group); free(event); free(desc); free(name); @@ -565,6 +690,7 @@ int json_events(const char *fn, free(metric_expr); free(metric_name); free(metric_group); + if (err) break; tok += j; @@ -789,6 +915,32 @@ static int is_leaf_dir(const char *fpath) return res; } +static int is_json_file(const char *name) +{ + const char *suffix; + + if (strlen(name) < 5) + return 0; + + suffix = name + strlen(name) - 5; + + if (strncmp(suffix, ".json", 5) == 0) + return 1; + return 0; +} + +static int preprocess_arch_std_files(const char *fpath, const struct stat *sb, + int typeflag, struct FTW *ftwbuf) +{ + int level = ftwbuf->level; + int is_file = typeflag == FTW_F; + + if (level == 1 && is_file && is_json_file(fpath)) + return json_events(fpath, save_arch_std_events, (void *)sb); + + return 0; +} + static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { @@ -876,9 +1028,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, * ignore it. It could be a readme.txt for instance. */ if (is_file) { - char *suffix = bname + strlen(bname) - 5; - - if (strncmp(suffix, ".json", 5)) { + if (!is_json_file(bname)) { pr_info("%s: Ignoring file without .json suffix %s\n", prog, fpath); return 0; @@ -940,6 +1090,7 @@ int main(int argc, char *argv[]) const char *output_file; const char *start_dirname; struct stat stbuf; + struct event_struct *es1, *es2; prog = basename(argv[0]); if (argc < 4) { @@ -984,17 +1135,28 @@ int main(int argc, char *argv[]) maxfds = get_maxfds(); mapfile = NULL; + rc = nftw(ldirname, preprocess_arch_std_files, get_maxfds(), 0); + if (rc && verbose) { + pr_info("%s: Error preprocessing arch standard files %s\n", + prog, ldirname); + goto empty_map; + } else if (rc < 0) { + /* Make build fail */ + return 1; + } rc = nftw(ldirname, process_one_file, maxfds, 0); if (rc && verbose) { pr_info("%s: Error walking file tree %s\n", prog, ldirname); - goto empty_map; + goto free_standard_arch_events; } else if (rc < 0) { /* Make build fail */ return 1; - } else if (rc) { - goto empty_map; } + /* Free memories for architecture standard events */ + list_for_each_entry_safe(es1, es2, &arch_std_events, list) + free(es1); + if (close_table) print_events_table_suffix(eventsfp); @@ -1011,6 +1173,9 @@ int main(int argc, char *argv[]) return 0; +free_standard_arch_events: + list_for_each_entry_safe(es1, es2, &arch_std_events, list) + free(es1); empty_map: fclose(eventsfp); create_empty_mapping(output_file); From patchwork Tue Feb 6 17:45:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127036 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3094339ljc; Tue, 6 Feb 2018 08:57:38 -0800 (PST) X-Google-Smtp-Source: AH8x225yzAvTj9vK7WV/ks4GWdXhzOCaVH31fUC3T0cfvqpnx2/7AUn3BJZTt8bd/L//82RxKN0s X-Received: by 10.98.170.24 with SMTP id e24mr3036899pff.177.1517936257827; Tue, 06 Feb 2018 08:57:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936257; cv=none; d=google.com; s=arc-20160816; b=cip3A2UuY+tPeV7AeXbHNfbE2TClW8NJzJd3P9baCwJz4SObVm8y0E8HgyXw5LqB5E Rs2FVyQT5pnglt0NaJJ5zTnXanNyUJnNjWrzjJ2Omufi/M8M+hHE3qr7mfWpQ4Z0svHN slh1lTO0k2QLLe9xt6Nz61hKDvkmYESe/oThSwpzCXH3MFDC+RMu2E9IoOsbwq4iw3Gz bk2Q13QlalmNuz3r6Fsbjrj9/2uCrIHCxyyeIaKFWK8Cq19M4EVnsRF5Yc2zvBXQ1Wi+ fc5cOO+VN+ONI3XYslBMClD5gMfxvYknxkzv03HZCZq4lgC2iULCyPM/I2dU3SjvYeSb ce3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=VIZjMVfclJRYeGMpuI3aPi9PrGNWBIgFil9HAwLKamY=; b=KHex2+c0EiOPqSRwGRYxPmqMo+RXQY8XqgmXIJXEW3k/nmcsNjera+DcjA8NTs6lk/ 7iA9Tbuxtl/i+NgJGVoUPzRc46Kl4NnMLN4rYMth1Q4z5A8LlHXhVy25QLpW7GuWvGVT Md9a+f6h+UYb9D1AkC3PJ2uPEWgOtP2XbWbSWiLw7/IqgilppQkn4LPPEpc75SsoILuJ PV5wTa2E83dCBjXqSXbQOPyQPmFDVMd/6l9hl81tonIBiGLTs6ym7QmpE+q3ZYbCKxtU nB86WehEnV6c0UA1VX6TXuepfv5lxdl1zI6UOHpm6ca9iJL5NwHb+yakMgS3LFRHo4oM ASqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b59-v6si1814697plc.302.2018.02.06.08.57.37; Tue, 06 Feb 2018 08:57:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753327AbeBFQ5e (ORCPT + 21 others); Tue, 6 Feb 2018 11:57:34 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51700 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753252AbeBFQ4I (ORCPT ); Tue, 6 Feb 2018 11:56:08 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 989DF5BBD41FA; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:52 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 6/9] perf utils: add armv8-recommended.json Date: Wed, 7 Feb 2018 01:45:01 +0800 Message-ID: <1517939104-230881-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events. The JSON is copied from ARMv8 architecture reference manual, available here: https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf Signed-off-by: John Garry Signed-off-by: Shaokun Zhang --- .../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json new file mode 100644 index 0000000..6328828 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -0,0 +1,452 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "L1D_CACHE_RD", + "BriefDescription": "L1D cache access, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write", + "EventCode": "0x41", + "EventName": "L1D_CACHE_WR", + "BriefDescription": "L1D cache access, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "L1D_CACHE_REFILL_RD", + "BriefDescription": "L1D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "L1D_CACHE_REFILL_WR", + "BriefDescription": "L1D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, inner", + "EventCode": "0x44", + "EventName": "L1D_CACHE_REFILL_INNER", + "BriefDescription": "L1D cache refill, inner" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, outer", + "EventCode": "0x45", + "EventName": "L1D_CACHE_REFILL_OUTER", + "BriefDescription": "L1D cache refill, outer" + }, + { + "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", + "EventCode": "0x46", + "EventName": "L1D_CACHE_WB_VICTIM", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", + "EventCode": "0x47", + "EventName": "L1D_CACHE_WB_CLEAN", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 1 data cache invalidate", + "EventCode": "0x48", + "EventName": "L1D_CACHE_INVAL", + "BriefDescription": "L1D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "L1D_TLB_REFILL_RD", + "BriefDescription": "L1D tlb refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "L1D_TLB_REFILL_WR", + "BriefDescription": "L1D tlb refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "L1D_TLB_RD", + "BriefDescription": "L1D tlb access, read" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "L1D_TLB_WR", + "BriefDescription": "L1D tlb access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, read", + "EventCode": "0x50", + "EventName": "L2D_CACHE_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, write", + "EventCode": "0x51", + "EventName": "L2D_CACHE_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, read", + "EventCode": "0x52", + "EventName": "L2D_CACHE_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, write", + "EventCode": "0x53", + "EventName": "L2D_CACHE_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache Write-Back, victim", + "EventCode": "0x56", + "EventName": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency", + "EventCode": "0x57", + "EventName": "L2D_CACHE_WB_CLEAN", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 2 data cache invalidate", + "EventCode": "0x58", + "EventName": "L2D_CACHE_INVAL", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", + "EventCode": "0x5c", + "EventName": "L2D_TLB_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, write", + "EventCode": "0x5d", + "EventName": "L2D_TLB_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, read", + "EventCode": "0x5e", + "EventName": "L2D_TLB_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, write", + "EventCode": "0x5f", + "EventName": "L2D_TLB_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "BUS_ACCESS_RD", + "BriefDescription": "Bus access read" + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "BUS_ACCESS_WR", + "BriefDescription": "Bus access write" + } + { + "PublicDescription": "Bus access, Normal, Cacheable, Shareable", + "EventCode": "0x62", + "EventName": "BUS_ACCESS_SHARED", + "BriefDescription": "Bus access, Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", + "EventCode": "0x63", + "EventName": "BUS_ACCESS_NOT_SHARED", + "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, Normal", + "EventCode": "0x64", + "EventName": "BUS_ACCESS_NORMAL", + "BriefDescription": "Bus access, Normal" + } + { + "PublicDescription": "Bus access, peripheral", + "EventCode": "0x65", + "EventName": "BUS_ACCESS_PERIPH", + "BriefDescription": "Bus access, peripheral" + } + { + "PublicDescription": "Data memory access, read", + "EventCode": "0x66", + "EventName": "MEM_ACCESS_RD", + "BriefDescription": "Data memory access, read" + } + { + "PublicDescription": "Data memory access, write", + "EventCode": "0x67", + "EventName": "MEM_ACCESS_WR", + "BriefDescription": "Data memory access, write" + } + { + "PublicDescription": "Unaligned access, read", + "EventCode": "0x68", + "EventName": "UNALIGNED_LD_SPEC", + "BriefDescription": "Unaligned access, read" + } + { + "PublicDescription": "Unaligned access, write", + "EventCode": "0x69", + "EventName": "UNALIGNED_ST_SPEC", + "BriefDescription": "Unaligned access, write" + } + { + "PublicDescription": "Unaligned access", + "EventCode": "0x6a", + "EventName": "UNALIGNED_LDST_SPEC", + "BriefDescription": "Unaligned access" + } + { + "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", + "EventCode": "0x6c", + "EventName": "LDREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", + "EventCode": "0x6d", + "EventName": "STREX_PASS_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", + "EventCode": "0x6e", + "EventName": "STREX_FAIL_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", + "EventCode": "0x6f", + "EventName": "STREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" + } + { + "PublicDescription": "Operation speculatively executed, load", + "EventCode": "0x70", + "EventName": "LD_SPEC", + "BriefDescription": "Operation speculatively executed, load" + } + { + "PublicDescription": "Operation speculatively executed, store" + "EventCode": "0x71", + "EventName": "ST_SPEC", + "BriefDescription": "Operation speculatively executed, store" + } + { + "PublicDescription": "Operation speculatively executed, load or store", + "EventCode": "0x72", + "EventName": "LDST_SPEC", + "BriefDescription": "Operation speculatively executed, load or store" + } + { + "PublicDescription": "Operation speculatively executed, integer data processing", + "EventCode": "0x73", + "EventName": "DP_SPEC", + "BriefDescription": "Operation speculatively executed, integer data processing" + } + { + "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", + "EventCode": "0x74", + "EventName": "ASE_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", + } + { + "PublicDescription": "Operation speculatively executed, floating-point instruction", + "EventCode": "0x75", + "EventName": "VFP_SPEC", + "BriefDescription": "Operation speculatively executed, floating-point instruction" + } + { + "PublicDescription": "Operation speculatively executed, software change of the PC", + "EventCode": "0x76", + "EventName": "PC_WRITE_SPEC", + "BriefDescription": "Operation speculatively executed, software change of the PC" + } + { + "PublicDescription": "Operation speculatively executed, Cryptographic instruction", + "EventCode": "0x77", + "EventName": "CRYPTO_SPEC", + "BriefDescription": "Operation speculatively executed, Cryptographic instruction" + } + { + "PublicDescription": "Branch speculatively executed, immediate branch" + "EventCode": "0x78", + "EventName": "BR_IMMED_SPEC", + "BriefDescription": "Branch speculatively executed, immediate branch" + } + { + "PublicDescription": "Branch speculatively executed, procedure return" + "EventCode": "0x79", + "EventName": "BR_RETURN_SPEC", + "BriefDescription": "Branch speculatively executed, procedure return" + } + { + "PublicDescription": "Branch speculatively executed, indirect branch" + "EventCode": "0x7a", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed, indirect branch" + } + { + "PublicDescription": "Barrier speculatively executed, ISB" + "EventCode": "0x7c", + "EventName": "ISB_SPEC", + "BriefDescription": "Barrier speculatively executed, ISB" + } + { + "PublicDescription": "Barrier speculatively executed, DSB" + "EventCode": "0x7d", + "EventName": "DSB_SPEC", + "BriefDescription": "Barrier speculatively executed, DSB" + } + { + "PublicDescription": "Barrier speculatively executed, DMB" + "EventCode": "0x7e", + "EventName": "DMB_SPEC", + "BriefDescription": "Barrier speculatively executed, DMB" + } + { + "PublicDescription": "Exception taken, Other synchronous" + "EventCode": "0x81", + "EventName": "EXC_UNDEF", + "BriefDescription": "Exception taken, Other synchronous" + } + { + "PublicDescription": "Exception taken, Supervisor Call" + "EventCode": "0x82", + "EventName": "EXC_SVC", + "BriefDescription": "Exception taken, Supervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort" + "EventCode": "0x83", + "EventName": "EXC_PABORT", + "BriefDescription": "Exception taken, Instruction Abort" + } + { + "PublicDescription": "Exception taken, Data Abort and SError" + "EventCode": "0x84", + "EventName": "EXC_DABORT", + "BriefDescription": "Exception taken, Data Abort and SError" + } + { + "PublicDescription": "Exception taken, IRQ" + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + } + { + "PublicDescription": "Exception taken, FIQ" + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + } + { + "PublicDescription": "Exception taken, Secure Monitor Call" + "EventCode": "0x88", + "EventName": "EXC_SMC", + "BriefDescription": "Exception taken, Secure Monitor Call" + } + { + "PublicDescription": "Exception taken, Hypervisor Call" + "EventCode": "0x8a", + "EventName": "EXC_HVC", + "BriefDescription": "Exception taken, Hypervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "EventCode": "0x8b", + "EventName": "EXC_TRAP_PABORT", + "BriefDescription": "Exception taken, Instruction Abort not taken locally" + } + { + "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "EventCode": "0x8c", + "EventName": "EXC_TRAP_DABORT", + "BriefDescription": "Exception taken, Data Abort or SError not taken locally" + } + { + "PublicDescription": "Exception taken, Other traps not taken locally" + "EventCode": "0x8d", + "EventName": "EXC_TRAP_OTHER", + "BriefDescription": "Exception taken, Other traps not taken locally" + } + { + "PublicDescription": "Exception taken, IRQ not taken locally" + "EventCode": "0x8e", + "EventName": "EXC_TRAP_IRQ", + "BriefDescription": "Exception taken, IRQ not taken locally" + } + { + "PublicDescription": "Exception taken, FIQ not taken locally" + "EventCode": "0x8f", + "EventName": "EXC_TRAP_FIQ", + "BriefDescription": "Exception taken, FIQ not taken locally" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire" + "EventCode": "0x90", + "EventName": "RC_LD_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Store-Release" + "EventCode": "0x91", + "EventName": "RC_ST_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Store-Release" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, read" + "EventCode": "0xa0", + "EventName": "L3D_CACHE_RD", + "BriefDescription": "Attributable Level 3 data or unified cache access, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, write" + "EventCode": "0xa1", + "EventName": "L3D_CACHE_WR", + "BriefDescription": "Attributable Level 3 data or unified cache access, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, read" + "EventCode": "0xa2", + "EventName": "L3D_CACHE_REFILL_RD", + "BriefDescription": "Attributable Level 3 data or unified cache refill, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, write" + "EventCode": "0xa3", + "EventName": "L3D_CACHE_REFILL_WR", + "BriefDescription": "Attributable Level 3 data or unified cache refill, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + "EventCode": "0xa6", + "EventName": "L3D_CACHE_WB_VICTIM", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + "EventCode": "0xa7", + "EventName": "L3D_CACHE_WB_CLEAN", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate" + "EventCode": "0xa8", + "EventName": "L3D_CACHE_INVAL", + "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate" + } +] From patchwork Tue Feb 6 17:45:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127044 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096380ljc; Tue, 6 Feb 2018 09:00:15 -0800 (PST) X-Google-Smtp-Source: AH8x225EvT0ga/zCXbt4Q+mQ3OF7RlUh5+884hxVFNnlitcXOjBdCc7mCnP/NjVsAnMER9jWg1x8 X-Received: by 2002:a17:902:8607:: with SMTP id f7-v6mr3033321plo.273.1517936415724; Tue, 06 Feb 2018 09:00:15 -0800 (PST) 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[209.132.180.67]) by mx.google.com with ESMTP id s13-v6si9013984plq.557.2018.02.06.09.00.15; Tue, 06 Feb 2018 09:00:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753226AbeBFRAN (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:13 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51743 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752927AbeBFQ4J (ORCPT ); Tue, 6 Feb 2018 11:56:09 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BD8BFDC9D9354; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:52 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 7/9] perf utils: fixup Cavium ThunderX2 JSON to use ARMv8 recommended events Date: Wed, 7 Feb 2018 01:45:02 +0800 Message-ID: <1517939104-230881-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. The brief description is kept for readability for arch standard events, but is not strictly required. Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 60 ++++++++-------------- 1 file changed, 20 insertions(+), 40 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c4..f47bf0f 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,42 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D cache refill, inner" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "0x60", + "BriefDescription": "Bus access read" }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "0x61", + "BriefDescription": "Bus access write" } ] From patchwork Tue Feb 6 17:45:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127037 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3094447ljc; Tue, 6 Feb 2018 08:57:47 -0800 (PST) X-Google-Smtp-Source: AH8x225HaFunps9tG7MZuRGE0vrWDU/PS45Acs6lLQ8L7k5kYexn16xmJZw22BUEPxtZwpXqRe6+ X-Received: by 2002:a17:902:b94c:: with SMTP id h12-v6mr3033898pls.45.1517936267169; Tue, 06 Feb 2018 08:57:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936267; cv=none; d=google.com; s=arc-20160816; b=AR3rBevGGJhwvK+SkzS6LCiD549H1rCgttbcFAd5pLEXD/BxaxFDrrCQjyELfVjnLS cfH93/KJ9JvTkiRZ+dCULBTLdh9Rk92qO2LoN50x29isAi2hXtvwlwn5hNKRCx7oIl9h P8Fltlm6t17qSz+kxF5weknX4qk6G2TtyDc4pu/gJxqqVtOUHiZ+sThyx2WdAnLlaf+y 4Hmo27w+aHKmSa6aAcTcS9aldx3l0UITcn4+s3SgXOsf4O/xBFFaKPS312oaJCw5HGl1 7wyoVK5N5Oz+iSyg4VaIeEUPlSOX6SE9vdjPxp6zLchwVpjJAYt302a1bPUF54Y0vL50 awWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=7z0hq8i574nIDNMeobPh/xXQwECCH+jwR5/fsSIfoPg=; b=e0T5NlC8BEXDbxdp12M0/6ow4uy+stFRa3t1BUBnl30C0+bltlxj3uY+N6KN2KT4U6 v6PeRvR+ZStVJsoi7Fjmw2LKVEp/vXoiDdMEOFi4zI2HIv9UYsGwJ1HVy1n7HDOjcg/P ymEIZ1j0d7i6ysvy8fqhxeDPOA4M5HfvS/zipB6hS+xhfCrTTTFAZDgAwt6JytkgVYb+ 7ay9CANfqClACU0HZlpeCh+661VXul/pC12yong6mf4B8uoOriA9Wjc58iIfhVRhn/i7 D9AvMB+hikvD4Wcsj8RNzXdGXjcD5D5bnEKpmdb0bS3pjTy6YbWp/rizmhnlSyBaKrho 1d+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h61-v6si1701971pld.816.2018.02.06.08.57.46; Tue, 06 Feb 2018 08:57:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753334AbeBFQ5p (ORCPT + 21 others); Tue, 6 Feb 2018 11:57:45 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51701 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752488AbeBFQ4H (ORCPT ); Tue, 6 Feb 2018 11:56:07 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id AAFB63A52E6CD; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:53 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 8/9] perf utils: fixup ARM Cortex A53 JSONs to use ARMv8 recommended events Date: Wed, 7 Feb 2018 01:45:03 +0800 Message-ID: <1517939104-230881-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes the ARM Cortex-A53 json to use event definitions from the ARMv8 recommended events. The brief description is kept for readability for arch standard events, but is not strictly required. In addition to this change, other changes were made: - remove stray ',' - remove mirrored events in memory.json and bus.json - fixed indentation to be consistent with other ARM JSONs Signed-off-by: John Garry --- .../arch/arm64/arm/cortex-a53/branch.json | 15 ++++--- .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 24 +++-------- .../arch/arm64/arm/cortex-a53/cache.json | 40 +++++++++---------- .../arch/arm64/arm/cortex-a53/memory.json | 14 +------ .../arch/arm64/arm/cortex-a53/other.json | 46 +++++++++++----------- .../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++----- 6 files changed, 67 insertions(+), 92 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json index 3b62087..efcebaa 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -1,25 +1,24 @@ [ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" + { + "ArchStdEvent": "0x7A", + "BriefDescription": "Branch speculatively executed, indirect branch" }, - {, + { "EventCode": "0xC9", "EventName": "BR_COND", "BriefDescription": "Conditional branch executed" }, - {, + { "EventCode": "0xCA", "EventName": "BR_INDIRECT_MISPRED", "BriefDescription": "Indirect branch mispredicted" }, - {, + { "EventCode": "0xCB", "EventName": "BR_INDIRECT_MISPRED_ADDR", "BriefDescription": "Indirect branch mispredicted because of address miscompare" }, - {, + { "EventCode": "0xCC", "EventName": "BR_COND_MISPRED", "BriefDescription": "Conditional branch mispredicted" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json index 480d9f7..bbbc930 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -1,22 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" + { + "ArchStdEvent": "0x60", + "BriefDescription": "Bus access read" }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" + { + "ArchStdEvent": "0x61", + "BriefDescription": "Bus access write" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json index 11baad6..5dfbec4 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json @@ -1,27 +1,27 @@ [ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" + { + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" + { + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" + { + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" + { + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" + { + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json index 480d9f7..25ae642 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json @@ -1,20 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, + { "EventCode": "0xC0", "EventName": "EXT_MEM_REQ", "BriefDescription": "External memory request" }, - {, + { "EventCode": "0xC1", "EventName": "EXT_MEM_REQ_NC", "BriefDescription": "Non-cacheable external memory request" diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json index 73a2240..4eb17a8 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -1,32 +1,30 @@ [ - {, - "EventCode": "0x86", - "EventName": "EXC_IRQ", - "BriefDescription": "Exception taken, IRQ" + { + "ArchStdEvent": "0x86", + "BriefDescription": "Exception taken, IRQ" }, - {, - "EventCode": "0x87", - "EventName": "EXC_FIQ", - "BriefDescription": "Exception taken, FIQ" + { + "ArchStdEvent": "0x87", + "BriefDescription": "Exception taken, FIQ" }, - {, - "EventCode": "0xC6", - "EventName": "PRE_DECODE_ERR", - "BriefDescription": "Pre-decode error" + { + "EventCode": "0xC6", + "EventName": "PRE_DECODE_ERR", + "BriefDescription": "Pre-decode error" }, - {, - "EventCode": "0xD0", - "EventName": "L1I_CACHE_ERR", - "BriefDescription": "L1 Instruction Cache (data or tag) memory error" + { + "EventCode": "0xD0", + "EventName": "L1I_CACHE_ERR", + "BriefDescription": "L1 Instruction Cache (data or tag) memory error" }, - {, - "EventCode": "0xD1", - "EventName": "L1D_CACHE_ERR", - "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" + { + "EventCode": "0xD1", + "EventName": "L1D_CACHE_ERR", + "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable" }, - {, - "EventCode": "0xD2", - "EventName": "TLB_ERR", - "BriefDescription": "TLB memory error" + { + "EventCode": "0xD2", + "EventName": "TLB_ERR", + "BriefDescription": "TLB memory error" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json index 3149fb9..f45a6b5 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json @@ -1,50 +1,50 @@ [ - {, + { "EventCode": "0xC7", "EventName": "STALL_SB_FULL", "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" }, - {, + { "EventCode": "0xE0", "EventName": "OTHER_IQ_DEP_STALL", "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" }, - {, + { "EventCode": "0xE1", "EventName": "IC_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" }, - {, + { "EventCode": "0xE2", "EventName": "IUTLB_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" }, - {, + { "EventCode": "0xE3", "EventName": "DECODE_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" }, - {, + { "EventCode": "0xE4", "EventName": "OTHER_INTERLOCK_STALL", "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" }, - {, + { "EventCode": "0xE5", "EventName": "AGU_DEP_STALL", "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" }, - {, + { "EventCode": "0xE6", "EventName": "SIMD_DEP_STALL", "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." }, - {, + { "EventCode": "0xE7", "EventName": "LD_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" }, - {, + { "EventCode": "0xE8", "EventName": "ST_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a store" From patchwork Tue Feb 6 17:45:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127042 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096005ljc; Tue, 6 Feb 2018 08:59:51 -0800 (PST) X-Google-Smtp-Source: AH8x2270VP9nVmnAFYqdj8thVJUwmpntVo9c3qjLH0rMz10OzfgGYS+I/o06o3LqKbSqBB6xilqw X-Received: by 10.98.149.69 with SMTP id p66mr3018655pfd.183.1517936391236; Tue, 06 Feb 2018 08:59:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936391; cv=none; d=google.com; s=arc-20160816; b=0y5Fzh1YOISMav1nKLQRYFY0rSI69VsUEdb/hBJI6np56feG0kX9Z9ECtcgqBkbR1a D7pnISzECJYo2IueI5SgD+sI1M+73t9YJ6EXDzzxN+Dl1ZjGhmLZUX2qAold4wGagVKY Q1Xtqc+gGqI4s08kjGJHcWRYyC/RwA4ti5VcdogVy1VO5/FvUHmlJkjaNj6M3UU5QOxN TSzk61mfsxBIcCyzIvr6ATtMf0F7DyWnuRp7RKdKtYQQWnNJ582QgUUHO+hCi+iQ6oiH ZGnuXxD0XGodvYR6GiYhNyzBTlaKxDNOf9by2rqjEXiRIrFXCDh7+Qeq5C5Gj6FBfB4E GHAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=pQ273+2+E0vGy4QjuGmOIeNmOmMVqEFfXZYrz56PJKc=; b=tlA0hyN/UtH8Raq0hYkd6oXDvJzFtj3EtAXki2L7cGEj0D3RHlpJFTWTQ1Qji5Pxga wHv0KMnDzCoJ8AAU/oYBe1+x2I5HV0ylzY8RLQ5xT/gbvSD5sNSdfRFGWogxPoJvl2d0 9ADjelhb0WL9CBkQyyRk4sgc9dIs4oX7hTEYaSZ6WN7T2NvJGzW3KxhnOoWJf94SP3Db bdF9BY9HQ+4YcFyZUiT40X2JeU4VtE2Oqovh88pYAVwIRCeL9CpHr4TsemyXIHP1qjFB 5WbJjnYPKlMylevx5matHLikBr/eUMMkLH+32WeCaKfThrNu3wZ3CGuEETO5cms4zMoA Vtsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w1si5322945pgt.182.2018.02.06.08.59.50; Tue, 06 Feb 2018 08:59:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753054AbeBFQ7t (ORCPT + 21 others); Tue, 6 Feb 2018 11:59:49 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51744 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753145AbeBFQ4M (ORCPT ); Tue, 6 Feb 2018 11:56:12 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id CFD39EE5CD1A; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:53 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 9/9] perf utils: add HiSilicon hip08 JSON file Date: Wed, 7 Feb 2018 01:45:04 +0800 Message-ID: <1517939104-230881-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. The brief description is kept for readability for arch defined events, but is not strictly required. Signed-off-by: John Garry --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 140 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 141 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 0000000..ca0be5e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,140 @@ +[ + { + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" + }, + { + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" + }, + { + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" + }, + { + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" + }, + { + "ArchStdEvent": "0x46", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x47", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x48", + "BriefDescription": "L1D cache invalidate" + }, + { + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D tlb refill, read" + }, + { + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" + }, + { + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" + }, + { + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" + }, + { + "ArchStdEvent": "0x50", + "BriefDescription": "L2D cache access, read" + }, + { + "ArchStdEvent": "0x51", + "BriefDescription": "L2D cache access, write" + }, + { + "ArchStdEvent": "0x52", + "BriefDescription": "L2D cache refill, read" + }, + { + "ArchStdEvent": "0x53", + "BriefDescription": "L2D cache refill, write" + }, + { + "ArchStdEvent": "0x56", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x57", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x58", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index cf14e23..8f11aeb 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,3 +14,4 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core