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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id 21sm415740lfy.174.2020.12.09.23.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 23:22:01 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Florian Fainelli Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe PCIe reset controller Date: Thu, 10 Dec 2020 08:21:54 +0100 Message-Id: <20201210072154.20278-1-zajec5@gmail.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Rafał Miłecki This reset controller is a single register in the Broadcom's MISC block. Signed-off-by: Rafał Miłecki --- This binding got documented in the commit a269adab36d7 ("reset: simple: add BCM4908 MISC PCIe reset controller support") that sits currently in the git://git.pengutronix.de/git/pza/linux reset/next --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 55d9b56ac749..b5b772a9a51b 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -177,6 +177,21 @@ nandcs: nandcs@0 { }; }; + misc@2600 { + compatible = "brcm,misc", "simple-mfd"; + reg = <0x2600 0xe4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x2600 0xe4>; + + reset-controller@2644 { + compatible = "brcm,bcm4908-misc-pcie-reset"; + reg = <0x44 0x04>; + #reset-cells = <1>; + }; + }; + reboot { compatible = "syscon-reboot"; regmap = <&timer>;