From patchwork Fri Dec 11 17:01:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 342098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1096AC4361B for ; Fri, 11 Dec 2020 18:23:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D748F23EF3 for ; Fri, 11 Dec 2020 18:23:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404601AbgLKRCe (ORCPT ); Fri, 11 Dec 2020 12:02:34 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3607 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392627AbgLKRC0 (ORCPT ); Fri, 11 Dec 2020 12:02:26 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 11 Dec 2020 09:01:32 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 11 Dec 2020 17:01:32 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 11 Dec 2020 17:01:31 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v2 1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM Date: Fri, 11 Dec 2020 09:01:18 -0800 Message-ID: <1607706088-1437-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> References: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607706092; bh=OdeajKJ0j5APS54go9aWji3Lx0upX2LRZePHgYW8yjo=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=VtjhTy5sBr+eLvDjPh/PJSXP8TNRWaXT2TggkBVIMF28cxsk5lOxHdAF56eISv/0M oiZaH6FPQsH9roiPTsCv2gBoniHKMEF1DSi1BDOH3aC+pdJrHZ+QuNsMdlyQzimkjs S2h8KcCYgVMYkAKndMMOBKGpXhe2icp3rOfmTiF96aSf9N600LCVlUJgFbAgh7a7Jw ZtySQK/afP5wfE5Msw5A2hbUgmSe2eMQMWA9w4OWzv/pXF9jO7J303zebsS8PF7yv/ a7LtXPCATg5Qex/5hpMgZ6y5GgVlE9NxhqRJio8eWlz5lrkRXYQTquIAtLFNclyXAH Q9ciBLN8pQDMw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode. This patch adds clock ID for this to dt-binding. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index ab8b8a7..9cfcc3b 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -307,7 +307,7 @@ #define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_SPDIF 276 /* 277 */ -/* 278 */ +#define TEGRA210_CLK_QSPI_PM 278 /* 279 */ /* 280 */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ From patchwork Fri Dec 11 17:01:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 342097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A40C4361B for ; Fri, 11 Dec 2020 18:24:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7419423DE3 for ; Fri, 11 Dec 2020 18:24:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404283AbgLKRCe (ORCPT ); Fri, 11 Dec 2020 12:02:34 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:5109 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392629AbgLKRC0 (ORCPT ); Fri, 11 Dec 2020 12:02:26 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 11 Dec 2020 09:01:33 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 11 Dec 2020 17:01:32 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 11 Dec 2020 17:01:32 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v2 2/9] dt-bindings: spi: Add Tegra QSPI device tree binding Date: Fri, 11 Dec 2020 09:01:19 -0800 Message-ID: <1607706088-1437-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> References: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607706093; bh=36JHLEYe1p+6EBepHQem7ikyL8LqLLQtBVfJ11+gUik=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=d/B2F2BX6PEN2Ou1GSvQwwq8BwHfR2UU4A5Rg8z5nj5zI9gJxmXxtc1wz1h0qI7sd aU1C6JsKs+bm+Q32VZvAYEqZMrZmQDWgg66sk6klgfSj4GydDBKuFzqJAHu3sHrdBg f5BL5M1vOOZnuM44068DTqhvxnDrqqOH0kJvwg5XVadjMc0mbDP+wA/fPiGZ6YP2yv b/2nXPEF+BTIP8EjGHOeS49B3dkd3WoVFB+HE8886i58dqMhLwhAKMmhyg4zyFBSJW MwJ8yAQQ1DBYwBVJdLghznOwIVxbvxeeJCWkCKyKOJHt/WUaA38LHY2JBmk/zHzdxp KvCCukryf77qw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds YAML based device tree binding document for Tegra QSPI driver. Signed-off-by: Sowjanya Komatineni --- .../bindings/spi/nvidia,tegra210-quad.yaml | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml new file mode 100644 index 0000000..8d577c0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Quad SPI Controller + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra210-qspi + - nvidia,tegra186-qspi + - nvidia,tegra194-qspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: qspi + - const: qspi_out + + clocks: + maxItems: 2 + + resets: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: rx + - const: tx + +patternProperties: + "^.*@[0-9a-f]+": + type: object + + properties: + compatible: + description: + Compatible of the SPI device. + + reg: + maxItems: 1 + + spi-max-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum Quad SPI clocking speed of the device in Hz. + + spi-rx-bus-width: + description: + Bus width to the Quad SPI bus used for read transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] + + spi-tx-bus-width: + description: + Bus width to the Quad SPI bus used for write transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] + + nvidia,tx-clk-tap-delay: + description: + Delays the clock going out to device with this tap value. + Tap value varies based on platform design trace lengths from Tegra + QSPI to corresponding slave device. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + nvidia,rx-clk-tap-delay: + description: + Delays the clock coming in from the device with this tap value. + Tap value varies based on platform design trace lengths from Tegra + QSPI to corresponding slave device. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + required: + - reg + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - resets + +additionalProperties: true + +examples: + - | + #include + #include + #include + + spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x70410000 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&tegra_car 211>; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + flash@0 { + compatible = "spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + }; From patchwork Fri Dec 11 17:01:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 342092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FCAEC433FE for ; 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Fri, 11 Dec 2020 17:01:35 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v2 5/9] spi: spi-mem: Allow masters to transfer dummy cycles directly by hardware Date: Fri, 11 Dec 2020 09:01:24 -0800 Message-ID: <1607706088-1437-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> References: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607706096; bh=w3ehnwe0omM34FaObddURkJNKGQctD+ZomRiDYg+fkY=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=M3QtDGJ0G+ShIS2KqrK5wZz8VU8My4IP/kP7qgLkbEN9RveXHb+BLDuafNnSEfepb Jl/1QcV4ALz/6ulU1WiQXFUJz49nEI4AcFnx+CMZcYhShgSI80dlbGjxnri0AB1bSs Xib4karOu1aK6Y/NxIZHAvryLIkpyXPHvBWqXN0rdFPPboa6u7MxFrILOhcnzXz+Vt DHRgp4UV18Pms2tOZlUAtF303lwzpdfISmpiUTh8+NhrBGtTH8Mrvg4o2WbZwbeJxG 1fjnN9/qTEq7LULCLS4CYb7ge6SVuNbuCJ+O2vKBJr5CHYH2f1OUaL4C6ODj+3n6FK Jhz2B4tLt2nbQ== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds a flag SPI_MASTER_USES_HW_DUMMY_CYCLES for the controllers that support transfer of dummy cycles by the hardware directly. For controller with this flag set, spi-mem driver will skip dummy bytes transfer in the spi message. Controller drivers can get the number of dummy cycles from spi_message. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-mem.c | 18 +++++++++++------- include/linux/spi/spi.h | 8 ++++++++ 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index f3a3f19..38a523b 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -350,13 +350,17 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) } if (op->dummy.nbytes) { - memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes); - xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1; - xfers[xferpos].len = op->dummy.nbytes; - xfers[xferpos].tx_nbits = op->dummy.buswidth; - spi_message_add_tail(&xfers[xferpos], &msg); - xferpos++; - totalxferlen += op->dummy.nbytes; + if (ctlr->flags & SPI_MASTER_USES_HW_DUMMY_CYCLES) { + msg.dummy_cycles = (op->dummy.nbytes * 8) / op->dummy.buswidth; + } else { + memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes); + xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1; + xfers[xferpos].len = op->dummy.nbytes; + xfers[xferpos].tx_nbits = op->dummy.buswidth; + spi_message_add_tail(&xfers[xferpos], &msg); + xferpos++; + totalxferlen += op->dummy.nbytes; + } } if (op->data.nbytes) { diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index aa09fdc..2024149 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -512,6 +512,8 @@ struct spi_controller { #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ +#define SPI_MASTER_USES_HW_DUMMY_CYCLES BIT(6) /* HW dummy bytes transfer */ + /* flag indicating this is an SPI slave controller */ bool slave; @@ -1022,6 +1024,12 @@ struct spi_message { unsigned actual_length; int status; + /* + * dummy cycles in the message transfer. This is used by the controller + * drivers supports transfer of dummy cycles directly by the hardware. + */ + u8 dummy_cycles; + /* for optional use by whatever driver currently owns the * spi_message ... between calls to spi_async and then later * complete(), that's the spi_controller controller driver. From patchwork Fri Dec 11 17:01:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 342096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C0FC4361B for ; Fri, 11 Dec 2020 18:26:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B4DF323DE3 for ; Fri, 11 Dec 2020 18:26:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404074AbgLKRCd (ORCPT ); Fri, 11 Dec 2020 12:02:33 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2199 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392681AbgLKRC0 (ORCPT ); Fri, 11 Dec 2020 12:02:26 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 11 Dec 2020 09:01:36 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 11 Dec 2020 17:01:36 +0000 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 11 Dec 2020 17:01:36 +0000 From: Sowjanya Komatineni To: , , , , CC: , , , , Subject: [PATCH v2 6/9] spi: tegra210-quad: Add support for hardware dummy cycles Date: Fri, 11 Dec 2020 09:01:25 -0800 Message-ID: <1607706088-1437-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> References: <1607706088-1437-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607706096; bh=UDrsTDiQs8eElO67iIY2kdbQNgxNBN6S/8FNEm5eF/U=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=EVqGco5u6jN2kJlsz1g+D7jTfOt45rROyZytYB3YzeTdl7f8//XEuBk3WsPu9Revz qVpmGDKP4XcCiznOR+yJtj/RvY0H07LyiTfGjAj8nBSYClJp9fWhhuJT8em5QeXyQM jIY1Rsvq4aDjVxTfPQikx5jEjrNlcaSHURpz2EnBlyyDc8fZg4BV4DZ+l/v/UsppQa FDzDIbl9tHd14uyMlrF0Bx5iX9qsdgCdfYbfP7u/VVYj/1JQ732nOCv/Siwq1obdrj 3tYUrEldRIlxUsJLSBJl9Oqzq9We6OftSpWYUr05mnm6clg6IsfrCee9tiISqkQC2o XYq8hiG3NYGaQ== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra Quad SPI controller hardware supports sending dummy cycles after address bytes. This patch adds this support. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra210-quad.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 624f395..1d1b125 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -124,6 +124,13 @@ #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) #define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) +enum transfer_phase { + CMD_BYTE_XFER = 0, + ADDR_BYTES_XFER, + DATA_BYTES_XFER, + MAX_XFERS, +}; + struct tegra_qspi_client_data { int tx_clk_tap_delay; int rx_clk_tap_delay; @@ -857,6 +864,8 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi, tqspi->command1_reg = command1; + tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG); + ret = tegra_qspi_flush_fifos(tqspi, false); if (ret < 0) return ret; @@ -977,7 +986,7 @@ static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi struct spi_device *spi = msg->spi; struct spi_transfer *xfer; bool is_first_msg = true; - int ret; + int ret, xfer_phase = 0; msg->status = 0; msg->actual_length = 0; @@ -987,6 +996,15 @@ static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi list_for_each_entry(xfer, &msg->transfers, transfer_list) { u32 cmd1; + /* + * Program dummy clock cycles in Tegra QSPI register only + * during address transfer phase. + */ + if (xfer_phase == ADDR_BYTES_XFER) + tqspi->dummy_cycles = msg->dummy_cycles; + else + tqspi->dummy_cycles = 0; + reinit_completion(&tqspi->xfer_completion); cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg); @@ -1018,6 +1036,7 @@ static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi } msg->actual_length += xfer->len; + xfer_phase++; complete_xfer: if (ret < 0) { @@ -1203,6 +1222,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_MASTER_USES_HW_DUMMY_CYCLES; master->setup = tegra_qspi_setup; master->cleanup = tegra_qspi_cleanup; master->transfer_one_message = tegra_qspi_transfer_one_message;