From patchwork Thu Dec 10 12:49:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 342202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FD5AC433FE for ; Thu, 10 Dec 2020 12:51:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5425523D25 for ; Thu, 10 Dec 2020 12:51:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733226AbgLJMun (ORCPT ); Thu, 10 Dec 2020 07:50:43 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46754 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732831AbgLJMua (ORCPT ); Thu, 10 Dec 2020 07:50:30 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BACnU1i047474; Thu, 10 Dec 2020 06:49:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607604570; bh=Dtt2z35S/y3LA+4MvOenkJyQyKKN9WQT4N5VF53o60w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HAL9jNYaxJm5Fi6cYcACaIkKzmwXftMXFML/j+42tAMNKAkg+llzOAdTfXjKpX+UU Uz0GdS6QHUH2PE6UdJatoGDoyUPffQhP0Erp3TnJrDtHbOfjA2V9Sd+4adDPARl2S0 lmNdI2xZHg7BYhwph/G4nqnEMKaYp+RDDQTtei0w= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BACnUjb108594 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Dec 2020 06:49:30 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 10 Dec 2020 06:49:30 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 10 Dec 2020 06:49:30 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BACnKJM112244; Thu, 10 Dec 2020 06:49:24 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Tom Joseph , Lorenzo Pieralisi CC: , , , , Subject: [RESEND PATCH 1/4] dt-bindings: pci: ti, j721e: Fix "ti, syscon-pcie-ctrl" to take argument Date: Thu, 10 Dec 2020 18:19:14 +0530 Message-ID: <20201210124917.24185-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201210124917.24185-1-kishon@ti.com> References: <20201210124917.24185-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with argument. The argument is the register offset within "syscon" used to configure PCIe controller. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC") Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC") Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 11 +++++++---- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 11 +++++++---- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 3ae3e1a2d4b0..3766565cf258 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -29,9 +29,12 @@ properties: - const: mem ti,syscon-pcie-ctrl: - description: Phandle to the SYSCON entry required for configuring PCIe mode - and link speed. - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON + description: Specifier for configuring PCIe mode and link speed. power-domains: maxItems: 1 @@ -80,7 +83,7 @@ examples: <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x08000000>; reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index ee7a8eade3f6..2b6a1a5eaf7a 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -29,9 +29,12 @@ properties: - const: cfg ti,syscon-pcie-ctrl: - description: Phandle to the SYSCON entry required for configuring PCIe mode - and link speed. - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON + description: Specifier for configuring PCIe mode and link speed. power-domains: maxItems: 1 @@ -90,7 +93,7 @@ examples: <0x00 0x0d000000 0x00 0x00800000>, <0x00 0x10000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; From patchwork Thu Dec 10 12:49:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 341209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A992BC0018C for ; Thu, 10 Dec 2020 12:53:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58C3323D99 for ; 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Thu, 10 Dec 2020 06:49:34 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 10 Dec 2020 06:49:33 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 10 Dec 2020 06:49:33 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BACnKJN112244; Thu, 10 Dec 2020 06:49:30 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Tom Joseph , Lorenzo Pieralisi CC: , , , , Subject: [RESEND PATCH 2/4] dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC Date: Thu, 10 Dec 2020 18:19:15 +0530 Message-ID: <20201210124917.24185-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201210124917.24185-1-kishon@ti.com> References: <20201210124917.24185-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add host mode dt-bindings for TI's J7200 SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 2b6a1a5eaf7a..0880a613ece6 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-host + oneOf: + - description: PCIe controller in J7200 + items: + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in J721E + items: + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -51,7 +57,11 @@ properties: const: 0x104c device-id: - const: 0xb00d + oneOf: + - items: + - const: 0xb00d + - items: + - const: 0xb00f msi-map: true From patchwork Thu Dec 10 12:49:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 341039 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5499391jai; Thu, 10 Dec 2020 04:53:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOTjiqHI7Tl+d9HexEIaZXx3x8k3T7C+dvcxmdPCzRcFME60erBT7jMmw6suc/Nly0CXti X-Received: by 2002:a50:8163:: with SMTP id 90mr6512780edc.142.1607604794323; Thu, 10 Dec 2020 04:53:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607604794; cv=none; d=google.com; s=arc-20160816; b=Nk+opd/h0YZxYdsrggLbiKcz7WsyS6mYQ4eqnW74wyqEmKt0HxbRNfkOwnLDHtKON1 62s86arDfK3l9x9G4sNh6L7YBLJLl2qUJZQtrdcbPVjqkeHEv9oTNHODdlo/4JnTqM26 tyo58KMO0JtOdBJJUHM1jrVFyBvShZTtc6wqnpszHVOg/tOS099TxcwtGb4nNkTSx+ra BQp87wPfgDPlUPIATTs8B0/7J8T2z3OQXPydXotvHTFOf/XnZKZ6VC34PxYJiN94SeU7 S9TichhQ04pAgW/uJxPY2fx8afZRhJkBeuBj5mTd3oysAriKr+V2tNUToHpWg+YtodAo geAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=R1MaPbeUY9MQuLOK++4xDkqG3NqXBK7qSXA9xOtlxUo=; b=jc0k/GrPL/LiQBQhI1iD+P9TuHuO4vS1SR+s2u5jy9/EfOhAoEF7EcTqi32/7baCho BGKeQWQ4Lx52MH6zQa/YA3QGsQmIfqaXXSVwtWurn6zrQf/8h5y5zEVp7SeR2N9TR28K JMxxzLdHzLWh8FzI70Pem/VY3Rvr77czrNgIxaZqJSdjpeG3Tb+haPj/uMww/HFUGqF0 PUWUKareFQobI7UopuT9HfkMCjL9568A3yqgGO7p4ELF6yobt8Aq8YX5vWCFo2FPgoNE oEiU2VY+ejhU94AGcpwcMfVMkIr1dKE6wrW62g98/8/HbX3vRrvg7PAlDQKOAp0sPu2Y Gm/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GwaVvywA; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 3766565cf258..fa449273ae2b 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-ep + oneOf: + - description: PCIe EP controller in J7200 + items: + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in J721E + items: + - const: ti,j721e-pcie-ep reg: maxItems: 4 From patchwork Thu Dec 10 12:49:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 341037 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5499367jai; Thu, 10 Dec 2020 04:53:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJx4GpXApdzRnRDQAtfliBCg0CzmeqVqnVqGBthluBxHH7W6IPp3upfgZRPV2Kq0jksf0UE4 X-Received: by 2002:a17:906:b793:: with SMTP id dt19mr6292545ejb.120.1607604792313; Thu, 10 Dec 2020 04:53:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607604792; cv=none; d=google.com; s=arc-20160816; b=YvJUk+K2SkoPLBTRH5QHn2jObJ6MkavF2XfGoXmXWKoj1kBhI8rUMpC5r6CbJyDV6o puowbj93Ngp8ONbPnHEX7HELo66GtKNKszYySYgaTvN9KfQd2KRlT7sReR0ToYaMQUpQ UhdlSsK+CaKmqmLRJCHIYnRGb0cMph/mgwOhaE23twXW9Lj+kCGSSjM7OJ6XlUza3/y/ IN6ie8H0bKvO1HZGwnyINpJhXWTiXjO5PxR+zpEuwwvM1ecbSEdnabJ4G0+J1+zYU7P4 zvEkmAhzUVRw0x/DIqoMu8drbjEUgZJea971UR7a1812kT/ILbfyB8CVMvJJBqPn2hN0 aaWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=dAYh1u4G3eyAbCk5zFRGbIp8xQDnvfPh2urszVIB35o=; b=FJ49kxtOrgiij+sncPHf6MAd+B4vxYJGAIR8gd1CSzUPvK6e2R1KJtjK2R4Vc5RBJP r0vOzTyaneYrx5jbkvndWPsVWDUckJ/JaivUVUNMmmu67pNZ1Wm+ppFuSDJpVs4EnSiz Oz/cRYQqGieLInek2EjGNjxJbsEd2k4CiEc5ohFwjLsab79y7784XY8wyzmXtl3x6L0+ ACEESSEVNWeRfwzyOYSjp5FNHA17V6ZHmzIjiU8hO1g3XOQWg5Xr5BLH3ImemPPf4WVl nlSZloXj3KvkVaIOOyX7TBpAme4ApuCCHYKCB1qh8FhYkWy6CILiq8Dz3DNihZ4vUXTE Ylsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o7JWsraT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e26si3088150edr.162.2020.12.10.04.53.12; Thu, 10 Dec 2020 04:53:12 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=o7JWsraT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387661AbgLJMvc (ORCPT + 6 others); Thu, 10 Dec 2020 07:51:32 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36416 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387545AbgLJMv0 (ORCPT ); Thu, 10 Dec 2020 07:51:26 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BACnfnH054539; Thu, 10 Dec 2020 06:49:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1607604581; bh=dAYh1u4G3eyAbCk5zFRGbIp8xQDnvfPh2urszVIB35o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o7JWsraTaI9sSIJiBSPb1RPltUu0IyLYhoT8LiFpI+dEO1tpyM5FVb3/v4N+mCoTs eeBzGJlv9Jm8XvLVVUd5dlcLBRms7X8RoxsPBGeY1TFKm6Lc7K4FAt6EeBBBmNtzUU nAhFvEn20hruV/+/i0YfIVTwlQj5rsvd8Fv3SuSI= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BACnfOj092597 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Dec 2020 06:49:41 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 10 Dec 2020 06:49:41 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 10 Dec 2020 06:49:41 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BACnKJP112244; Thu, 10 Dec 2020 06:49:38 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Tom Joseph , Lorenzo Pieralisi CC: , , , , Subject: [RESEND PATCH 4/4] PCI: j721e: Get offset within "syscon" from "ti, syscon-pcie-ctrl" phandle arg Date: Thu, 10 Dec 2020 18:19:17 +0530 Message-ID: <20201210124917.24185-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201210124917.24185-1-kishon@ti.com> References: <20201210124917.24185-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl" phandle. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl" phandle. If the offset is not provided in "ti,syscon-pcie-ctrl", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- drivers/pci/controller/cadence/pci-j721e.c | 28 +++++++++++++++------- 1 file changed, 19 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 586b9d69fa5e..dac1ac8a7615 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -153,7 +154,8 @@ static const struct cdns_pcie_ops j721e_pcie_ops = { .link_up = j721e_pcie_link_up, }; -static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, + unsigned int offset) { struct device *dev = pcie->dev; u32 mask = J721E_MODE_RC; @@ -164,7 +166,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) if (mode == PCI_MODE_RC) val = J721E_MODE_RC; - ret = regmap_update_bits(syscon, 0, mask, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set pcie mode\n"); @@ -172,7 +174,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) } static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, - struct regmap *syscon) + struct regmap *syscon, unsigned int offset) { struct device *dev = pcie->dev; struct device_node *np = dev->of_node; @@ -185,7 +187,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, link_speed = 2; val = link_speed - 1; - ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) dev_err(dev, "failed to set link speed\n"); @@ -193,7 +195,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, } static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, - struct regmap *syscon) + struct regmap *syscon, unsigned int offset) { struct device *dev = pcie->dev; u32 lanes = pcie->num_lanes; @@ -201,7 +203,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, int ret; val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -212,6 +214,8 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) { struct device *dev = pcie->dev; struct device_node *node = dev->of_node; + struct of_phandle_args args; + unsigned int offset = 0; struct regmap *syscon; int ret; @@ -221,19 +225,25 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) return PTR_ERR(syscon); } - ret = j721e_pcie_set_mode(pcie, syscon); + /* Do not error out to maintain old DT compatibility */ + ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, + 0, &args); + if (!ret) + offset = args.args[0]; + + ret = j721e_pcie_set_mode(pcie, syscon, offset); if (ret < 0) { dev_err(dev, "Failed to set pci mode\n"); return ret; } - ret = j721e_pcie_set_link_speed(pcie, syscon); + ret = j721e_pcie_set_link_speed(pcie, syscon, offset); if (ret < 0) { dev_err(dev, "Failed to set link speed\n"); return ret; } - ret = j721e_pcie_set_lane_count(pcie, syscon); + ret = j721e_pcie_set_lane_count(pcie, syscon, offset); if (ret < 0) { dev_err(dev, "Failed to set num-lanes\n"); return ret;