From patchwork Wed Mar 22 20:07:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95837 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp414453qgd; Wed, 22 Mar 2017 13:15:17 -0700 (PDT) X-Received: by 10.84.217.140 with SMTP id p12mr58081862pli.164.1490213717712; Wed, 22 Mar 2017 13:15:17 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b62si2129692pfd.138.2017.03.22.13.15.16; Wed, 22 Mar 2017 13:15:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751611AbdCVUMf (ORCPT + 11 others); Wed, 22 Mar 2017 16:12:35 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25201 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751453AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK895r029452; Thu, 23 Mar 2017 05:08:21 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK895r029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213302; bh=AgQh8cQ7AIUaLNdb66J9JNb3uPC28UDXxgRvfI70kZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jTmMyOZyRUsuwWlhKM2dIOKV8roXax7BvGzA0l5fQH4T2cvHNiAx4Yx3qNer1tV7t l/kktwxOnDsq6LZCJib9vgeEv/dKqslAJAmhSO4usdy02Xe+n57xm1D2EMK1I1nS5b HWMvyyqgk6IoiFeIUtQd1Vkg5WBO844OZbJiwDwDmWgxtqPKhYGHlwPiDe/eZpkEYO ilX7IaJTGvuo5b5ftQiEsE6Vh+WMBfVsW8LF8Me34y8hxGzxuLluURhqurV22FJrc5 T3n7LxaXaJWkjp+vp+iUt3f2KdqRrH/HkqZvfMpDq7xqgMr+Qo5Du1HQ1kbs2bhBSy HGnDwtF5rrMYw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 03/53] mtd: nand: denali: remove unused CONFIG option and macros Date: Thu, 23 Mar 2017 05:07:02 +0900 Message-Id: <1490213273-8571-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All of these macros are not used at all. CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR is not used for anything but defining SCRATCH_REG_ADDR. The config option should go away as well. I am removing some register macros. They are not used, and do not exist in recent IP versions. Signed-off-by: Masahiro Yamada --- Changes in v2: - Remove more unused macros drivers/mtd/nand/Kconfig | 11 ------ drivers/mtd/nand/denali.c | 5 --- drivers/mtd/nand/denali.h | 99 ----------------------------------------------- 3 files changed, 115 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 6d4d567..817558b 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -60,17 +60,6 @@ config MTD_NAND_DENALI_DT Enable the driver for NAND flash on platforms using a Denali NAND controller as a DT device. -config MTD_NAND_DENALI_SCRATCH_REG_ADDR - hex "Denali NAND size scratch register address" - default "0xFF108018" - depends on MTD_NAND_DENALI_PCI - help - Some platforms place the NAND chip size in a scratch register - because (some versions of) the driver aren't able to automatically - determine the size of certain chips. Set the address of the - scratch register here to enable this feature. On Intel Moorestown - boards, the scratch register is at 0xFF108018. - config MTD_NAND_GPIO tristate "GPIO assisted NAND Flash driver" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 73b9d4e..f993e13 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -91,11 +91,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) #define DENALI_READ 0 #define DENALI_WRITE 0x100 -/* types of device accesses. We can issue commands and get status */ -#define COMMAND_CYCLE 0 -#define ADDR_CYCLE 1 -#define STATUS_CYCLE 2 - /* * this is a helper macro that allows us to * format the bank into the proper bits for the controller diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index ea22191..c4f3a68 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -257,26 +257,6 @@ #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) #define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) -#define DATA_INTR 0x550 -#define DATA_INTR__WRITE_SPACE_AV 0x0001 -#define DATA_INTR__READ_DATA_AV 0x0002 - -#define DATA_INTR_EN 0x560 -#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 -#define DATA_INTR_EN__READ_DATA_AV 0x0002 - -#define GPREG_0 0x570 -#define GPREG_0__VALUE 0xffff - -#define GPREG_1 0x580 -#define GPREG_1__VALUE 0xffff - -#define GPREG_2 0x590 -#define GPREG_2__VALUE 0xffff - -#define GPREG_3 0x5a0 -#define GPREG_3__VALUE 0xffff - #define ECC_THRESHOLD 0x600 #define ECC_THRESHOLD__VALUE 0x03ff @@ -331,69 +311,15 @@ #define CHNL_ACTIVE__CHANNEL2 0x0004 #define CHNL_ACTIVE__CHANNEL3 0x0008 -#define ACTIVE_SRC_ID 0x800 -#define ACTIVE_SRC_ID__VALUE 0x00ff - -#define PTN_INTR 0x810 -#define PTN_INTR__CONFIG_ERROR 0x0001 -#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 -#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 -#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 -#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 -#define PTN_INTR__REG_ACCESS_ERROR 0x0020 - -#define PTN_INTR_EN 0x820 -#define PTN_INTR_EN__CONFIG_ERROR 0x0001 -#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 -#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 -#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 -#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 -#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 - -#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) -#define PERM_SRC_ID__SRCID 0x00ff -#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 -#define PERM_SRC_ID__WRITE_ACTIVE 0x2000 -#define PERM_SRC_ID__READ_ACTIVE 0x4000 -#define PERM_SRC_ID__PARTITION_VALID 0x8000 - -#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) -#define MIN_BLK_ADDR__VALUE 0xffff - -#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) -#define MAX_BLK_ADDR__VALUE 0xffff - -#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) -#define MIN_MAX_BANK__MIN_VALUE 0x0003 -#define MIN_MAX_BANK__MAX_VALUE 0x000c - - -/* ffsdefs.h */ -#define CLEAR 0 /*use this to clear a field instead of "fail"*/ -#define SET 1 /*use this to set a field instead of "pass"*/ #define FAIL 1 /*failed flag*/ #define PASS 0 /*success flag*/ -#define ERR -1 /*error flag*/ - -/* lld.h */ -#define GOOD_BLOCK 0 -#define DEFECTIVE_BLOCK 1 -#define READ_ERROR 2 #define CLK_X 5 #define CLK_MULTI 4 -/* KBV - Updated to LNW scratch register address */ -#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR -#define SCRATCH_REG_SIZE 64 - -#define GLOB_HWCTL_DEFAULT_BLKS 2048 - #define SUPPORT_15BITECC 1 #define SUPPORT_8BITECC 1 -#define CUSTOM_CONF_PARAMS 0 - #define ONFI_BLOOM_TIME 1 #define MODE5_WORKAROUND 0 @@ -403,31 +329,6 @@ #define MODE_10 0x08000000 #define MODE_11 0x0C000000 - -#define DATA_TRANSFER_MODE 0 -#define PROTECTION_PER_BLOCK 1 -#define LOAD_WAIT_COUNT 2 -#define PROGRAM_WAIT_COUNT 3 -#define ERASE_WAIT_COUNT 4 -#define INT_MONITOR_CYCLE_COUNT 5 -#define READ_BUSY_PIN_ENABLED 6 -#define MULTIPLANE_OPERATION_SUPPORT 7 -#define PRE_FETCH_MODE 8 -#define CE_DONT_CARE_SUPPORT 9 -#define COPYBACK_SUPPORT 10 -#define CACHE_WRITE_SUPPORT 11 -#define CACHE_READ_SUPPORT 12 -#define NUM_PAGES_IN_BLOCK 13 -#define ECC_ENABLE_SELECT 14 -#define WRITE_ENABLE_2_READ_ENABLE 15 -#define ADDRESS_2_DATA 16 -#define READ_ENABLE_2_WRITE_ENABLE 17 -#define TWO_ROW_ADDRESS_CYCLES 18 -#define MULTIPLANE_ADDRESS_RESTRICT 19 -#define ACC_CLOCKS 20 -#define READ_WRITE_ENABLE_LOW_COUNT 21 -#define READ_WRITE_ENABLE_HIGH_COUNT 22 - #define ECC_SECTOR_SIZE 512 struct nand_buf { From patchwork Wed Mar 22 20:07:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95831 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413683qgd; Wed, 22 Mar 2017 13:13:18 -0700 (PDT) X-Received: by 10.84.173.228 with SMTP id p91mr57174779plb.121.1490213598439; Wed, 22 Mar 2017 13:13:18 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k80si2116963pfk.272.2017.03.22.13.13.18; Wed, 22 Mar 2017 13:13:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751862AbdCVUNQ (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:16 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:24988 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751444AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK895t029452; Thu, 23 Mar 2017 05:08:24 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK895t029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213305; bh=M22zm3PWk0stckUN7PtyKOfWrIezQpbscJWx9KlHXuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2cISonORwbyzMQBDYn9xTiLlHRuDWBqu3PrvRUZ2TXt129gyOMNJERlNT5f9RqCZU K+W+CJuri+9f+CPIOUyoEi+qSdpgdd1/sGbGggG9IG0sQ8ziYzpzEo2U7+pLiC9P69 TUD1QZxfCK1y/er7OS7jrpa1hzJGJQeXaXegW3KSODXGVMJ42UHOd/QvBEudsedsb7 BzA09wJiyypOXBE+l7NdBVaSc9aYU85fF/RCnIYIAQ+1xg9hd88aVXAE5mLDcGD3DV hG3GKrtSBSaik9ADRLuud0NaMM2tE3TuBl/TPZQ3l3CuBlfRUSt4zLCQf+On1Fxm98 mLWNGg3TxuGFA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 05/53] mtd: nand: denali: remove more unused struct members Date: Thu, 23 Mar 2017 05:07:04 +0900 Message-Id: <1490213273-8571-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These members are not used at all. Signed-off-by: Masahiro Yamada --- Changes in v2: - Add git description drivers/mtd/nand/denali.h | 2 -- 1 file changed, 2 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index c4f3a68..6573ea5 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -350,7 +350,6 @@ struct denali_nand_info { struct nand_buf buf; struct device *dev; int total_used_banks; - uint32_t block; /* stored for future use */ uint16_t page; void __iomem *flash_reg; /* Mapped io reg base address */ void __iomem *flash_mem; /* Mapped io reg base address */ @@ -359,7 +358,6 @@ struct denali_nand_info { struct completion complete; spinlock_t irq_lock; uint32_t irq_status; - int irq_debug_array[32]; int irq; uint32_t devnum; /* represent how many nands connected */ From patchwork Wed Mar 22 20:07:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95829 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413577qgd; Wed, 22 Mar 2017 13:13:03 -0700 (PDT) X-Received: by 10.98.59.8 with SMTP id i8mr48400884pfa.132.1490213583452; Wed, 22 Mar 2017 13:13:03 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e7si2997211pln.78.2017.03.22.13.13.03; Wed, 22 Mar 2017 13:13:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751800AbdCVUMz (ORCPT + 11 others); Wed, 22 Mar 2017 16:12:55 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25131 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751450AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK895u029452; Thu, 23 Mar 2017 05:08:25 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK895u029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213306; bh=sYMvXOoGOJZ8hbnok9r9LRTppg6Zo/oq3jVDyyalZI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eSXxXRax0QHbWl177j3qEdG+vgoaw5qBdHn3fNLOnkDjG3cbVQX+L7h4cYA/nRyrO 1P+4T2QswnAW3U9T+f5NZPI9vhI98h8ylUfd87vIqtNdQmXx49NNAqRMTAAczr+L/V WbPbX4ZUbS8XgxW7HNtcBWVs9IXoq4m60lRwZ18FFfngclUFjWLqvLCBxNGgJ0TOSY Px18e5PPsMXRKBNtPNYzgXbU5y4nbsFFxGq910b0Q9ia4LSlw9tKIQF4XFTS67xloV 9zYDh9nYymShd77wvQHEKHKFQLpDpUD3MWvcw39eCRhjNMpy+22S9MiD4NwFXj1m1N LOaaFJz9vwQMA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 06/53] mtd: nand: denali: fix comment of denali_nand_info::flash_mem Date: Thu, 23 Mar 2017 05:07:05 +0900 Message-Id: <1490213273-8571-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The same comment "Mapped io reg base address" for flash_reg and flash_mem probably due to the mistake of copy-paste work. Of course, the latter is not the register base address. Reword the comments using the terminology in the Denali User's Guide. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 6573ea5..403a7c8 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -351,8 +351,8 @@ struct denali_nand_info { struct device *dev; int total_used_banks; uint16_t page; - void __iomem *flash_reg; /* Mapped io reg base address */ - void __iomem *flash_mem; /* Mapped io reg base address */ + void __iomem *flash_reg; /* Register Interface */ + void __iomem *flash_mem; /* Host Data/Command Interface */ /* elements used by ISR */ struct completion complete; From patchwork Wed Mar 22 20:07:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95834 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413906qgd; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) X-Received: by 10.84.241.203 with SMTP id t11mr58209781plm.48.1490213635855; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2964310pgc.350.2017.03.22.13.13.55; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751979AbdCVUNg (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:36 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25071 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751448AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK895v029452; Thu, 23 Mar 2017 05:08:26 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK895v029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213307; bh=yDhaih8HScIkQBmryb+HebglCf4qFlW3Sd8/pEb9UCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bDw+WtMtsa5bGtXzl5kOsCJl5DeVe17tFnR1pdv2Yjjr2ntXWDYfLYy0nCre/NW2I xkm6gNFk+eH3/saYwsLszHMacD4OzsKDB3iRGb2vTqkZcOdzB52NKXctNero/9j+gI y++wq91GenZxzVO9VvYxl2KRQYhLm9oM6iA5jhOwA1GXbxkCM3f4JRibLHKZ38ZZP8 aEI7U1PH327Ozup1i9V29es08jOiV4+WDYhirjZeeeYPHvf5f2hYNy8GwxUcaK3fyG Oj8apTY81mhefAMNTKgyrB2C2T4nh9J/n937M8v4tRh+6T9Vg3Ov69BaNqqLzPWmtf I/26oo4Fu3JZQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 07/53] mtd: nand: denali: consolidate INTR_STATUS__* and INTR_EN__* macros Date: Thu, 23 Mar 2017 05:07:06 +0900 Message-Id: <1490213273-8571-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The interrupts are enabled by INTR_EN register, then asserted interrupts can be observed via INTR_STATUS register. The bit fields are identical between INTR_EN and INTR_STATUS, so we can merge the bit field macros. Likewise for DATA_INTR. Signed-off-by: Masahiro Yamada --- Changes in v2: - Newly added drivers/mtd/nand/denali.c | 56 ++++++++++++++++++++----------------------- drivers/mtd/nand/denali.h | 61 ++++++++++++++--------------------------------- 2 files changed, 44 insertions(+), 73 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index c9806e6..2c59eb3 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -45,16 +45,16 @@ MODULE_PARM_DESC(onfi_timing_mode, * We define a macro here that combines all interrupts this driver uses into * a single constant value, for convenience. */ -#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ - INTR_STATUS__ECC_TRANSACTION_DONE | \ - INTR_STATUS__ECC_ERR | \ - INTR_STATUS__PROGRAM_FAIL | \ - INTR_STATUS__LOAD_COMP | \ - INTR_STATUS__PROGRAM_COMP | \ - INTR_STATUS__TIME_OUT | \ - INTR_STATUS__ERASE_FAIL | \ - INTR_STATUS__RST_COMP | \ - INTR_STATUS__ERASE_COMP) +#define DENALI_IRQ_ALL (INTR__DMA_CMD_COMP | \ + INTR__ECC_TRANSACTION_DONE | \ + INTR__ECC_ERR | \ + INTR__PROGRAM_FAIL | \ + INTR__LOAD_COMP | \ + INTR__PROGRAM_COMP | \ + INTR__TIME_OUT | \ + INTR__ERASE_FAIL | \ + INTR__RST_COMP | \ + INTR__ERASE_COMP) /* * indicates whether or not the internal value for the flash bank is @@ -159,7 +159,7 @@ static void read_status(struct denali_nand_info *denali) static void reset_bank(struct denali_nand_info *denali) { uint32_t irq_status; - uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; + uint32_t irq_mask = INTR__RST_COMP | INTR__TIME_OUT; clear_interrupts(denali); @@ -167,7 +167,7 @@ static void reset_bank(struct denali_nand_info *denali) irq_status = wait_for_irq(denali, irq_mask); - if (irq_status & INTR_STATUS__TIME_OUT) + if (irq_status & INTR__TIME_OUT) dev_err(denali->dev, "reset bank failed.\n"); } @@ -177,22 +177,22 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) int i; for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + iowrite32(INTR__RST_COMP | INTR__TIME_OUT, denali->flash_reg + INTR_STATUS(i)); for (i = 0; i < denali->max_banks; i++) { iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & - (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) + (INTR__RST_COMP | INTR__TIME_OUT))) cpu_relax(); if (ioread32(denali->flash_reg + INTR_STATUS(i)) & - INTR_STATUS__TIME_OUT) + INTR__TIME_OUT) dev_dbg(denali->dev, "NAND Reset operation timed out on bank %d\n", i); } for (i = 0; i < denali->max_banks; i++) - iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, + iowrite32(INTR__RST_COMP | INTR__TIME_OUT, denali->flash_reg + INTR_STATUS(i)); return PASS; @@ -716,7 +716,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, uint32_t addr, cmd, irq_status, irq_mask; if (op == DENALI_READ) - irq_mask = INTR_STATUS__LOAD_COMP; + irq_mask = INTR__LOAD_COMP; else if (op == DENALI_WRITE) irq_mask = 0; else @@ -823,8 +823,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t irq_status; - uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | - INTR_STATUS__PROGRAM_FAIL; + uint32_t irq_mask = INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL; int status = 0; denali->page = page; @@ -851,7 +850,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); - uint32_t irq_mask = INTR_STATUS__LOAD_COMP; + uint32_t irq_mask = INTR__LOAD_COMP; uint32_t irq_status, addr, cmd; denali->page = page; @@ -912,7 +911,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, bool check_erased_page = false; unsigned int bitflips = 0; - if (irq_status & INTR_STATUS__ECC_ERR) { + if (irq_status & INTR__ECC_ERR) { /* read the ECC errors. we'll ignore them for now */ uint32_t err_address, err_correction_info, err_byte, err_sector, err_device, err_correction_value; @@ -969,7 +968,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, * for a while for this interrupt */ while (!(read_interrupt_status(denali) & - INTR_STATUS__ECC_TRANSACTION_DONE)) + INTR__ECC_TRANSACTION_DONE)) cpu_relax(); clear_interrupts(denali); denali_set_intr_modes(denali, true); @@ -1020,8 +1019,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, dma_addr_t addr = denali->buf.dma_buf; size_t size = mtd->writesize + mtd->oobsize; uint32_t irq_status; - uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | - INTR_STATUS__PROGRAM_FAIL; + uint32_t irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; /* * if it is a raw xfer, we want to disable ecc and send the spare area. @@ -1119,8 +1117,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, size_t size = mtd->writesize + mtd->oobsize; uint32_t irq_status; - uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | - INTR_STATUS__ECC_ERR; + uint32_t irq_mask = INTR__ECC_TRANSACTION_DONE | INTR__ECC_ERR; bool check_erased_page = false; if (page != denali->page) { @@ -1168,7 +1165,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, struct denali_nand_info *denali = mtd_to_denali(mtd); dma_addr_t addr = denali->buf.dma_buf; size_t size = mtd->writesize + mtd->oobsize; - uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; + uint32_t irq_mask = INTR__DMA_CMD_COMP; if (page != denali->page) { dev_err(denali->dev, @@ -1241,10 +1238,9 @@ static int denali_erase(struct mtd_info *mtd, int page) index_addr(denali, cmd, 0x1); /* wait for erase to complete or failure to occur */ - irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | - INTR_STATUS__ERASE_FAIL); + irq_status = wait_for_irq(denali, INTR__ERASE_COMP | INTR__ERASE_FAIL); - return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; + return irq_status & INTR__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; } static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 403a7c8..8df2285 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -218,40 +218,22 @@ #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) - -#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 -#define INTR_STATUS__ECC_ERR 0x0002 -#define INTR_STATUS__DMA_CMD_COMP 0x0004 -#define INTR_STATUS__TIME_OUT 0x0008 -#define INTR_STATUS__PROGRAM_FAIL 0x0010 -#define INTR_STATUS__ERASE_FAIL 0x0020 -#define INTR_STATUS__LOAD_COMP 0x0040 -#define INTR_STATUS__PROGRAM_COMP 0x0080 -#define INTR_STATUS__ERASE_COMP 0x0100 -#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 -#define INTR_STATUS__LOCKED_BLK 0x0400 -#define INTR_STATUS__UNSUP_CMD 0x0800 -#define INTR_STATUS__INT_ACT 0x1000 -#define INTR_STATUS__RST_COMP 0x2000 -#define INTR_STATUS__PIPE_CMD_ERR 0x4000 -#define INTR_STATUS__PAGE_XFER_INC 0x8000 - -#define INTR_EN__ECC_TRANSACTION_DONE 0x0001 -#define INTR_EN__ECC_ERR 0x0002 -#define INTR_EN__DMA_CMD_COMP 0x0004 -#define INTR_EN__TIME_OUT 0x0008 -#define INTR_EN__PROGRAM_FAIL 0x0010 -#define INTR_EN__ERASE_FAIL 0x0020 -#define INTR_EN__LOAD_COMP 0x0040 -#define INTR_EN__PROGRAM_COMP 0x0080 -#define INTR_EN__ERASE_COMP 0x0100 -#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 -#define INTR_EN__LOCKED_BLK 0x0400 -#define INTR_EN__UNSUP_CMD 0x0800 -#define INTR_EN__INT_ACT 0x1000 -#define INTR_EN__RST_COMP 0x2000 -#define INTR_EN__PIPE_CMD_ERR 0x4000 -#define INTR_EN__PAGE_XFER_INC 0x8000 +#define INTR__ECC_TRANSACTION_DONE 0x0001 +#define INTR__ECC_ERR 0x0002 +#define INTR__DMA_CMD_COMP 0x0004 +#define INTR__TIME_OUT 0x0008 +#define INTR__PROGRAM_FAIL 0x0010 +#define INTR__ERASE_FAIL 0x0020 +#define INTR__LOAD_COMP 0x0040 +#define INTR__PROGRAM_COMP 0x0080 +#define INTR__ERASE_COMP 0x0100 +#define INTR__PIPE_CPYBCK_CMD_COMP 0x0200 +#define INTR__LOCKED_BLK 0x0400 +#define INTR__UNSUP_CMD 0x0800 +#define INTR__INT_ACT 0x1000 +#define INTR__RST_COMP 0x2000 +#define INTR__PIPE_CMD_ERR 0x4000 +#define INTR__PAGE_XFER_INC 0x8000 #define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) @@ -284,20 +266,13 @@ #define IGNORE_ECC_DONE__FLAG 0x0001 #define DMA_INTR 0x720 +#define DMA_INTR_EN 0x730 #define DMA_INTR__TARGET_ERROR 0x0001 #define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 #define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 #define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 #define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 -#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 - -#define DMA_INTR_EN 0x730 -#define DMA_INTR_EN__TARGET_ERROR 0x0001 -#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 -#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 -#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 -#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 -#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 +#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 #define TARGET_ERR_ADDR_LO 0x740 #define TARGET_ERR_ADDR_LO__VALUE 0xffff From patchwork Wed Mar 22 20:07:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95841 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415116qgd; Wed, 22 Mar 2017 13:17:04 -0700 (PDT) X-Received: by 10.98.22.87 with SMTP id 84mr49811769pfw.145.1490213824247; Wed, 22 Mar 2017 13:17:04 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s5si3000811plj.108.2017.03.22.13.17.03; Wed, 22 Mar 2017 13:17:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752581AbdCVUQz (ORCPT + 11 others); Wed, 22 Mar 2017 16:16:55 -0400 Received: from condef-03.nifty.com ([202.248.20.68]:41740 "EHLO condef-03.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751775AbdCVUQV (ORCPT ); Wed, 22 Mar 2017 16:16:21 -0400 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-03.nifty.com with ESMTP id v2MKBpDJ011617 for ; Thu, 23 Mar 2017 05:11:51 +0900 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8960029452; Thu, 23 Mar 2017 05:08:30 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8960029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213311; bh=4fY1lO0n4sY5X3gRy4Dunpb62ZCGHW++MXJt5PFaI3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c60aobA8As3LW93EUT8ozklx2Mc8ChvEWsRbrYjd22PCGarPGJnch58RbKB/DfBAZ /8xTV28HKC4S1ESCbzsaD8d0gwXrPKHG0r3b+vxFd7WO3bvyNwgNEcZhK6HHE26u52 ULcc80nRR9zrPzYqr5iEdFEW+hA1ndKBJK65A9CVpTG1lPvTTsUaH+liGD1l1dxvCE WFshW2kJ7Pn2snDUEZrg4nrPKcatkHCzXn1Rh7ZOaWQN80E0V2doOmB2EblwqV9jaE 0WZejXxZrOJ56P8IkWT/AwlgukDkXdvA57sV6Xovwh+0+ZUpYyr5KCYd5xo8eMUUb1 viDLtauyjfRTQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 10/53] mtd: nand: denali: fix erased page checking Date: Thu, 23 Mar 2017 05:07:09 +0900 Message-Id: <1490213273-8571-11-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This part is wrong in multiple ways: [1] is_erased() is called against "buf" twice, so the second one is meaningless. The second call should check chip->oob_poi. [2] This code block is nested by double "if (check_erase_page)". The inner one is redundant. [3] Erased page checking without threshold is false-positive. Basically, there are two ways for erased page checking: - read the whole of page + oob in raw transfer, then check if all the data are 0xFF. - read the ECC-corrected page + oob, then check if *almost* all the data are 0xFF (bit-flips less than ecc.strength are allowed) While here, it checks if all data in ECC-corrected page are 0xFF. This is too strong because not all of the data are 0xFF after they are manipulated by the ECC engine. Proper threshold must be taken into account to avoid false-positive ecc_stats.failed increments. [4] positive return value for uncorrectable bitflips The comment of ecc->read_page() says it should return "0 if bitflips uncorrectable", but the current code could return a positive value in the case. This commit solves the problems above. The nand framework provides a helper nand_check_erased_ecc_chunk() for erased page check with threshold. The driver's own helper is unneeded. Signed-off-by: Masahiro Yamada --- Changes in v2: - Squash some patches into one. - Use nand_check_erased_ecc_chunk() with threshold drivers/mtd/nand/denali.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 2c59eb3..86381ac 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -883,19 +883,6 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) } } -/* - * this function examines buffers to see if they contain data that - * indicate that the buffer is part of an erased region of flash. - */ -static bool is_erased(uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (buf[i] != 0xFF) - return false; - return true; -} #define ECC_SECTOR_SIZE 512 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) @@ -1119,6 +1106,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t irq_status; uint32_t irq_mask = INTR__ECC_TRANSACTION_DONE | INTR__ECC_ERR; bool check_erased_page = false; + int stat; if (page != denali->page) { dev_err(denali->dev, @@ -1148,12 +1136,15 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, if (check_erased_page) { read_oob_data(mtd, chip->oob_poi, denali->page); - /* check ECC failures that may have occurred on erased pages */ - if (check_erased_page) { - if (!is_erased(buf, mtd->writesize)) - mtd->ecc_stats.failed++; - if (!is_erased(buf, mtd->oobsize)) - mtd->ecc_stats.failed++; + stat = nand_check_erased_ecc_chunk( + buf, mtd->writesize, + chip->oob_poi, mtd->oobsize, + NULL, 0, + chip->ecc.strength * chip->ecc.steps); + if (stat < 0) { + mtd->ecc_stats.failed++; + /* return 0 for uncorrectable bitflips */ + max_bitflips = 0; } } return max_bitflips; From patchwork Wed Mar 22 20:07:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95840 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415108qgd; Wed, 22 Mar 2017 13:17:03 -0700 (PDT) X-Received: by 10.84.208.102 with SMTP id f35mr58460636plh.19.1490213823527; Wed, 22 Mar 2017 13:17:03 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s5si3000811plj.108.2017.03.22.13.17.03; Wed, 22 Mar 2017 13:17:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752673AbdCVUQ6 (ORCPT + 11 others); Wed, 22 Mar 2017 16:16:58 -0400 Received: from condef-06.nifty.com ([202.248.20.71]:40732 "EHLO condef-06.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdCVUPz (ORCPT ); Wed, 22 Mar 2017 16:15:55 -0400 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-06.nifty.com with ESMTP id v2MKBpWd013405 for ; Thu, 23 Mar 2017 05:11:51 +0900 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8961029452; Thu, 23 Mar 2017 05:08:31 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8961029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213312; bh=qYbsLp7Yfe0wPu41bq2nDxLiTJkmpwAeFevL0dSGe0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lGE0TiZjY4HeNb7AmiYAZ8KlaJi01cmvGsqdWtERzEGrCcNBhNuyCQySAxSXkbkaQ rcMJvxd44YEak+4QvfevEqLswc7tmQW9DHxJK4vMzl09+aCrimohgnEa9gBFsJn6s3 CQ0o1cFDMMy1NYJtbiwbP+KRLgY4J+9dPsZQX5K5bFarwaZKJoVmud0Udo2fx4Pou3 V31HYAAIBD44wSATIKiBTo2OY7JJ5VMp23YwuKSH8BrGCdFPJzri82IG6jfg+9jNk+ JCrG//l1WIU6/FCvSjyC+rhcTkD4lYvovZwbRy7YvpjYQmsN/x9epB97RMkf5BAo3l i8EPnN9QN8Xdw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 11/53] mtd: nand: denali: fix bitflips calculation in handle_ecc() Date: Thu, 23 Mar 2017 05:07:10 +0900 Message-Id: <1490213273-8571-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This function is wrong in multiple ways: [1] Counting corrected bytes instead of corrected bits. The following code is counting the number of corrected _bytes_. /* correct the ECC error */ buf[offset] ^= err_cor_value; mtd->ecc_stats.corrected++; bitflips++; What the core framework expects is the number of corrected _bits_. They can be different if multiple bitflips occur within one byte. [2] total number of errors instead of max of per-sector errors The core framework expects that corrected errors are counted per sector, then the max value should be taken. The current code simply iterates over the whole page, i.e. counts the total number of correction in the page. This means "too many bitflips" is triggered earlier than it should be, i.e. the NAND device is worn out sooner. Besides those bugs, this function is unreadable due to the deep nesting. Notice the whole code in this function is wrapped in if (irq_status & INTR__ECC_ERR), so this conditional can be moved out of the function. Also, use shorter names for local variables. Re-work the function to fix all the issues. Signed-off-by: Masahiro Yamada --- Changes in v2: - Use shorter names for local variables. - Fix bugs addressed by [1], [2] drivers/mtd/nand/denali.c | 157 ++++++++++++++++++++++++---------------------- 1 file changed, 82 insertions(+), 75 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 86381ac..608fe6f 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -888,80 +888,87 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) -#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) +#define ECC_ERROR_UNCORRECTABLE(x) ((x) & ERR_CORRECTION_INFO__ERROR_TYPE) #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) -static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, - uint32_t irq_status, unsigned int *max_bitflips) +static int handle_ecc(struct mtd_info *mtd, + struct denali_nand_info *denali, uint8_t *buf) { - bool check_erased_page = false; unsigned int bitflips = 0; + unsigned int max_bitflips = 0; + unsigned int total_bitflips = 0; + uint32_t err_addr, err_cor_info; + unsigned int err_byte, err_sector, err_device; + uint8_t err_cor_value; + unsigned int prev_sector = 0; + int ret = 0; + + /* read the ECC errors. we'll ignore them for now */ + denali_set_intr_modes(denali, false); - if (irq_status & INTR__ECC_ERR) { - /* read the ECC errors. we'll ignore them for now */ - uint32_t err_address, err_correction_info, err_byte, - err_sector, err_device, err_correction_value; - denali_set_intr_modes(denali, false); - - do { - err_address = ioread32(denali->flash_reg + - ECC_ERROR_ADDRESS); - err_sector = ECC_SECTOR(err_address); - err_byte = ECC_BYTE(err_address); - - err_correction_info = ioread32(denali->flash_reg + - ERR_CORRECTION_INFO); - err_correction_value = - ECC_CORRECTION_VALUE(err_correction_info); - err_device = ECC_ERR_DEVICE(err_correction_info); - - if (ECC_ERROR_CORRECTABLE(err_correction_info)) { - /* - * If err_byte is larger than ECC_SECTOR_SIZE, - * means error happened in OOB, so we ignore - * it. It's no need for us to correct it - * err_device is represented the NAND error - * bits are happened in if there are more - * than one NAND connected. - */ - if (err_byte < ECC_SECTOR_SIZE) { - struct mtd_info *mtd = - nand_to_mtd(&denali->nand); - int offset; - - offset = (err_sector * - ECC_SECTOR_SIZE + - err_byte) * - denali->devnum + - err_device; - /* correct the ECC error */ - buf[offset] ^= err_correction_value; - mtd->ecc_stats.corrected++; - bitflips++; - } - } else { - /* - * if the error is not correctable, need to - * look at the page to see if it is an erased - * page. if so, then it's not a real ECC error - */ - check_erased_page = true; - } - } while (!ECC_LAST_ERR(err_correction_info)); - /* - * Once handle all ecc errors, controller will triger - * a ECC_TRANSACTION_DONE interrupt, so here just wait - * for a while for this interrupt - */ - while (!(read_interrupt_status(denali) & - INTR__ECC_TRANSACTION_DONE)) - cpu_relax(); - clear_interrupts(denali); - denali_set_intr_modes(denali, true); - } - *max_bitflips = bitflips; - return check_erased_page; + do { + err_addr = ioread32(denali->flash_reg + ECC_ERROR_ADDRESS); + err_sector = ECC_SECTOR(err_addr); + err_byte = ECC_BYTE(err_addr); + + err_cor_info = ioread32(denali->flash_reg + ERR_CORRECTION_INFO); + err_cor_value = ECC_CORRECTION_VALUE(err_cor_info); + err_device = ECC_ERR_DEVICE(err_cor_info); + + /* reset the bitflip counter when crossing ECC sector */ + if (err_sector != prev_sector) + bitflips = 0; + + if (ECC_ERROR_UNCORRECTABLE(err_cor_info)) { + /* + * if the error is not correctable, need to look at the + * page to see if it is an erased page. if so, then + * it's not a real ECC error + */ + ret = -EBADMSG; + } else if (err_byte < ECC_SECTOR_SIZE) { + /* + * If err_byte is larger than ECC_SECTOR_SIZE, means error + * happened in OOB, so we ignore it. It's no need for + * us to correct it err_device is represented the NAND + * error bits are happened in if there are more than + * one NAND connected. + */ + int offset; + unsigned int flips_in_byte; + + offset = (err_sector * ECC_SECTOR_SIZE + err_byte) * + denali->devnum + err_device; + + /* correct the ECC error */ + flips_in_byte = hweight8(buf[offset] ^ err_cor_value); + bitflips += flips_in_byte; + total_bitflips += flips_in_byte; + buf[offset] ^= err_cor_value; + + max_bitflips = max(max_bitflips, bitflips); + } + + prev_sector = err_sector; + } while (!ECC_LAST_ERR(err_cor_info)); + + /* + * Once handle all ecc errors, controller will trigger a + * ECC_TRANSACTION_DONE interrupt, so here just wait for + * a while for this interrupt + */ + while (!(read_interrupt_status(denali) & INTR__ECC_TRANSACTION_DONE)) + cpu_relax(); + clear_interrupts(denali); + denali_set_intr_modes(denali, true); + + if (ret) + return ret; + + mtd->ecc_stats.corrected += total_bitflips; + + return max_bitflips; } /* programs the controller to either enable/disable DMA transfers */ @@ -1097,7 +1104,6 @@ static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - unsigned int max_bitflips; struct denali_nand_info *denali = mtd_to_denali(mtd); dma_addr_t addr = denali->buf.dma_buf; @@ -1105,8 +1111,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t irq_status; uint32_t irq_mask = INTR__ECC_TRANSACTION_DONE | INTR__ECC_ERR; - bool check_erased_page = false; - int stat; + int stat = 0; if (page != denali->page) { dev_err(denali->dev, @@ -1130,10 +1135,11 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, memcpy(buf, denali->buf.buf, mtd->writesize); - check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); + if (irq_status & INTR__ECC_ERR) + stat = handle_ecc(mtd, denali, buf); denali_enable_dma(denali, false); - if (check_erased_page) { + if (stat == -EBADMSG) { read_oob_data(mtd, chip->oob_poi, denali->page); stat = nand_check_erased_ecc_chunk( @@ -1144,10 +1150,11 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, if (stat < 0) { mtd->ecc_stats.failed++; /* return 0 for uncorrectable bitflips */ - max_bitflips = 0; + stat = 0; } } - return max_bitflips; + + return stat; } static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, From patchwork Wed Mar 22 20:07:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95839 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415104qgd; Wed, 22 Mar 2017 13:17:02 -0700 (PDT) X-Received: by 10.99.116.10 with SMTP id p10mr45799174pgc.74.1490213822864; Wed, 22 Mar 2017 13:17:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s5si3000811plj.108.2017.03.22.13.17.02; Wed, 22 Mar 2017 13:17:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752529AbdCVUPZ (ORCPT + 11 others); Wed, 22 Mar 2017 16:15:25 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:24794 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdCVUL6 (ORCPT ); Wed, 22 Mar 2017 16:11:58 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8962029452; Thu, 23 Mar 2017 05:08:33 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8962029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213314; bh=bIjoQT1mwHplizobDSyXhZ4bT5hlB/Yxmrw0Og+ZLJI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G9gSka15yHPm66q0CCkYNsw8y0MPTGI6qXh/v8hm6ki0VwRV32gXhhnnZ0mcQgmmC 6xPGAqmXKWFHO+MrI6d3vURxjz6EovmlLc2GjgG7ar4ONbGcMB/7J5njgQUCrgTqUW MtTyBSpHlbViM/0jYwwUAUQG4RRoy6pOinl5HGMsctcasuRKKBi9h2TGhiNUE0EuIZ Z7GNYLVF3ezI+wd96qWeC00bn2L9olTWjZfVU5AaVPnHvSsMks4TdeWTcpcqJHiB7P eu8ZQZEgTKRtTXVU4Ziv7H4NxJZgmCCBE7CfSPFg7SkamrWl5VsyXhxd3vsEb4mhjn Q3F2J5+HdMwEQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 12/53] mtd: nand: denali: support HW_ECC_FIXUP capability Date: Thu, 23 Mar 2017 05:07:11 +0900 Message-Id: <1490213273-8571-13-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some old versions of the Denali IP (perhaps used only for Intel?) detects ECC errors and provides correct data via a register, but does not touch the transferred data. So, the software must fixup the data in the buffer according to the provided ECC correction information. Newer versions perform ECC correction before transferring the data. No more software intervention is needed. The ECC_ERROR_ADDRESS and ECC_CORRECTION_INFO registers were deprecated. Instead, the number of corrected bit-flips can be read from the ECC_COR_INFO register. When an uncorrectable ECC error happens, a status flag is set to the INTR_STATUS and ECC_COR_INFO registers. As is often the case with this IP, the register view of INTR_STATUS had broken compatibility. For older versions (SW ECC fixup): bit 0: ECC_TRANSACTION_DONE bit 1: ECC_ERR For newer versions (HW ECC fixup): bit 0: ECC_UNCOR_ERR bit 1: Reserved Due to this difference, the irq_mask must be fixed too. The comment block in handle_ecc() has been moved to the common part because the comment applies to both cases. The existing handle_ecc() has been renamed to denali_sw_ecc_fixup() for clarification. The U-Boot port of this driver already supports the HW ECC fixup. I borrowed the comment "Some versions of ..." in denali.h from U-Boot. Signed-off-by: Masahiro Yamada --- Changes in v2: - Change the capability prefix DENALI_CAPS_ -> DENALI_CAP_ drivers/mtd/nand/denali.c | 52 ++++++++++++++++++++++++++++++++++++----------- drivers/mtd/nand/denali.h | 14 +++++++++++++ 2 files changed, 54 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 608fe6f..91f0def 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -883,6 +883,32 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) } } +static int denali_hw_ecc_fixup(struct mtd_info *mtd, + struct denali_nand_info *denali) +{ + int bank = denali->flash_bank; + uint32_t ecc_cor; + unsigned int max_bitflips; + + ecc_cor = ioread32(denali->flash_reg + ECC_COR_INFO(bank)); + ecc_cor >>= ECC_COR_INFO__SHIFT(bank); + + if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) + return -EBADMSG; + + max_bitflips = ecc_cor & ECC_COR_INFO__MAX_ERRORS; + + /* + * The register holds the maximum of the number of corrected bitflips + * per sector. This can be returned from ecc->read_page() as-is. + * Unfortunately, we can not know the total number of corrected bits + * in the page. mtd->ecc_stats.corrected is compromised here. + */ + mtd->ecc_stats.corrected += max_bitflips; + + return max_bitflips; +} + #define ECC_SECTOR_SIZE 512 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) @@ -892,8 +918,8 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) -static int handle_ecc(struct mtd_info *mtd, - struct denali_nand_info *denali, uint8_t *buf) +static int denali_sw_ecc_fixup(struct mtd_info *mtd, + struct denali_nand_info *denali, uint8_t *buf) { unsigned int bitflips = 0; unsigned int max_bitflips = 0; @@ -921,11 +947,6 @@ static int handle_ecc(struct mtd_info *mtd, bitflips = 0; if (ECC_ERROR_UNCORRECTABLE(err_cor_info)) { - /* - * if the error is not correctable, need to look at the - * page to see if it is an erased page. if so, then - * it's not a real ECC error - */ ret = -EBADMSG; } else if (err_byte < ECC_SECTOR_SIZE) { /* @@ -1105,12 +1126,12 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); - dma_addr_t addr = denali->buf.dma_buf; size_t size = mtd->writesize + mtd->oobsize; - uint32_t irq_status; - uint32_t irq_mask = INTR__ECC_TRANSACTION_DONE | INTR__ECC_ERR; + uint32_t irq_mask = denali->caps & DENALI_CAP_HW_ECC_FIXUP ? + INTR__DMA_CMD_COMP | INTR__ECC_UNCOR_ERR : + INTR__ECC_TRANSACTION_DONE | INTR__ECC_ERR; int stat = 0; if (page != denali->page) { @@ -1135,11 +1156,18 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, memcpy(buf, denali->buf.buf, mtd->writesize); - if (irq_status & INTR__ECC_ERR) - stat = handle_ecc(mtd, denali, buf); + if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) + stat = denali_hw_ecc_fixup(mtd, denali); + else if (irq_status & INTR__ECC_ERR) + stat = denali_sw_ecc_fixup(mtd, denali, buf); denali_enable_dma(denali, false); if (stat == -EBADMSG) { + /* + * If the error is not correctable, need to look at the page to + * see if it is an erased page. If so, then it's not a real ECC + * error. + */ read_oob_data(mtd, chip->oob_poi, denali->page); stat = nand_check_erased_ecc_chunk( diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 7b2d785..ed42b16 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -20,6 +20,7 @@ #ifndef __DENALI_H__ #define __DENALI_H__ +#include #include #define DEVICE_RESET 0x0 @@ -218,6 +219,13 @@ #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) +/* + * Some versions of the IP have the ECC fixup handled in hardware. In this + * configuration we only get interrupted when the error is uncorrectable. + * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the + * old IP. + */ +#define INTR__ECC_UNCOR_ERR 0x0001 #define INTR__ECC_TRANSACTION_DONE 0x0001 #define INTR__ECC_ERR 0x0002 #define INTR__DMA_CMD_COMP 0x0004 @@ -259,6 +267,11 @@ #define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 #define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 +#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) +#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) +#define ECC_COR_INFO__MAX_ERRORS 0x007f +#define ECC_COR_INFO__UNCOR_ERR 0x0080 + #define DMA_ENABLE 0x700 #define DMA_ENABLE__FLAG 0x0001 @@ -339,6 +352,7 @@ struct denali_nand_info { int bbtskipbytes; int max_banks; unsigned int caps; +#define DENALI_CAP_HW_ECC_FIXUP BIT(0) }; extern int denali_init(struct denali_nand_info *denali); From patchwork Wed Mar 22 20:07:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95828 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413488qgd; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) X-Received: by 10.98.134.142 with SMTP id x136mr48866067pfd.64.1490213569115; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 63si2130331pfl.124.2017.03.22.13.12.48; Wed, 22 Mar 2017 13:12:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751773AbdCVUMq (ORCPT + 11 others); Wed, 22 Mar 2017 16:12:46 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25274 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751454AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8964029452; Thu, 23 Mar 2017 05:08:35 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8964029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213316; bh=9SLvobft3NRln3CJ75gdFVjmMYflLyfuuo0womwkTgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XnM+iuR8iKBjIoCEBjTpUZNHBNdbqTnJ9kr9R/YYTnmET6FQkf96KD4VTJgOkYGFL XlT4maPqLP8H8GWd4adGnP3DcpAyq5+637aueTD4YHYN1pZtUZ1VdSh/8097GU5aux JFFeHxq6W6i6akEjem6PUoWuCzsOrzLDeKZ9dcSWb5uiSUkM5uwnE4NbjuoVwQ2G3C L3DWP4OXxaeB7IUXt+Vl3HH5uW/u3xvgpuXykFT0HmOIjYA1bsfYhOdwPzufb5Gu/e uxaKp0jMG+n6/t/x+qMirE55CwePE58XOEFb+i1QLGBFjyMSU39CZbtQ61Ks0mcIkT gXjhWk2kr35jw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 14/53] mtd: nand: denali: support 64bit capable DMA engine Date: Thu, 23 Mar 2017 05:07:13 +0900 Message-Id: <1490213273-8571-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current driver only supports the DMA engine up to 32 bit physical address, but there also exists 64 bit capable DMA engine for this IP. The data DMA setup sequence is completely different, so I added the 64 bit DMA code as a new function denali_setup_dma64(). The 32 bit one has been renamed to denali_setup_dma32(). Signed-off-by: Masahiro Yamada --- Changes in v2: - Change the capability prefix DENALI_CAPS_ -> DENALI_CAP_ drivers/mtd/nand/denali.c | 39 +++++++++++++++++++++++++++++++++++---- drivers/mtd/nand/denali.h | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 91f0def..513292f 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -999,8 +999,30 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en) ioread32(denali->flash_reg + DMA_ENABLE); } -/* setups the HW to perform the data DMA */ -static void denali_setup_dma(struct denali_nand_info *denali, int op) +static void denali_setup_dma64(struct denali_nand_info *denali, int op) +{ + uint32_t mode; + const int page_count = 1; + uint64_t addr = denali->buf.dma_buf; + + mode = MODE_10 | BANK(denali->flash_bank) | denali->page; + + /* DMA is a three step process */ + + /* + * 1. setup transfer type, interrupt when complete, + * burst len = 64 bytes, the number of pages + */ + index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); + + /* 2. set memory low address */ + index_addr(denali, mode, addr); + + /* 3. set memory high address */ + index_addr(denali, mode, addr >> 32); +} + +static void denali_setup_dma32(struct denali_nand_info *denali, int op) { uint32_t mode; const int page_count = 1; @@ -1023,6 +1045,14 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op) index_addr(denali, mode | 0x14000, 0x2400); } +static void denali_setup_dma(struct denali_nand_info *denali, int op) +{ + if (denali->caps & DENALI_CAP_DMA_64BIT) + denali_setup_dma64(denali, op); + else + denali_setup_dma32(denali, op); +} + /* * writes a page. user specifies type, and this function handles the * configuration details. @@ -1492,8 +1522,9 @@ int denali_init(struct denali_nand_info *denali) goto failed_req_irq; } - /* Is 32-bit DMA supported? */ - ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask(denali->dev, + DMA_BIT_MASK(denali->caps & DENALI_CAP_DMA_64BIT ? + 64 : 32)); if (ret) { dev_err(denali->dev, "No usable DMA configuration\n"); goto failed_req_irq; diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index ed42b16..a8e8d68 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -353,6 +353,7 @@ struct denali_nand_info { int max_banks; unsigned int caps; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) +#define DENALI_CAP_DMA_64BIT BIT(1) }; extern int denali_init(struct denali_nand_info *denali); From patchwork Wed Mar 22 20:07:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95847 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415565qgd; Wed, 22 Mar 2017 13:18:11 -0700 (PDT) X-Received: by 10.84.224.133 with SMTP id s5mr56528613plj.93.1490213891404; Wed, 22 Mar 2017 13:18:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i21si2979672pgh.289.2017.03.22.13.18.11; Wed, 22 Mar 2017 13:18:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752621AbdCVUQ5 (ORCPT + 11 others); Wed, 22 Mar 2017 16:16:57 -0400 Received: from condef-09.nifty.com ([202.248.20.74]:51656 "EHLO condef-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752533AbdCVUPz (ORCPT ); Wed, 22 Mar 2017 16:15:55 -0400 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-09.nifty.com with ESMTP id v2MKBmbQ019381; Thu, 23 Mar 2017 05:11:48 +0900 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8965029452; Thu, 23 Mar 2017 05:08:37 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8965029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213318; bh=k0OolJzglYZESV6rxKJganwnwaMw8DLMYS5PnlGJdLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i6pou6t7kC2mu7C3WM2NZjjJndHdzgobTIIftlEEPXxqWoohocZD5H2tzKH2rayit yD8ayI+DmXOGndJJaHzb1HbLJiimamRcmf+CnheNpXzldJ++ynTFDQ83h/QDLJ6+V5 Kcz/Js+JOKagPxcSb8h2r0WJZaMyaOBVzWao4GTauVu6MISomobXA0cktn2X4iLVf0 Sj0CpBRRldfuo6aQHxz5hYoCg1BmJh8tQAisq4GpqMf+NJ7mJ9x/Xc94WRdJ0mnUDC 9D/+8AUXZpax6RuFSBUy6D5ah06z209GBcTYItb+fREwWxydJoBbUE/SaOUX22fTHp 2uJCOtvmveLDw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen , Rob Herring , Mark Rutland Subject: [RESEND PATCH v2 15/53] mtd: nand: denali_dt: remove dma-mask DT property Date: Thu, 23 Mar 2017 05:07:14 +0900 Message-Id: <1490213273-8571-16-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver sets appropriate DMA mask. Delete the "dma-mask" DT property. See [1] for negative comments for this binding. [1] https://lkml.org/lkml/2016/2/8/57 Signed-off-by: Masahiro Yamada Acked-by: Rob Herring --- Changes in v2: None Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 -- drivers/mtd/nand/denali_dt.c | 9 --------- 2 files changed, 11 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index 6f4ab4c..e593bbe 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -6,7 +6,6 @@ Required properties: - reg : should contain registers location and length for data and reg. - reg-names: Should contain the reg names "nand_data" and "denali_reg" - interrupts : The interrupt number. - - dm-mask : DMA bit mask The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. @@ -20,5 +19,4 @@ nand: nand@ff900000 { reg = <0xff900000 0x100000>, <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 144 4>; - dma-mask = <0xffffffff>; }; diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 9577bfd..b8a8284 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -46,8 +46,6 @@ static const struct of_device_id denali_nand_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); -static u64 denali_dma_mask; - static int denali_dt_probe(struct platform_device *ofdev) { struct resource *denali_reg, *nand_data; @@ -83,13 +81,6 @@ static int denali_dt_probe(struct platform_device *ofdev) if (IS_ERR(denali->flash_mem)) return PTR_ERR(denali->flash_mem); - if (!of_property_read_u32(ofdev->dev.of_node, - "dma-mask", (u32 *)&denali_dma_mask)) { - denali->dev->dma_mask = &denali_dma_mask; - } else { - denali->dev->dma_mask = NULL; - } - dt->clk = devm_clk_get(&ofdev->dev, NULL); if (IS_ERR(dt->clk)) { dev_err(&ofdev->dev, "no clk available\n"); From patchwork Wed Mar 22 20:07:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95845 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415376qgd; Wed, 22 Mar 2017 13:17:45 -0700 (PDT) X-Received: by 10.98.223.133 with SMTP id d5mr49155722pfl.222.1490213865114; Wed, 22 Mar 2017 13:17:45 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v8si2993871pgo.187.2017.03.22.13.17.44; Wed, 22 Mar 2017 13:17:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752747AbdCVURb (ORCPT + 11 others); Wed, 22 Mar 2017 16:17:31 -0400 Received: from condef-10.nifty.com ([202.248.20.75]:49313 "EHLO condef-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdCVURR (ORCPT ); Wed, 22 Mar 2017 16:17:17 -0400 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-10.nifty.com with ESMTP id v2MKBptI009240 for ; Thu, 23 Mar 2017 05:11:51 +0900 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8967029452; Thu, 23 Mar 2017 05:08:39 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8967029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213320; bh=uTxP8uSgKDdcyWTVMZxtm2JF7W6b7or+g/XUZVmI6+g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cbTRcP8G99owiK57bi7+Y+2dXPcTh14VcZEoYlE7QXMh0g0imhFkFxVpi9N+Bl9PP OTKgRRcnCi7FrCQESCXHyTOjEcOm9vpqwKMY13xRGbTEr2zZsQ5Cxxuw8XBmlOPlKK HbObeArgTyN9vEVeCP1eab9PQdTSQYgYatm+xrnTVzGNBbKbx64VqsbJFfDxWysufu 0OWZEkhbNsrHjmpCl/07IV+IpYJ38wX1wtpuCjUgNhZfhetMyRqaSn4Iv9XBCeTca3 v9njQrGbzicnU2CS+i5z/JhBiEAj+U/7UzUfj6/doF3b274VuptrJS1TKhncyj/BJa 7ZeDHuglGR3HQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 17/53] mtd: nand: denali: allow to override revision number Date: Thu, 23 Mar 2017 05:07:16 +0900 Message-Id: <1490213273-8571-18-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 271707b1d817 ("mtd: nand: denali: max_banks calculation changed in revision 5.1") added a revision check to support the new max_banks encoding. Its git-log states "The encoding of max_banks changed in Denali revision 5.1". There are exceptional cases, for example, the revision register on some UniPhier SoCs says the IP is 5.0 but the max_banks is encoded in the new format. This IP updates the resister specification from time to time (often breaking the backward compatibility), but the revision number is not incremented correctly. The max_banks is not only the case that needs revision checking. Let's allow to override an incorrect revision number. Signed-off-by: Masahiro Yamada --- Changes in v2: - Replace the NEW_N_BANKS_FORMAT approach drivers/mtd/nand/denali.c | 19 +++++++++---------- drivers/mtd/nand/denali.h | 3 +-- drivers/mtd/nand/denali_dt.c | 5 ++++- 3 files changed, 14 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 513292f..ff6af1d 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -449,17 +449,12 @@ static void find_valid_banks(struct denali_nand_info *denali) static void detect_max_banks(struct denali_nand_info *denali) { uint32_t features = ioread32(denali->flash_reg + FEATURES); - /* - * Read the revision register, so we can calculate the max_banks - * properly: the encoding changed from rev 5.0 to 5.1 - */ - u32 revision = MAKE_COMPARABLE_REVISION( - ioread32(denali->flash_reg + REVISION)); - if (revision < REVISION_5_1) - denali->max_banks = 2 << (features & FEATURES__N_BANKS); - else - denali->max_banks = 1 << (features & FEATURES__N_BANKS); + denali->max_banks = 1 << (features & FEATURES__N_BANKS); + + /* the encoding changed from rev 5.0 to 5.1 */ + if (denali->revision < 0x0501) + denali->max_banks <<= 1; } static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) @@ -1348,6 +1343,10 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, /* Initialization code to bring the device up to a known good state */ static void denali_hw_init(struct denali_nand_info *denali) { + if (!denali->revision) + denali->revision = + swab16(ioread32(denali->flash_reg + REVISION)); + /* * tell driver how many bit controller will skip before * writing ECC code in OOB, this register may be already diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index a8e8d68..58a8042 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -179,8 +179,6 @@ #define REVISION 0x370 #define REVISION__VALUE 0xffff -#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE) -#define REVISION_5_1 0x00000501 #define ONFI_DEVICE_FEATURES 0x380 #define ONFI_DEVICE_FEATURES__VALUE 0x003f @@ -351,6 +349,7 @@ struct denali_nand_info { int devnum; /* represent how many nands connected */ int bbtskipbytes; int max_banks; + unsigned int revision; unsigned int caps; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) #define DENALI_CAP_DMA_64BIT BIT(1) diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index ada3863..df9ef36 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -30,6 +30,7 @@ struct denali_dt { }; struct denali_dt_data { + unsigned int revision; unsigned int caps; }; @@ -60,8 +61,10 @@ static int denali_dt_probe(struct platform_device *pdev) denali = &dt->denali; data = of_device_get_match_data(&pdev->dev); - if (data) + if (data) { + denali->revision = data->revision; denali->caps = data->caps; + } denali->platform = DT; denali->dev = &pdev->dev; From patchwork Wed Mar 22 20:07:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95843 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415223qgd; Wed, 22 Mar 2017 13:17:21 -0700 (PDT) X-Received: by 10.98.108.196 with SMTP id h187mr49140251pfc.233.1490213841680; Wed, 22 Mar 2017 13:17:21 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i5si2986774pgk.180.2017.03.22.13.17.21; Wed, 22 Mar 2017 13:17:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752703AbdCVURJ (ORCPT + 11 others); Wed, 22 Mar 2017 16:17:09 -0400 Received: from condef-07.nifty.com ([202.248.20.72]:49967 "EHLO condef-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdCVURF (ORCPT ); Wed, 22 Mar 2017 16:17:05 -0400 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-07.nifty.com with ESMTP id v2MKBp5x001543 for ; Thu, 23 Mar 2017 05:11:51 +0900 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK8968029452; Thu, 23 Mar 2017 05:08:41 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK8968029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213322; bh=QZtC1PwWoPdhAms0pfDpaW1R8+f0pfBPDcJb0an838U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ESXhO621bgscHaMWBi74fovOPz2mGR4JEfUD7bu4nSwNpkRUmPc4lSgW9CRjIJV92 AbaVHWu1fefw2OPsDWvGD05rzE8uIE6kUpW+PW8TtS28+hL3gSz8b3ghso/KKQC6qJ ivDhGVlSaqAxbqGvcoxJLK/YC1uXALM2t3E1SIRyz81UePuYP2jV98XW6ViMi0ApOW u+NmDeu3RlRzRKlZsZ2HBEu7yg/IDfptxzsiHnijXooisjWL1+3w3sHkGmPYM49kd2 jgC1xlOPMZzx2fH6ib/8vVav3lAzFJ/wXUcajcy5AMXyC7PlShrr2XaIWVE8lrQz3L 4ZOpiBNq9slGQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 18/53] mtd: nand: denali: use nand_chip to hold frequently accessed data Date: Thu, 23 Mar 2017 05:07:17 +0900 Message-Id: <1490213273-8571-19-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The denali_init() needs to setup a bunch of parameters of nand_chip. Replace denali->nand.(member) with chip->(member) for shorter code. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 68 +++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 34 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ff6af1d..24c35a6 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1460,7 +1460,8 @@ static void denali_drv_init(struct denali_nand_info *denali) int denali_init(struct denali_nand_info *denali) { - struct mtd_info *mtd = nand_to_mtd(&denali->nand); + struct nand_chip *chip = &denali->nand; + struct mtd_info *mtd = nand_to_mtd(chip); int ret; if (denali->platform == INTEL_CE4100) { @@ -1497,10 +1498,10 @@ int denali_init(struct denali_nand_info *denali) mtd->name = "denali-nand"; /* register the driver with the NAND core subsystem */ - denali->nand.select_chip = denali_select_chip; - denali->nand.cmdfunc = denali_cmdfunc; - denali->nand.read_byte = denali_read_byte; - denali->nand.waitfunc = denali_waitfunc; + chip->select_chip = denali_select_chip; + chip->cmdfunc = denali_cmdfunc; + chip->read_byte = denali_read_byte; + chip->waitfunc = denali_waitfunc; /* * scan for NAND devices attached to the controller @@ -1544,17 +1545,16 @@ int denali_init(struct denali_nand_info *denali) * the real pagesize and anything necessery */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); - denali->nand.chipsize <<= denali->devnum - 1; - denali->nand.page_shift += denali->devnum - 1; - denali->nand.pagemask = (denali->nand.chipsize >> - denali->nand.page_shift) - 1; - denali->nand.bbt_erase_shift += denali->devnum - 1; - denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; - denali->nand.chip_shift += denali->devnum - 1; + chip->chipsize <<= denali->devnum - 1; + chip->page_shift += denali->devnum - 1; + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; + chip->bbt_erase_shift += denali->devnum - 1; + chip->phys_erase_shift = chip->bbt_erase_shift; + chip->chip_shift += denali->devnum - 1; mtd->writesize <<= denali->devnum - 1; mtd->oobsize <<= denali->devnum - 1; mtd->erasesize <<= denali->devnum - 1; - mtd->size = denali->nand.numchips * denali->nand.chipsize; + mtd->size = chip->numchips * chip->chipsize; denali->bbtskipbytes *= denali->devnum; /* @@ -1564,29 +1564,29 @@ int denali_init(struct denali_nand_info *denali) */ /* Bad block management */ - denali->nand.bbt_td = &bbt_main_descr; - denali->nand.bbt_md = &bbt_mirror_descr; + chip->bbt_td = &bbt_main_descr; + chip->bbt_md = &bbt_mirror_descr; /* skip the scan for now until we have OOB read and write support */ - denali->nand.bbt_options |= NAND_BBT_USE_FLASH; - denali->nand.options |= NAND_SKIP_BBTSCAN; - denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; + chip->bbt_options |= NAND_BBT_USE_FLASH; + chip->options |= NAND_SKIP_BBTSCAN; + chip->ecc.mode = NAND_ECC_HW_SYNDROME; /* no subpage writes on denali */ - denali->nand.options |= NAND_NO_SUBPAGE_WRITE; + chip->options |= NAND_NO_SUBPAGE_WRITE; /* * Denali Controller only support 15bit and 8bit ECC in MRST, * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ - if (!nand_is_slc(&denali->nand) && + if (!nand_is_slc(chip) && (mtd->oobsize > (denali->bbtskipbytes + ECC_15BITS * (mtd->writesize / ECC_SECTOR_SIZE)))) { /* if MLC OOB size is large enough, use 15bit ECC*/ - denali->nand.ecc.strength = 15; - denali->nand.ecc.bytes = ECC_15BITS; + chip->ecc.strength = 15; + chip->ecc.bytes = ECC_15BITS; iowrite32(15, denali->flash_reg + ECC_CORRECTION); } else if (mtd->oobsize < (denali->bbtskipbytes + ECC_8BITS * (mtd->writesize / @@ -1594,24 +1594,24 @@ int denali_init(struct denali_nand_info *denali) pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); goto failed_req_irq; } else { - denali->nand.ecc.strength = 8; - denali->nand.ecc.bytes = ECC_8BITS; + chip->ecc.strength = 8; + chip->ecc.bytes = ECC_8BITS; iowrite32(8, denali->flash_reg + ECC_CORRECTION); } mtd_set_ooblayout(mtd, &denali_ooblayout_ops); - denali->nand.ecc.bytes *= denali->devnum; - denali->nand.ecc.strength *= denali->devnum; + chip->ecc.bytes *= denali->devnum; + chip->ecc.strength *= denali->devnum; /* override the default read operations */ - denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; - denali->nand.ecc.read_page = denali_read_page; - denali->nand.ecc.read_page_raw = denali_read_page_raw; - denali->nand.ecc.write_page = denali_write_page; - denali->nand.ecc.write_page_raw = denali_write_page_raw; - denali->nand.ecc.read_oob = denali_read_oob; - denali->nand.ecc.write_oob = denali_write_oob; - denali->nand.erase = denali_erase; + chip->ecc.size = ECC_SECTOR_SIZE * denali->devnum; + chip->ecc.read_page = denali_read_page; + chip->ecc.read_page_raw = denali_read_page_raw; + chip->ecc.write_page = denali_write_page; + chip->ecc.write_page_raw = denali_write_page_raw; + chip->ecc.read_oob = denali_read_oob; + chip->ecc.write_oob = denali_write_oob; + chip->erase = denali_erase; ret = nand_scan_tail(mtd); if (ret) From patchwork Wed Mar 22 20:07:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95835 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413912qgd; Wed, 22 Mar 2017 13:13:56 -0700 (PDT) X-Received: by 10.98.192.217 with SMTP id g86mr47648917pfk.170.1490213636524; Wed, 22 Mar 2017 13:13:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2964310pgc.350.2017.03.22.13.13.56; Wed, 22 Mar 2017 13:13:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752008AbdCVUNq (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:46 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:24984 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751441AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896A029452; Thu, 23 Mar 2017 05:08:43 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896A029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213324; bh=O8JPIucCF07Nakg4ppK7wT0JGjjUZzgayy+q5W5ewDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DK6rnYu6Z+B+DQlWD8LT7/NTeqxFJ+IovCXSgLR4seIOYVBeId9gGfVmNFH0fkVGw PN9BVsq3RYYf7l6KpdyrRERVQu4DeHWr586uUhlYjUEqAcS4EEU2a1DCoStPIyUvzO NRnMPg+dSGeJ2g8apXMxPAgRz8AHHlR/LO1HJ8Vg24agEHM0yWMs/Rl0IwRoZqRmZd el2Hc4v7vC1Z73faK8TlH4EpohRvwh6k0hqMv2fpCAeeq0Eb9Cd8BvvinLKVHOAaQa /T4OU9a+PQ9NBugNKjMj5TjJtFQ6P7cH3CDGvfy1J97CxF8AkMubxENWkb6BbnCqCC Ow1cUhWcbSeqA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 20/53] mtd: nand: denali: do not set mtd->name Date: Thu, 23 Mar 2017 05:07:19 +0900 Message-Id: <1490213273-8571-21-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This will be filled by nand_scan_ident() later. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 1 - 1 file changed, 1 deletion(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3badb1d..1706975 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1495,7 +1495,6 @@ int denali_init(struct denali_nand_info *denali) /* now that our ISR is registered, we can enable interrupts */ denali_set_intr_modes(denali, true); - mtd->name = "denali-nand"; nand_set_flash_node(chip, denali->dev->of_node); /* register the driver with the NAND core subsystem */ From patchwork Wed Mar 22 20:07:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95833 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413905qgd; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) X-Received: by 10.99.175.66 with SMTP id s2mr14573245pgo.30.1490213635205; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2964310pgc.350.2017.03.22.13.13.54; Wed, 22 Mar 2017 13:13:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751938AbdCVUNb (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:31 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25185 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751452AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896B029452; Thu, 23 Mar 2017 05:08:44 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896B029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213325; bh=+BdYgaCimnBuNwXJS61p9WaED1bYNvo9IRK2uAAiokc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xFM4khCCKonVvYfc4WpbbO90MV/I2q0PqeUhkL1fYKnKB440hWR0CFL1H6pRIi7kU UXgjWbBqMDH+TS0wRv6NQtjPLz++4wKTpTPZNem0YQHDk3EWeNPhUOteH8AhRgYnXC tdoXCfJCXePItSZTAiox7mSb1COfgM8CZsj2WQtgdBjOcGdohI5w60BIQdfzXcUd+5 RYBFLt5Ir9cHA76zIBzmWPVgbDvWlXTaxhr8mNM07zTRTNAiexDvCHZNaH0gk3M1m+ FKRhcqD7b+vOQmKH+s0E2vy1gnp58702VrgM1ApRs1j2usjRY1MseeT9369XIdlYbM YwvtL1FvQI26w== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 21/53] mtd: nand: denali: move multi device fixup code to a helper function Date: Thu, 23 Mar 2017 05:07:20 +0900 Message-Id: <1490213273-8571-22-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Collect multi NAND fixups into a helper function instead of scattering them in denali_init(). I am rewording the comment block to clearly explain what is called "multi device". Signed-off-by: Masahiro Yamada --- Changes in v2: - Reword the comment block for clarification drivers/mtd/nand/denali.c | 54 +++++++++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 1706975..4e63d57 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1458,6 +1458,36 @@ static void denali_drv_init(struct denali_nand_info *denali) denali->irq_status = 0; } +static void denali_multidev_fixup(struct denali_nand_info *denali) +{ + struct nand_chip *chip = &denali->nand; + struct mtd_info *mtd = nand_to_mtd(chip); + + /* + * Support for multi device: + * When the IP configuration is x16 capable and two x8 chips are + * connected in parallel, DEVICES_CONNECTED should be set to 2. + * In this case, the core framework knows nothing about this fact, + * so we should tell it the _logical_ pagesize and anything necessary. + */ + denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); + + mtd->size <<= denali->devnum - 1; + mtd->erasesize <<= denali->devnum - 1; + mtd->writesize <<= denali->devnum - 1; + mtd->oobsize <<= denali->devnum - 1; + chip->chipsize <<= denali->devnum - 1; + chip->page_shift += denali->devnum - 1; + chip->phys_erase_shift += denali->devnum - 1; + chip->bbt_erase_shift += denali->devnum - 1; + chip->chip_shift += denali->devnum - 1; + chip->pagemask <<= denali->devnum - 1; + chip->ecc.size *= denali->devnum; + chip->ecc.bytes *= denali->devnum; + chip->ecc.strength *= denali->devnum; + denali->bbtskipbytes *= denali->devnum; +} + int denali_init(struct denali_nand_info *denali) { struct nand_chip *chip = &denali->nand; @@ -1540,24 +1570,6 @@ int denali_init(struct denali_nand_info *denali) } /* - * support for multi nand - * MTD known nothing about multi nand, so we should tell it - * the real pagesize and anything necessery - */ - denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); - chip->chipsize <<= denali->devnum - 1; - chip->page_shift += denali->devnum - 1; - chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; - chip->bbt_erase_shift += denali->devnum - 1; - chip->phys_erase_shift = chip->bbt_erase_shift; - chip->chip_shift += denali->devnum - 1; - mtd->writesize <<= denali->devnum - 1; - mtd->oobsize <<= denali->devnum - 1; - mtd->erasesize <<= denali->devnum - 1; - mtd->size = chip->numchips * chip->chipsize; - denali->bbtskipbytes *= denali->devnum; - - /* * second stage of the NAND scan * this stage requires information regarding ECC and * bad block management. @@ -1600,11 +1612,9 @@ int denali_init(struct denali_nand_info *denali) } mtd_set_ooblayout(mtd, &denali_ooblayout_ops); - chip->ecc.bytes *= denali->devnum; - chip->ecc.strength *= denali->devnum; /* override the default read operations */ - chip->ecc.size = ECC_SECTOR_SIZE * denali->devnum; + chip->ecc.size = ECC_SECTOR_SIZE; chip->ecc.read_page = denali_read_page; chip->ecc.read_page_raw = denali_read_page_raw; chip->ecc.write_page = denali_write_page; @@ -1613,6 +1623,8 @@ int denali_init(struct denali_nand_info *denali) chip->ecc.write_oob = denali_write_oob; chip->erase = denali_erase; + denali_multidev_fixup(denali); + ret = nand_scan_tail(mtd); if (ret) goto failed_req_irq; From patchwork Wed Mar 22 20:07:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95832 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413896qgd; Wed, 22 Mar 2017 13:13:54 -0700 (PDT) X-Received: by 10.98.137.75 with SMTP id v72mr49081085pfd.190.1490213634255; Wed, 22 Mar 2017 13:13:54 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si2964310pgc.350.2017.03.22.13.13.53; Wed, 22 Mar 2017 13:13:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751904AbdCVUN0 (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:26 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:24986 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751442AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896C029452; Thu, 23 Mar 2017 05:08:46 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896C029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213327; bh=G+AgR3Ob/63ow59ue1QR6E0QhLg1wbcp7WadF72jlqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LLR/Wfchxk457nhByE/IwJWD938YhQWoi5b/f6RCjtS0sxxXPXo1sM5ECx5ZPk+aK o8MZNeMTDRG9vQHVeZUevFcJBfPRW0IQs2WY6fNZ/2ltoC4s72Ka9JXSnO/LnMOw+y eecKVyeLtd4goeNCO6jmGCwaZFMgIGleT02fJBsrea3PElSoq4PrPRhrcOl/NpI8WG k8RxP2Gv4375f1jmTQP1AUf+qUTnMidOxfSI52n8n9ZhRncv6UMuokZEYh8UA2U56Q s21gkaW90qzY/P5pU/Y6AIPC66Jdo9fsEV7xkReiy9flezAyRhJPp9gibdNM0unRvg E23UFdm2K72kQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 22/53] mtd: nand: denali: simplify multi device fixup code Date: Thu, 23 Mar 2017 05:07:21 +0900 Message-Id: <1490213273-8571-23-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The available configuration of the IP bus width is x8 or x16, so the possible value for denali->devnum is 1 or 2. If the value is 1, there is nothing to do. Fixup parameters only when denali->devnum is 2. Signed-off-by: Masahiro Yamada --- Changes in v2: - Simplify the code given 1 or 2 is possible for denali->devnum drivers/mtd/nand/denali.c | 46 ++++++++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 4e63d57..abf8997 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1458,7 +1458,7 @@ static void denali_drv_init(struct denali_nand_info *denali) denali->irq_status = 0; } -static void denali_multidev_fixup(struct denali_nand_info *denali) +static int denali_multidev_fixup(struct denali_nand_info *denali) { struct nand_chip *chip = &denali->nand; struct mtd_info *mtd = nand_to_mtd(chip); @@ -1472,20 +1472,32 @@ static void denali_multidev_fixup(struct denali_nand_info *denali) */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); - mtd->size <<= denali->devnum - 1; - mtd->erasesize <<= denali->devnum - 1; - mtd->writesize <<= denali->devnum - 1; - mtd->oobsize <<= denali->devnum - 1; - chip->chipsize <<= denali->devnum - 1; - chip->page_shift += denali->devnum - 1; - chip->phys_erase_shift += denali->devnum - 1; - chip->bbt_erase_shift += denali->devnum - 1; - chip->chip_shift += denali->devnum - 1; - chip->pagemask <<= denali->devnum - 1; - chip->ecc.size *= denali->devnum; - chip->ecc.bytes *= denali->devnum; - chip->ecc.strength *= denali->devnum; - denali->bbtskipbytes *= denali->devnum; + if (denali->devnum == 1) + return 0; + + if (denali->devnum != 2) { + dev_err(denali->dev, "unsupported number of devices %d\n", + denali->devnum); + return -EINVAL; + } + + /* 2 chips in parallel */ + mtd->size <<= 1; + mtd->erasesize <<= 1; + mtd->writesize <<= 1; + mtd->oobsize <<= 1; + chip->chipsize <<= 1; + chip->page_shift += 1; + chip->phys_erase_shift += 1; + chip->bbt_erase_shift += 1; + chip->chip_shift += 1; + chip->pagemask <<= 1; + chip->ecc.size <<= 1; + chip->ecc.bytes <<= 1; + chip->ecc.strength <<= 1; + denali->bbtskipbytes <<= 1; + + return 0; } int denali_init(struct denali_nand_info *denali) @@ -1623,7 +1635,9 @@ int denali_init(struct denali_nand_info *denali) chip->ecc.write_oob = denali_write_oob; chip->erase = denali_erase; - denali_multidev_fixup(denali); + ret = denali_multidev_fixup(denali); + if (ret) + goto failed_req_irq; ret = nand_scan_tail(mtd); if (ret) From patchwork Wed Mar 22 20:07:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95830 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp413658qgd; Wed, 22 Mar 2017 13:13:15 -0700 (PDT) X-Received: by 10.98.211.143 with SMTP id z15mr49459050pfk.46.1490213595609; Wed, 22 Mar 2017 13:13:15 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k80si2116963pfk.272.2017.03.22.13.13.15; Wed, 22 Mar 2017 13:13:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751833AbdCVUNE (ORCPT + 11 others); Wed, 22 Mar 2017 16:13:04 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25128 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751449AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896D029452; Thu, 23 Mar 2017 05:08:47 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896D029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213328; bh=lJjun7m07Up94XhckEfI9LGZQhK6861r5EIlvWfOCpk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tX8nqjDtkzjdRzDjHJmBEexHmpzZsMPfXmmR0KuJhsaMupYgIEA32ZKe8T81iLGYQ O8PeepUQc7g0qNZghpJ7B8Gl7U4t3dcbN1J577P2LgU3hJ4F6/SFM55/wGpNiAGLKN YTmwe129MzIl4xDoMaFa2YTN0sOoNBg4q5Cc4CznaEEMBtvUp5lA4CrIedImA4QB8k Y6vT/de5MymFIMwdKQ6/wOcOPj0eKtT27EnXzmApTMWAQq+VZ+lLeFIn/A7KFfH7dY AeHvszXF3Of7Q/4aztx+VCFLGpLz0FB4yv4rZ1V5bB+JJzetwqQ4kcRcQG72pIJoJZ DGN3zWZNtLbdQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 23/53] mtd: nand: denali: set DEVICES_CONNECTED 1 if not set Date: Thu, 23 Mar 2017 05:07:22 +0900 Message-Id: <1490213273-8571-24-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, the driver expects DEVICE_CONNECTED is automatically set by the hardware, but this feature is disabled in some cases. In such cases, it is the software's responsibility to set up the DEVICES_CONNECTED register. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index abf8997..3da0a0e 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1472,6 +1472,15 @@ static int denali_multidev_fixup(struct denali_nand_info *denali) */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); + /* + * On some SoCs, DEVICES_CONNECTED is not auto-detected. + * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. + */ + if (denali->devnum == 0) { + denali->devnum = 1; + iowrite32(1, denali->flash_reg + DEVICES_CONNECTED); + } + if (denali->devnum == 1) return 0; From patchwork Wed Mar 22 20:07:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95850 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp415747qgd; Wed, 22 Mar 2017 13:18:38 -0700 (PDT) X-Received: by 10.98.207.68 with SMTP id b65mr48319422pfg.12.1490213918266; Wed, 22 Mar 2017 13:18:38 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v19si3010694pgj.29.2017.03.22.13.18.37; Wed, 22 Mar 2017 13:18:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752487AbdCVUPY (ORCPT + 11 others); Wed, 22 Mar 2017 16:15:24 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:24951 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751425AbdCVUL6 (ORCPT ); Wed, 22 Mar 2017 16:11:58 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896E029452; Thu, 23 Mar 2017 05:08:48 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896E029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213329; bh=ETbm79CiIOZbgKFV5qv7tXWHCr+CVtF1sohZbi3+yhw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mwxva5lUl+/HO/dCds2OJdneSZiyGvkauPZBwDotyP7vH8Yi64DpiWRrvJRPCth2/ c60aIlZbiI2k4HIgfgYq+ZlV08EWHh7gOSCPtuBAahIOFUBGeF+P5KvMtHLMa4dzHs fg1N3fChKkZiJO+Dp1oB/r1YOlAqzu6/gW2QZMJOlW9c9+Bv9eDGQdBueEshhbFmDl TPmVu/taTNCEKCrZVnapH7F9mYGhNziQw3A4g5RUjIrVheryGtCpN4xkGKHQ0WDRUf bgsj5YVtNTzjk5kyRSEM/COP8APwfsSwRBpu6+boHQXZG6Kc7CtJWafed5s3ARx5r2 lbsxQ+dAh1wEg== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 24/53] mtd: nand: denali: remove meaningless writes to read-only registers Date: Thu, 23 Mar 2017 05:07:23 +0900 Message-Id: <1490213273-8571-25-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The write accesses to LOGICAL_PAGE_{DATA,SPARE}_SIZE have no effect because the Denali User's Guide says these registers are read-only. The hardware automatically multiplies the main/spare size by the number of devices and update LOGICAL_PAGE_{DATA,SPARE}_SIZE. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 16 ---------------- 1 file changed, 16 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3da0a0e..5e89709 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -342,8 +342,6 @@ static void get_samsung_nand_para(struct denali_nand_info *denali, static void get_toshiba_nand_para(struct denali_nand_info *denali) { - uint32_t tmp; - /* * Workaround to fix a controller bug which reports a wrong * spare area size for some kind of Toshiba NAND device @@ -351,10 +349,6 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali) if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); - tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * - ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); - iowrite32(tmp, - denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); #if SUPPORT_15BITECC iowrite32(15, denali->flash_reg + ECC_CORRECTION); #elif SUPPORT_8BITECC @@ -366,22 +360,12 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali) static void get_hynix_nand_para(struct denali_nand_info *denali, uint8_t device_id) { - uint32_t main_size, spare_size; - switch (device_id) { case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); - main_size = 4096 * - ioread32(denali->flash_reg + DEVICES_CONNECTED); - spare_size = 224 * - ioread32(denali->flash_reg + DEVICES_CONNECTED); - iowrite32(main_size, - denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); - iowrite32(spare_size, - denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); iowrite32(0, denali->flash_reg + DEVICE_WIDTH); #if SUPPORT_15BITECC iowrite32(15, denali->flash_reg + ECC_CORRECTION); From patchwork Wed Mar 22 20:07:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 95836 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp414231qgd; Wed, 22 Mar 2017 13:14:44 -0700 (PDT) X-Received: by 10.99.178.6 with SMTP id x6mr14514534pge.80.1490213684014; Wed, 22 Mar 2017 13:14:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y7si3003894plb.63.2017.03.22.13.14.43; Wed, 22 Mar 2017 13:14:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbdCVUMi (ORCPT + 11 others); Wed, 22 Mar 2017 16:12:38 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:25350 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751455AbdCVUL7 (ORCPT ); Wed, 22 Mar 2017 16:11:59 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2MK896F029452; Thu, 23 Mar 2017 05:08:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2MK896F029452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490213331; bh=T/lJif2f8AroioE4S7qrTzNgJVD7pAs2Jm30d1tfdko=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S7X0Nt8RriDKwmEt5qht4sa1lpEYHyRcgQtihciTR97S146Utj8lopmohwFrxhU2d i5a0aNXIW82iotgcL1j3U7U0O4oEl7RetL1Wi4mTDGFmLZ8rL2SD9HAdAbp91bAK0u wK30fjxMlvEdWYpSQVK8AkBFYyJiXmOuSBMYJ/SfNf0/NUIB6kCRl1EudK613whbAT mmahOF9GI7h+NWnH1HRZCuQdPuROIFHMMp5oUH5qBsFA8TuRrlKA/gyrGkN7SmNkR/ lh3PDs0BGHx5+bFumbq+TraAHZgCaYakF160jtPWK/vzvHyyjlOMePztCnKkSSsD/L zcB/6NyexQ/MA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: laurent.monat@idquantique.com, thorsten.christiansson@idquantique.com, Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen Subject: [RESEND PATCH v2 25/53] mtd: nand: denali: remove unnecessary writes to ECC_CORRECTION Date: Thu, 23 Mar 2017 05:07:24 +0900 Message-Id: <1490213273-8571-26-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> References: <1490213273-8571-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Because SUPPORT_15BITECC is defined, the following is dead code: #elif SUPPORT_8BITECC iowrite32(8, denali->flash_reg + ECC_CORRECTION); #endif Such ifdefs are useless and unacceptable coding style. These writes are not needed in the first place since ECC_CORRECTION is set up by the nand_init() function. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 15 +-------------- drivers/mtd/nand/denali.h | 3 --- 2 files changed, 1 insertion(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 5e89709..a190cb2 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -62,8 +62,6 @@ MODULE_PARM_DESC(onfi_timing_mode, */ #define CHIP_SELECT_INVALID -1 -#define SUPPORT_8BITECC 1 - /* * This macro divides two integers and rounds fractional values up * to the nearest integer value. @@ -347,14 +345,8 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali) * spare area size for some kind of Toshiba NAND device */ if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && - (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { + (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); -#if SUPPORT_15BITECC - iowrite32(15, denali->flash_reg + ECC_CORRECTION); -#elif SUPPORT_8BITECC - iowrite32(8, denali->flash_reg + ECC_CORRECTION); -#endif - } } static void get_hynix_nand_para(struct denali_nand_info *denali, @@ -367,11 +359,6 @@ static void get_hynix_nand_para(struct denali_nand_info *denali, iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); iowrite32(0, denali->flash_reg + DEVICE_WIDTH); -#if SUPPORT_15BITECC - iowrite32(15, denali->flash_reg + ECC_CORRECTION); -#elif SUPPORT_8BITECC - iowrite32(8, denali->flash_reg + ECC_CORRECTION); -#endif break; default: dev_warn(denali->dev, diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 58a8042..d9232e4 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -303,9 +303,6 @@ #define CLK_X 5 #define CLK_MULTI 4 -#define SUPPORT_15BITECC 1 -#define SUPPORT_8BITECC 1 - #define ONFI_BLOOM_TIME 1 #define MODE5_WORKAROUND 0