From patchwork Tue Dec 8 14:09:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 339739 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3722694jai; Tue, 8 Dec 2020 06:12:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJz6ugGz9O95QoYRr/cQCXKkyG/MKyjfST1d2Adt4dnzY4r3UhahO//GKxpWCpR6LbkJpjv3 X-Received: by 2002:a17:906:1282:: with SMTP id k2mr22787578ejb.554.1607436775740; Tue, 08 Dec 2020 06:12:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607436775; cv=none; d=google.com; s=arc-20160816; b=wMJd4Ay/uVzQnxE4Km2JOVJH0wVLaRdT3CCgQQl7MzS5ZH6G1mAEE9TwI0YGQeC8MG 25KDOmIg2mO4rDJoKiwDUICuaaqe+fWrQhQGTwNzg2cwyj47sKkL3b+sgEH0G6UKf4mJ nN2AFcEOPYmTIuq5TxSbzqL1rwp9wT0/Zj0WcTyyBWFuRCoJNTJWAH+DVzUx5miwYIzj Msan4pgCtQlRvZOcjfyd6/JBnRjM32QuqHxv6p6TgmAPqmjLxeasX8GT5eijWRZzSxxo 2UoagyOiLnXsHGqNj0zjZl2kEF7MxUZvpqnp2C1qUFRjOBFUnNFUaI+irw63K9mIzU2v QR4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E23eTr2Jxh27wQ1+0sxZOBBWYZDbcKVu8F0qLZ0IKIY=; b=zYZy8gESgmcElNNZIFj8WaOAa++/6GsSdMGHAl6AFqclxOvayyRb2OtTnHYmwCAQbQ yLECrF+OnE0PAhU+rv/vaYmRMytTb9lPuPK/n9Uuh76jQqv037yA8WtF3XSop1t4CVAA cNrtEDgerFxDtgjeFfHjYQeZN2byr+gMDLOix20/TF7bVmkf5olMbAPtCeZuIgdSWETr VJ62ptwoAn8NvvWGkF+YNhSyDNzCkacsOOgRO2ad+M7x+MHDLi9rLq2dD/t2HV7akmyR BrUxENeIyGDoB77zxrLiQnKqanOcilB9fY1TVr5kfW2S/rfZlE/+TQfgNkZmkncT8CY2 uS5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w+EI6ugm; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si5275960eju.331.2020.12.08.06.12.54; Tue, 08 Dec 2020 06:12:55 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w+EI6ugm; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729651AbgLHOLm (ORCPT + 6 others); Tue, 8 Dec 2020 09:11:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729570AbgLHOLl (ORCPT ); Tue, 8 Dec 2020 09:11:41 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D4F3C0617A7 for ; Tue, 8 Dec 2020 06:10:41 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id a1so18242088ljq.3 for ; Tue, 08 Dec 2020 06:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E23eTr2Jxh27wQ1+0sxZOBBWYZDbcKVu8F0qLZ0IKIY=; b=w+EI6ugmrY3V1qVcvQiDjc626zqEFOAHVMhueu9h8zbQ7K0JTHdyZUPBIVwX4Lo135 86QGht3BE+LF4s7El0Bw1ogw8ltcdsiy2YsmNKX3jXNBYjTfZyP0tX+i2xGFNT1TYLrC DvIsHotgNnJKCa8JDfn/9BOE/uQAsflhevb/Qnv6b1REwN2FxD+2G8TqKd7VDaXSrPxl vQWq3jN4vfDP2fqsuoYJDyFWMF8ABarbZoQndfVw2ZQgdfi+2GEAMWqw//342x2oC3PQ rZyhslbNS1eFuLjfz4+xg4ecrN45R/WnyZJ8wzfuQ1ETcMz4lBVPcFvuI4iH37rLUrZR wh6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E23eTr2Jxh27wQ1+0sxZOBBWYZDbcKVu8F0qLZ0IKIY=; b=DXmgBJQMc8if9tW3G6AMoSrytvPh+2HlQAWwFp5PvfopqctnmdUnbUWHKC+I2f4vcC 1EXC+We9g7liLLMwEgmWGIvso3Cfojj7mgbFOUys8OpyvGXMNLifS6ie1IN1cLetjjGu rjQQv52rqdThTO+lXjZTkQCmpSHJLR0CLEjlhKinT+QOmN5nZGObmIrwP9Hgtk5ao+P3 krLPKy91Yr0c4yvPg94/bIyXj8LXDZfGJZhCMPq5VkegPnLJTnbnHf8JCHZO7JOPJ2Te N6xzSWG9q/C9xVpYUOMUgA+adHzSCpSw7rk/nP6W6vDmqAozdvEFbbFpBdbNwMo14dlI s6LA== X-Gm-Message-State: AOAM532WjutD+7RiX/aXP35s4mkCpgaJdiDqbqibyrqRqhDKGjYeCbdB kxjRD9jhuCU8kZ+kbcwUwreCWA== X-Received: by 2002:a2e:87d5:: with SMTP id v21mr10915676ljj.442.1607436639937; Tue, 08 Dec 2020 06:10:39 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h23sm417017ljh.115.2020.12.08.06.10.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2020 06:10:39 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v4 1/6] dt-bindings: remoteproc: Add binding doc for PRU cores in the PRU-ICSS Date: Tue, 8 Dec 2020 15:09:57 +0100 Message-Id: <20201208141002.17777-2-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> References: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS or simply PRUSS) on various TI SoCs consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. The K3 AM65x amd J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG IP on AM65x SoCs has two PRU cores, two auxiliary custom PRU cores called Real Time Units (RTUs). The K3 AM65x SR2.0 and J721E SoCs have a revised version of the ICSSG IP, and include two additional custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs). This patch adds the bindings for these PRU cores. The binding covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; Keystone 2 architecture based 66AK2G SoC; and the K3 architecture based SoCs - AM65x and J721E. The Davinci based OMAPL138 SoCs will be covered in a future patch. Co-developed-by: Roger Quadros Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v3->v4: - no changes v2->v3: - no changes v1->v2: - fix below yamllint warnings: ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:37:6: [warning] wrong indentation: expected 6 but found 5 (indentation) ./Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml:92:2: [warning] wrong indentation: expected 2 but found 1 (indentation) --- .../bindings/remoteproc/ti,pru-rproc.yaml | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml -- 2.29.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml new file mode 100644 index 000000000000..63071eef1632 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Programmable Realtime Unit (PRU) cores + +maintainers: + - Suman Anna + +description: | + Each Programmable Real-Time Unit and Industrial Communication Subsystem + (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called + Programmable Real-Time Units (PRUs), each represented by a node. Each PRU + core has a dedicated Instruction RAM, Control and Debug register sets, and + use the Data RAMs present within the PRU-ICSS for code execution. + + The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary + PRU cores called RTUs with slightly different IP integration. The K3 SoCs + containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two + auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU + or Tx_PRU core can also be used independently like a PRU, or alongside a + corresponding PRU core to provide/implement auxiliary functionality/support. + + Each PRU, RTU or Tx_PRU core node should be defined as a child node of the + corresponding PRU-ICSS node. Each node can optionally be rendered inactive by + using the standard DT string property, "status". + + Please see the overall PRU-ICSS bindings document for additional details + including a complete example, + Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml + +properties: + compatible: + enum: + - ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only) + - ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only) + - ti,am5728-pru # for AM57xx SoC family + - ti,k2g-pru # for 66AK2G SoC family + - ti,am654-pru # for PRUs in K3 AM65x SoC family + - ti,am654-rtu # for RTUs in K3 AM65x SoC family + - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs + - ti,j721e-pru # for PRUs in K3 J721E SoC family + - ti,j721e-rtu # for RTUs in K3 J721E SoC family + - ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family + + reg: + items: + - description: Address and Size of the PRU Instruction RAM + - description: Address and Size of the PRU CTRL sub-module registers + - description: Address and Size of the PRU Debug sub-module registers + + reg-names: + items: + - const: iram + - const: control + - const: debug + + firmware-name: + description: | + Should contain the name of the default firmware image + file located on the firmware search path. + +if: + properties: + compatible: + enum: + - ti,am654-rtu + - ti,j721e-rtu +then: + properties: + $nodename: + pattern: "^rtu@[0-9a-f]+$" +else: + if: + properties: + compatible: + enum: + - ti,am654-tx-pru + - ti,j721e-tx-pru + then: + properties: + $nodename: + pattern: "^txpru@[0-9a-f]+" + else: + properties: + $nodename: + pattern: "^pru@[0-9a-f]+$" + +required: + - compatible + - reg + - reg-names + - firmware-name + +additionalProperties: false + +examples: + - | + /* AM33xx PRU-ICSS */ + pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc-pruss", "ti,sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x300000 0x80000>; + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + }; + }; + + - | + /* AM65x SR2.0 ICSSG */ + #include + + icssg0: icssg@b000000 { + compatible = "ti,am654-icssg"; + reg = <0xb000000 0x80000>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000000 0x80000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pru0_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_1-fw"; + }; + }; From patchwork Tue Dec 8 14:09:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 339740 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3722714jai; Tue, 8 Dec 2020 06:12:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJwlIWFV0AAQJHCEv8zPuZhgiZ5wbBHFjpjAJHoouHY5zi6EnzzZJA3a32Vhj88fHnMom0cz X-Received: by 2002:a17:906:7a18:: with SMTP id d24mr23450671ejo.324.1607436778665; Tue, 08 Dec 2020 06:12:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607436778; cv=none; d=google.com; s=arc-20160816; b=A6Vsp7j1PRMdjUJuXvh55wnH5srBVpTpYlwopkNVBJpF6rgALXtv+J/Hk3S4xoU2IE YL0/+MObdS7Rw9iPJGsQ6jhLjHHrXDqDZ+tMSGWVp+I3UzvX/sJEioXez3zbrpa28qjO 5Y8rjqDOEOntvbJ8Tl2CvPBwdwL5Xwb+qPHgX9MChxYiiSCP82oV9PFyZJMT0R+GrgsF 0Ss7gVJHP2wH3bEpAXsNrX+Hj4LZoa88rfcAs+b4hlVGo11PvNrnsb6+mW9Ag6KpeGRJ cUiKCUf4HXW4m4F4YeKSz6XVIy5r9mXcsHOU2aP721Otl4/uWOy7PqzBJR7s0FRUeAii +fqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uWuPHQBJYGT5qGWC4gn24eFk6bpKJ9aYZMm0zFyUADA=; b=VA7/2Tw0Oh3hvzmG9KQj3uZ4wJyjJ0ZPt/BkSLbU1gZJu/ElZNhI3RS2MRNg3Q9xfM tZCyecdkF7Q+8qRaZSWMNIhL6waHThK2TqrKdekws/9s+e1w30P6o59rj6twWjwDz27a Zvv7J2g5ntjooabMeQmo2FjciKqpYaVTp/IZZpcXdGxEx/zkXRVwvE1wZZ78jaKF6r1g X79c1A1td9GaKzZUnWYhEueNO/94PeGEQkIgaffoWKxs8rSsBxcFbdqfjsF1FEpCQZyq 5lVZNNxB4A+ncR/DOZlfweWLGwWZo80vE471Cug4+md7g9WEJlN0JSXl7lBVfDq/loSS Q68w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V6h3dlkO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si5275960eju.331.2020.12.08.06.12.58; Tue, 08 Dec 2020 06:12:58 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V6h3dlkO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729685AbgLHOL5 (ORCPT + 6 others); Tue, 8 Dec 2020 09:11:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729265AbgLHOL4 (ORCPT ); Tue, 8 Dec 2020 09:11:56 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BD75C0611CE for ; Tue, 8 Dec 2020 06:10:44 -0800 (PST) Received: by mail-lj1-x235.google.com with SMTP id s11so10880144ljp.4 for ; Tue, 08 Dec 2020 06:10:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uWuPHQBJYGT5qGWC4gn24eFk6bpKJ9aYZMm0zFyUADA=; b=V6h3dlkOTuWhxG2O96sMaBTGQFSKTmrBaaGudoDL45stb1gzPlpJnIJD3YKrEAKeYp tWBN37LEOk+4ymUV4a4jmXH5UBy9o9NBY84/u8N5z3eU/MiuYbpdCL6Umg67lb7SJLGG ZYL/TWZmDAX4fRUYIdSIaObXuuqpAHNkTDHa9LK21nwWKbBap3QhNe/H8CMJxBvzoVzM gAImOHX4QViOEUwQq9mGM5dso729a39+ZXGbJPWigsRxjhlRJv4XjfJaCHk+lmfDAfeF CSods8FEb84txLEE1IeWRczAuMsnu3fLq+a5fFyJaVUXXvtXWOnESBUFpnDc46NcWQxv vm2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uWuPHQBJYGT5qGWC4gn24eFk6bpKJ9aYZMm0zFyUADA=; b=cPrbJUS6QJiFpNHCBaFDCoZvDrTiFYVNuK5XDEA8soBf4k2xZVQnueadDi1B/Vlghx 5AqUugDpE4u3RNRSmLuZ5WfXXpeiLJX+gSkLItI6hjgxa1aYzut21bVMXmYBpKW9zL7H tSRIImK6/wBx/TMnXSDXXlx0g9GQW5F5IRIF6+HwwJDbbGJKPLjPkEo9Kb/7Is6yCp0R 6WdTZ2ngXojlEf9JFttvqcjya0vuXEwr7pIF0R3btdz6IRifX9+tIQICuEVZiHa+flME V+Esb17EMBgOo1WJCmBgeT7kd1WfzrSkGHk75zpJIkuvPegYKeFq7R2AujCNMixmxiHF 7t5A== X-Gm-Message-State: AOAM5305MyfY3pcY+LxiGE5KX8s+zJZOKChg8I2otIYZL12qGg2tZHLH hEd4pgaARKM5eqf62oUDhzdiJA== X-Received: by 2002:a2e:b949:: with SMTP id 9mr5483079ljs.376.1607436642826; Tue, 08 Dec 2020 06:10:42 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h23sm417017ljh.115.2020.12.08.06.10.41 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2020 06:10:42 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v4 3/6] remoteproc: pru: Add support for PRU specific interrupt configuration Date: Tue, 8 Dec 2020 15:09:59 +0100 Message-Id: <20201208141002.17777-4-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> References: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The firmware blob can contain optional ELF sections: .resource_table section and .pru_irq_map one. The second one contains the PRUSS interrupt mapping description, which needs to be setup before powering on the PRU core. To avoid RAM wastage this ELF section is not mapped to any ELF segment (by the firmware linker) and therefore is not loaded to PRU memory. The PRU interrupt configuration is handled within the PRUSS INTC irqchip driver and leverages the system events to interrupt channels and host interrupts mapping configuration. Relevant irq routing information is passed through a special .pru_irq_map ELF section (for interrupts routed to and used by PRU cores) or via the PRU application's device tree node (for interrupts routed to and used by the main CPU). The mappings are currently programmed during the booting/shutdown of the PRU. The interrupt configuration passed through .pru_irq_map ELF section is optional. It varies on specific firmware functionality and therefore have to be unwinded during PRU stop and performed again during PRU start. Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk --- v3->v4: - Use sizeof(unsigned int) instead of sizeof(int) for kcalloc in pru_handle_intrmap(). v2->v3: Address Mathieu comments: - Because irq_create_fwspec_mapping() returns an unsigned int, convert mapped_irq type to 'unsigned int *'. Due to this change update relevant error path. - Since the num_evts is u8 value and can't be negative drop 'rsc->num_evts < 0' check. Fix checkpatch --strict warning: CHECK: Alignment should match open parenthesis #163: FILE: drivers/remoteproc/pru_rproc.c:165: + dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", + i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); v1->v2: Address Suman comments: - Rework pru_rproc_find_interrupt_map() style: get rid of generic ELF helpers macros usage and stick with elf32_* related structs instead (in order to be consistent with pru_rproc_load_elf_segments() style). - Improve comments and dev_err msgs in pru_rproc_find_interrupt_map(). - Use u8 instead of ssize_t for evt_count. --- drivers/remoteproc/pru_rproc.c | 181 +++++++++++++++++++++++++++++++++ drivers/remoteproc/pru_rproc.h | 46 +++++++++ 2 files changed, 227 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.h -- 2.29.0 Reviewed-by: Mathieu Poirier diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index d33392bbd8af..72e64d15f0dc 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,13 +11,16 @@ */ #include +#include #include #include +#include #include #include #include "remoteproc_internal.h" #include "remoteproc_elf_helpers.h" +#include "pru_rproc.h" /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 @@ -42,6 +45,8 @@ #define PRU_SDRAM_DA 0x2000 /* Secondary Data RAM */ #define PRU_SHRDRAM_DA 0x10000 /* Shared Data RAM */ +#define MAX_PRU_SYS_EVENTS 160 + /** * enum pru_iomem - PRU core memory/register range identifiers * @@ -65,6 +70,10 @@ enum pru_iomem { * @rproc: remoteproc pointer for this PRU core * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading + * @mapped_irq: virtual interrupt numbers of created fw specific mapping + * @pru_interrupt_map: pointer to interrupt mapping description (firmware) + * @pru_interrupt_map_sz: pru_interrupt_map size + * @evt_count: number of mapped events */ struct pru_rproc { int id; @@ -73,6 +82,10 @@ struct pru_rproc { struct rproc *rproc; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; + unsigned int *mapped_irq; + struct pru_irq_rsc *pru_interrupt_map; + size_t pru_interrupt_map_sz; + u8 evt_count; }; static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg) @@ -86,15 +99,108 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static void pru_dispose_irq_mapping(struct pru_rproc *pru) +{ + while (pru->evt_count--) { + if (pru->mapped_irq[pru->evt_count] > 0) + irq_dispose_mapping(pru->mapped_irq[pru->evt_count]); + } + + kfree(pru->mapped_irq); +} + +/* + * Parse the custom PRU interrupt map resource and configure the INTC + * appropriately. + */ +static int pru_handle_intrmap(struct rproc *rproc) +{ + struct device *dev = rproc->dev.parent; + struct pru_rproc *pru = rproc->priv; + struct pru_irq_rsc *rsc = pru->pru_interrupt_map; + struct irq_fwspec fwspec; + struct device_node *irq_parent; + int i, ret = 0; + + /* not having pru_interrupt_map is not an error */ + if (!rsc) + return 0; + + /* currently supporting only type 0 */ + if (rsc->type != 0) { + dev_err(dev, "unsupported rsc type: %d\n", rsc->type); + return -EINVAL; + } + + if (rsc->num_evts > MAX_PRU_SYS_EVENTS) + return -EINVAL; + + if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) != + pru->pru_interrupt_map_sz) + return -EINVAL; + + pru->evt_count = rsc->num_evts; + pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int), + GFP_KERNEL); + if (!pru->mapped_irq) + return -ENOMEM; + + /* + * parse and fill in system event to interrupt channel and + * channel-to-host mapping + */ + irq_parent = of_irq_find_parent(pru->dev->of_node); + if (!irq_parent) { + kfree(pru->mapped_irq); + return -ENODEV; + } + + fwspec.fwnode = of_node_to_fwnode(irq_parent); + fwspec.param_count = 3; + for (i = 0; i < pru->evt_count; i++) { + fwspec.param[0] = rsc->pru_intc_map[i].event; + fwspec.param[1] = rsc->pru_intc_map[i].chnl; + fwspec.param[2] = rsc->pru_intc_map[i].host; + + dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n", + i, fwspec.param[0], fwspec.param[1], fwspec.param[2]); + + pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec); + if (!pru->mapped_irq[i]) { + dev_err(dev, "failed to get virq\n"); + ret = pru->mapped_irq[i]; + goto map_fail; + } + } + + return ret; + +map_fail: + pru_dispose_irq_mapping(pru); + + return ret; +} + static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; u32 val; + int ret; dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", pru->id, (rproc->bootaddr >> 2)); + ret = pru_handle_intrmap(rproc); + /* + * reset references to pru interrupt map - they will stop being valid + * after rproc_start returns + */ + pru->pru_interrupt_map = NULL; + pru->pru_interrupt_map_sz = 0; + if (ret) + return ret; + val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16); pru_control_write_reg(pru, PRU_CTRL_CTRL, val); @@ -113,6 +219,10 @@ static int pru_rproc_stop(struct rproc *rproc) val &= ~CTRL_CTRL_EN; pru_control_write_reg(pru, PRU_CTRL_CTRL, val); + /* dispose irq mapping - new firmware can provide new mapping */ + if (pru->mapped_irq) + pru_dispose_irq_mapping(pru); + return 0; } @@ -273,12 +383,70 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) return ret; } +static const void * +pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw) +{ + struct elf32_shdr *shdr, *name_table_shdr; + const char *name_table; + const u8 *elf_data = fw->data; + struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data; + u16 shnum = ehdr->e_shnum; + u16 shstrndx = ehdr->e_shstrndx; + int i; + + /* first, get the section header */ + shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff); + /* compute name table section header entry in shdr array */ + name_table_shdr = shdr + shstrndx; + /* finally, compute the name table section address in elf */ + name_table = elf_data + name_table_shdr->sh_offset; + + for (i = 0; i < shnum; i++, shdr++) { + u32 size = shdr->sh_size; + u32 offset = shdr->sh_offset; + u32 name = shdr->sh_name; + + if (strcmp(name_table + name, ".pru_irq_map")) + continue; + + /* make sure we have the entire irq map */ + if (offset + size > fw->size || offset + size < size) { + dev_err(dev, ".pru_irq_map section truncated\n"); + return ERR_PTR(-EINVAL); + } + + /* make sure irq map has at least the header */ + if (sizeof(struct pru_irq_rsc) > size) { + dev_err(dev, "header-less .pru_irq_map section\n"); + return ERR_PTR(-EINVAL); + } + + return shdr; + } + + dev_dbg(dev, "no .pru_irq_map section found for this fw\n"); + + return NULL; +} + /* * Use a custom parse_fw callback function for dealing with PRU firmware * specific sections. + * + * The firmware blob can contain optional ELF sections: .resource_table section + * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping + * description, which needs to be setup before powering on the PRU core. To + * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the + * firmware linker) and therefore is not loaded to PRU memory. */ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) { + struct device *dev = &rproc->dev; + struct pru_rproc *pru = rproc->priv; + const u8 *elf_data = fw->data; + const void *shdr; + u8 class = fw_elf_get_class(fw); + u64 sh_offset; int ret; /* load optional rsc table */ @@ -288,6 +456,19 @@ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) else if (ret) return ret; + /* find .pru_interrupt_map section, not having it is not an error */ + shdr = pru_rproc_find_interrupt_map(dev, fw); + if (IS_ERR(shdr)) + return PTR_ERR(shdr); + + if (!shdr) + return 0; + + /* preserve pointer to PRU interrupt map together with it size */ + sh_offset = elf_shdr_get_sh_offset(class, shdr); + pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset); + pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr); + return 0; } diff --git a/drivers/remoteproc/pru_rproc.h b/drivers/remoteproc/pru_rproc.h new file mode 100644 index 000000000000..8ee9c3171610 --- /dev/null +++ b/drivers/remoteproc/pru_rproc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * PRUSS Remote Processor specific types + * + * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Suman Anna + */ + +#ifndef _PRU_RPROC_H_ +#define _PRU_RPROC_H_ + +/** + * struct pruss_int_map - PRU system events _to_ channel and host mapping + * @event: number of the system event + * @chnl: channel number assigned to a given @event + * @host: host number assigned to a given @chnl + * + * PRU system events are mapped to channels, and these channels are mapped + * to host interrupts. Events can be mapped to channels in a one-to-one or + * many-to-one ratio (multiple events per channel), and channels can be + * mapped to host interrupts in a one-to-one or many-to-one ratio (multiple + * channels per interrupt). + */ +struct pruss_int_map { + u8 event; + u8 chnl; + u8 host; +}; + +/** + * struct pru_irq_rsc - PRU firmware section header for IRQ data + * @type: resource type + * @num_evts: number of described events + * @pru_intc_map: PRU interrupt routing description + * + * The PRU firmware blob can contain optional .pru_irq_map ELF section, which + * provides the PRUSS interrupt mapping description. The pru_irq_rsc struct + * describes resource entry format. + */ +struct pru_irq_rsc { + u8 type; + u8 num_evts; + struct pruss_int_map pru_intc_map[]; +} __packed; + +#endif /* _PRU_RPROC_H_ */ From patchwork Tue Dec 8 14:10:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 339863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CD8AC433FE for ; Tue, 8 Dec 2020 14:12:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 46CEE23A77 for ; Tue, 8 Dec 2020 14:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729497AbgLHOMM (ORCPT ); Tue, 8 Dec 2020 09:12:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728758AbgLHOMM (ORCPT ); Tue, 8 Dec 2020 09:12:12 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F145DC0619D4 for ; Tue, 8 Dec 2020 06:10:45 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id b4so15818627lfo.6 for ; Tue, 08 Dec 2020 06:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lNDBikXll/RoG1bzAS6wZydhLpoIoInZqBARx/07aaA=; b=zSNO9Ll0Oe4UWAbkCJf/8THXasWEpNEj6OqYFUkkGpAAKHQIbo9gZIP7G4WZJyC8c4 0EjcgeJCl8DeHN+/tWCNrRSCBViNXZpmUugHJftiIisfK5BuiXlOTAmUPWYz4frprHrw urXHis94TSNekBNjBFPx4Z7xy1rgsaLcWmSLFHjVxFinKrEgFVNZawSG+bXn39VFZEZ3 XjJ2GXzeDkoMrNV5PvBi2KspB5YN4lJPrZdboiatdhZdKX+Iu8lSMiUzdWG9f8OPTFNG 4/Vjnkv8Jcie00mZ16QASRjlew4JQgh5pdO4Jiy2qC19nTTZXiAutHNbu3lA4o86yyEg tnsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lNDBikXll/RoG1bzAS6wZydhLpoIoInZqBARx/07aaA=; b=uMEMZPpW43N46j5eLwdAmDnLFSmsAB84hJD8A3g3p97lEj4d6nJj9C0GTIHwnJHylw NDdH10ZNg14gFJU9MTNpZ+3uRujI7I8AEcDyx3jUPGueTRLf32hy5aR70+LGH7HDMIm9 zL5q3JzS/Ix90siXsHz6vT0Xuv2d4mPyeBS5bfPckO5+D7EnfFDwJIozDQKzWfORzJgA PePchb32n1LuXNWu8/qJooMRKkGZ7hKQbeGilhC3uoN7hciigsxTEtbyhfqw6EhRJxsO jQI82Cj7Dwt7pHeYI9wlfrK6oMG7Gnp+qErEfOo4MGty4ny1MoSxOT8FRY8AdlRy5FNW uIig== X-Gm-Message-State: AOAM530SGY+facqarcCu9eqDHEGEA50ndvuWSH+tiK2HgGFxJEt8E1hm J9g+PIs2HLVNeSxznGiix5sRRg== X-Google-Smtp-Source: ABdhPJwCqkm5G/LTluQPmYRBZDqr429xkC+vMv007TiHQw8F+qoJ1zstWrYNmbT10w6lZKO+4fIRDQ== X-Received: by 2002:a05:6512:3047:: with SMTP id b7mr9716612lfb.210.1607436644285; Tue, 08 Dec 2020 06:10:44 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h23sm417017ljh.115.2020.12.08.06.10.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2020 06:10:43 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v4 4/6] remoteproc: pru: Add pru-specific debugfs support Date: Tue, 8 Dec 2020 15:10:00 +0100 Message-Id: <20201208141002.17777-5-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> References: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The remoteproc core creates certain standard debugfs entries, that does not give a whole lot of useful information for the PRUs. The PRU remoteproc driver is enhanced to add additional debugfs entries for PRU. These will be auto-cleaned up when the parent rproc debug directory is removed. The enhanced debugfs support adds two new entries: 'regs' and 'single_step'. The 'regs' dumps out the useful CTRL sub-module registers as well as each of the 32 GPREGs and CT_REGs registers. The GPREGs and CT_REGs though are printed only when the PRU is halted and accessible as per the IP design. The 'single_step' utilizes the single-step execution of the PRU cores. Writing a non-zero value performs a single step, and a zero value restores the PRU to execute in the same mode as the mode before the first single step. (note: if the PRU is halted because of a halt instruction, then no change occurs). Logic for setting the PC and jumping over a halt instruction shall be added in the future. Signed-off-by: Suman Anna Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v3->v4: - No changes. v2->v3: Address Mathieu comments: - Remove extra line before DEFINE_SHOW_ATTRIBUTE(). - Add Reviewed-by: tag. --- drivers/remoteproc/pru_rproc.c | 136 +++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 72e64d15f0dc..59240fd82f56 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -25,6 +26,13 @@ /* PRU_ICSS_PRU_CTRL registers */ #define PRU_CTRL_CTRL 0x0000 #define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C /* CTRL register bit-fields */ #define CTRL_CTRL_SOFT_RST_N BIT(0) @@ -34,6 +42,10 @@ #define CTRL_CTRL_SINGLE_STEP BIT(8) #define CTRL_CTRL_RUNSTATE BIT(15) +/* PRU_ICSS_PRU_DEBUG registers */ +#define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) +#define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) + /* PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 @@ -73,6 +85,8 @@ enum pru_iomem { * @mapped_irq: virtual interrupt numbers of created fw specific mapping * @pru_interrupt_map: pointer to interrupt mapping description (firmware) * @pru_interrupt_map_sz: pru_interrupt_map size + * @dbg_single_step: debug state variable to set PRU into single step mode + * @dbg_continuous: debug state variable to restore PRU execution mode * @evt_count: number of mapped events */ struct pru_rproc { @@ -85,6 +99,8 @@ struct pru_rproc { unsigned int *mapped_irq; struct pru_irq_rsc *pru_interrupt_map; size_t pru_interrupt_map_sz; + u32 dbg_single_step; + u32 dbg_continuous; u8 evt_count; }; @@ -99,6 +115,124 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) +{ + return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); +} + +static int regs_show(struct seq_file *s, void *data) +{ + struct rproc *rproc = s->private; + struct pru_rproc *pru = rproc->priv; + int i, nregs = 32; + u32 pru_sts; + int pru_is_running; + + seq_puts(s, "============== Control Registers ==============\n"); + seq_printf(s, "CTRL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTRL)); + pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS); + seq_printf(s, "STS (PC) := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2); + seq_printf(s, "WAKEUP_EN := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN)); + seq_printf(s, "CYCLE := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CYCLE)); + seq_printf(s, "STALL := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_STALL)); + seq_printf(s, "CTBIR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR0)); + seq_printf(s, "CTBIR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTBIR1)); + seq_printf(s, "CTPPR0 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR0)); + seq_printf(s, "CTPPR1 := 0x%08x\n", + pru_control_read_reg(pru, PRU_CTRL_CTPPR1)); + + seq_puts(s, "=============== Debug Registers ===============\n"); + pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) & + CTRL_CTRL_RUNSTATE; + if (pru_is_running) { + seq_puts(s, "PRU is executing, cannot print/access debug registers.\n"); + return 0; + } + + for (i = 0; i < nregs; i++) { + seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n", + i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)), + i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i))); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(regs); + +/* + * Control PRU single-step mode + * + * This is a debug helper function used for controlling the single-step + * mode of the PRU. The PRU Debug registers are not accessible when the + * PRU is in RUNNING state. + * + * Writing a non-zero value sets the PRU into single-step mode irrespective + * of its previous state. The PRU mode is saved only on the first set into + * a single-step mode. Writing a zero value will restore the PRU into its + * original mode. + */ +static int pru_rproc_debug_ss_set(void *data, u64 val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + u32 reg_val; + + val = val ? 1 : 0; + if (!val && !pru->dbg_single_step) + return 0; + + reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL); + + if (val && !pru->dbg_single_step) + pru->dbg_continuous = reg_val; + + if (val) + reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN; + else + reg_val = pru->dbg_continuous; + + pru->dbg_single_step = val; + pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val); + + return 0; +} + +static int pru_rproc_debug_ss_get(void *data, u64 *val) +{ + struct rproc *rproc = data; + struct pru_rproc *pru = rproc->priv; + + *val = pru->dbg_single_step; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get, + pru_rproc_debug_ss_set, "%llu\n"); + +/* + * Create PRU-specific debugfs entries + * + * The entries are created only if the parent remoteproc debugfs directory + * exists, and will be cleaned up by the remoteproc core. + */ +static void pru_rproc_create_debug_entries(struct rproc *rproc) +{ + if (!rproc->dbg_dir) + return; + + debugfs_create_file("regs", 0400, rproc->dbg_dir, + rproc, ®s_fops); + debugfs_create_file("single_step", 0600, rproc->dbg_dir, + rproc, &pru_rproc_debug_ss_fops); +} + static void pru_dispose_irq_mapping(struct pru_rproc *pru) { while (pru->evt_count--) { @@ -572,6 +706,8 @@ static int pru_rproc_probe(struct platform_device *pdev) return ret; } + pru_rproc_create_debug_entries(rproc); + dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np); return 0; From patchwork Tue Dec 8 14:10:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 339744 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3722845jai; Tue, 8 Dec 2020 06:13:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJzNAIst0FvGptc3HnKtGA8NPKJxOCCxMA75SGNUpEsxZsTqHlV5ZfC0ZKNtwWCdOddhNJnS X-Received: by 2002:a17:907:961b:: with SMTP id gb27mr22865556ejc.313.1607436787153; Tue, 08 Dec 2020 06:13:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607436787; cv=none; d=google.com; s=arc-20160816; b=AaZwaPThSN0iALjwp0UaIvGDH7MxuKaklC0UaxHxh3b+fm59r5GrQBlS0bYpSNDdiF AMk3sInQySeJlsixgmx9HI2gAQUQuO/t+G35zMxplgCLJpNKNnirBBj04QLdcfzEio/j EqDgjry9nQ/QL9KmpC2wtTWGpK3HuCCSJ5PiV1NWJtjuF/WBJavThC2100/wVBzMkv37 tj7FE9GlDBQ7WnqnVby0OQkcAYMmZ17c3wOCw+T/QergpI1i4sXtHYec8CSfB1DGQGWt rmNa8PEZYhDgt7lNjhqy05cKgGgGkEIQxTfSevqxIgpMeen1o04DO/0wtel1azKVELiE T6fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YrmPgaht3F54ekOZjpnxRQJRgPSdJ6wC/G9opJrBVN8=; b=hMQ+z821wBH/AI+MhkxIxHG1pcAwjPQzm/7Mexo/OrvvL1MmHNlJ2OzFerLBeQyaS0 hBxFtPcy1N2S9hSwZdvnlBBfzA6R7/vj2GldS2ChJrXAJ6eb0iwPN+g9yCoB9o3RHq4R OM63GwyRRxrDIgIRkcUwJOx4r3v1dI11e+6HOcoqC8JVpkR9MZENRbNHwhTYGErWdtk7 UgM5iWux+lUSR5WIhlJeeTtMKVzRy/fNKWyMeNuDtoDHTq6DqUgpu0d8OcjyFfStemhG 8REgOABb/7asRO/YLWR8L3u2RWKJhr0yYUG3bWez8GlEuCmwIDEnxSpH/Epa3Kh8ho2l 78pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=inXM++kM; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si5275960eju.331.2020.12.08.06.13.06; Tue, 08 Dec 2020 06:13:07 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=inXM++kM; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729773AbgLHOMW (ORCPT + 6 others); Tue, 8 Dec 2020 09:12:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729753AbgLHOMW (ORCPT ); Tue, 8 Dec 2020 09:12:22 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6F3AC0619D8 for ; Tue, 8 Dec 2020 06:10:48 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id l11so23466832lfg.0 for ; Tue, 08 Dec 2020 06:10:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YrmPgaht3F54ekOZjpnxRQJRgPSdJ6wC/G9opJrBVN8=; b=inXM++kM5P/h1IHNIRmF9OWWtUw5y4lowenOLGJkshRcFvttw3Wc3nWDC6MYg0Bg+j 6qMf3UDd5YvznisJaBllC0lq9SVn4CO3IqGkMCDWwvNGOpfkXwE0AbNiuVdr9Qiu/ffE 5vWuF0iFRW0QDIvst4n+UZq3QkCEROfWaLSU1Zv4IARqs8ubxet5rn3ndcVh9mIUuvTb MswU9PFuUCV/rZB4wtvL6r5VCCrihH3v2C9DJhMBi4U5PyciG5TvybuRDjp+fpSEDCIg sETzUz1eCovTPMWCKaeYdUsQyOv8HnaawWVuE34RHBGX9J0Uy3e1ARD7z64/ftjYbpun hQEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YrmPgaht3F54ekOZjpnxRQJRgPSdJ6wC/G9opJrBVN8=; b=sxOUhz8X81Z6g65BiPql3/2TvUh2ORHg3pHkEkJYW+4FgGsOrW+soMARnYeJzbk/PG 9fBZXOefGPzZs9OgQ4PhGTNjpWrejvYisFDDcphGIkI0ogmPaLJiNx3KolOrCRaSgfrL 5AkA/8F78ezhO49s3oUQ234We+d1VlJUs2ICia+7BZOUWQiCIFOxmRxzSfJ5xZHQ6PNz yz7fjaNJIAIExrMiQzenNWwQkeSGXV4X5+N5DVF7HGrA2cPuIcXBs0U9qiSuQBdhgGgR ZT9CqX4WRmHeaRzWe0K4arDefQQQjYelL2WJdjivXbg4y0V4IO0Lr89Q175/c507x4Rn HN7g== X-Gm-Message-State: AOAM531/gF1JJ80xrdh7kZDD1ZmTRNl8/m1JGd3lwWoPH/n+JLifMgwu kCdjy4vIu85wTPee2rx2mOw4Rg== X-Received: by 2002:a19:f80a:: with SMTP id a10mr3890840lff.36.1607436645928; Tue, 08 Dec 2020 06:10:45 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h23sm417017ljh.115.2020.12.08.06.10.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2020 06:10:45 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v4 5/6] remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs Date: Tue, 8 Dec 2020 15:10:01 +0100 Message-Id: <20201208141002.17777-6-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> References: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. Enhance the existing PRU remoteproc driver to support these new PRU, RTU and Tx PRU cores by using specific compatibles. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. The PRU remoteproc driver has to be specifically modified to use a custom memcpy function within its ELF loader implementation for these new cores in order to overcome a limitation with copying data into each of the core's IRAM memories. These memory ports support only 4-byte writes, and any sub-word order byte writes clear out the remaining bytes other than the bytes being written within the containing word. The default ARM64 memcpy also cannot be used as it throws an exception when the preferred 8-byte copy operation is attempted. This choice is made by using a state flag that is set only on K3 SoCs. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v3->v4: - No changes. v2->v3: Address Mathieu comments: - Change type of some local variable in pru_rproc_memcpy from 'int *' to 'u32 *'. At the occasion use size_t for 'size' inside mentioned function. - Add Reviewed-by: tag. v1->v2: - Update documentation of pru_rproc_memcpy() according to Suman comments. - Update documentation of is_k3 flag. --- drivers/remoteproc/pru_rproc.c | 140 ++++++++++++++++++++++++++++++--- 1 file changed, 131 insertions(+), 9 deletions(-) -- 2.29.0 diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 59240fd82f56..421ebbc1c02d 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -46,10 +46,14 @@ #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) -/* PRU Core IRAM address masks */ +/* PRU/RTU/Tx_PRU Core IRAM address masks */ #define PRU_IRAM_ADDR_MASK 0x3ffff #define PRU0_IRAM_ADDR_MASK 0x34000 #define PRU1_IRAM_ADDR_MASK 0x38000 +#define RTU0_IRAM_ADDR_MASK 0x4000 +#define RTU1_IRAM_ADDR_MASK 0x6000 +#define TX_PRU0_IRAM_ADDR_MASK 0xa000 +#define TX_PRU1_IRAM_ADDR_MASK 0xc000 /* PRU device addresses for various type of PRU RAMs */ #define PRU_IRAM_DA 0 /* Instruction RAM */ @@ -74,12 +78,38 @@ enum pru_iomem { PRU_IOMEM_MAX, }; +/** + * enum pru_type - PRU core type identifier + * + * @PRU_TYPE_PRU: Programmable Real-time Unit + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit + * @PRU_TYPE_MAX: just keep this one at the end + */ +enum pru_type { + PRU_TYPE_PRU = 0, + PRU_TYPE_RTU, + PRU_TYPE_TX_PRU, + PRU_TYPE_MAX, +}; + +/** + * struct pru_private_data - device data for a PRU core + * @type: type of the PRU core (PRU, RTU, Tx_PRU) + * @is_k3: flag used to identify the need for special load handling + */ +struct pru_private_data { + enum pru_type type; + unsigned int is_k3 : 1; +}; + /** * struct pru_rproc - PRU remoteproc structure * @id: id of the PRU core within the PRUSS * @dev: PRU core device pointer * @pruss: back-reference to parent PRUSS structure * @rproc: remoteproc pointer for this PRU core + * @data: PRU core specific data * @mem_regions: data for each of the PRU memory regions * @fw_name: name of firmware image used during loading * @mapped_irq: virtual interrupt numbers of created fw specific mapping @@ -94,6 +124,7 @@ struct pru_rproc { struct device *dev; struct pruss *pruss; struct rproc *rproc; + const struct pru_private_data *data; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; const char *fw_name; unsigned int *mapped_irq; @@ -319,11 +350,12 @@ static int pru_rproc_start(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; int ret; - dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", - pru->id, (rproc->bootaddr >> 2)); + dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n", + names[pru->data->type], pru->id, (rproc->bootaddr >> 2)); ret = pru_handle_intrmap(rproc); /* @@ -345,9 +377,10 @@ static int pru_rproc_stop(struct rproc *rproc) { struct device *dev = &rproc->dev; struct pru_rproc *pru = rproc->priv; + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; u32 val; - dev_dbg(dev, "stopping PRU%d\n", pru->id); + dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id); val = pru_control_read_reg(pru, PRU_CTRL_CTRL); val &= ~CTRL_CTRL_EN; @@ -459,9 +492,52 @@ static struct rproc_ops pru_rproc_ops = { .da_to_va = pru_rproc_da_to_va, }; +/* + * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores + * + * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM + * memories, that is not seen on previous generation SoCs. The data is reflected + * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned + * copies result in all the other pre-existing bytes zeroed out within that + * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly used + * by ARM64 memcpy implementation) and throws an exception. The DRAM memory + * ports do not show this behavior. + */ +static int pru_rproc_memcpy(void *dest, const void *src, size_t count) +{ + const u32 *s = src; + u32 *d = dest; + size_t size = count / 4; + u32 *tmp_src = NULL; + + /* + * TODO: relax limitation of 4-byte aligned dest addresses and copy + * sizes + */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = kmemdup(src, count, GFP_KERNEL); + if (!tmp_src) + return -ENOMEM; + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + static int pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) { + struct pru_rproc *pru = rproc->priv; struct device *dev = &rproc->dev; struct elf32_hdr *ehdr; struct elf32_phdr *phdr; @@ -509,7 +585,17 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw) break; } - memcpy(ptr, elf_data + phdr->p_offset, filesz); + if (pru->data->is_k3 && is_iram) { + ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset, + filesz); + if (ret) { + dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } else { + memcpy(ptr, elf_data + phdr->p_offset, filesz); + } /* skip the memzero logic performed by remoteproc ELF loader */ } @@ -615,9 +701,17 @@ static int pru_rproc_set_id(struct pru_rproc *pru) int ret = 0; switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) { + case TX_PRU0_IRAM_ADDR_MASK: + fallthrough; + case RTU0_IRAM_ADDR_MASK: + fallthrough; case PRU0_IRAM_ADDR_MASK: pru->id = 0; break; + case TX_PRU1_IRAM_ADDR_MASK: + fallthrough; + case RTU1_IRAM_ADDR_MASK: + fallthrough; case PRU1_IRAM_ADDR_MASK: pru->id = 1; break; @@ -638,8 +732,13 @@ static int pru_rproc_probe(struct platform_device *pdev) struct rproc *rproc = NULL; struct resource *res; int i, ret; + const struct pru_private_data *data; const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" }; + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + ret = of_property_read_string(np, "firmware-name", &fw_name); if (ret) { dev_err(dev, "unable to retrieve firmware-name %d\n", ret); @@ -672,6 +771,7 @@ static int pru_rproc_probe(struct platform_device *pdev) pru = rproc->priv; pru->dev = dev; + pru->data = data; pru->pruss = platform_get_drvdata(ppdev); pru->rproc = rproc; pru->fw_name = fw_name; @@ -723,11 +823,33 @@ static int pru_rproc_remove(struct platform_device *pdev) return 0; } +static const struct pru_private_data pru_data = { + .type = PRU_TYPE_PRU, +}; + +static const struct pru_private_data k3_pru_data = { + .type = PRU_TYPE_PRU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_rtu_data = { + .type = PRU_TYPE_RTU, + .is_k3 = 1, +}; + +static const struct pru_private_data k3_tx_pru_data = { + .type = PRU_TYPE_TX_PRU, + .is_k3 = 1, +}; + static const struct of_device_id pru_rproc_match[] = { - { .compatible = "ti,am3356-pru", }, - { .compatible = "ti,am4376-pru", }, - { .compatible = "ti,am5728-pru", }, - { .compatible = "ti,k2g-pru", }, + { .compatible = "ti,am3356-pru", .data = &pru_data }, + { .compatible = "ti,am4376-pru", .data = &pru_data }, + { .compatible = "ti,am5728-pru", .data = &pru_data }, + { .compatible = "ti,k2g-pru", .data = &pru_data }, + { .compatible = "ti,am654-pru", .data = &k3_pru_data }, + { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, {}, }; MODULE_DEVICE_TABLE(of, pru_rproc_match); From patchwork Tue Dec 8 14:10:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 339743 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3722833jai; Tue, 8 Dec 2020 06:13:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJwfo7yheBK2Tx58RtALuVA8SjfvBIfc6dkWMhgDZGIabq637KPSoY6hC6iUV7jXfHchsNNK X-Received: by 2002:a17:906:77c5:: with SMTP id m5mr22660309ejn.424.1607436786638; Tue, 08 Dec 2020 06:13:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607436786; cv=none; d=google.com; s=arc-20160816; b=yaB+uJMoIpF9cS7b+1XSXu42+vaM4upnYQ07NNePTCaevJMmhbmNs4/i0Rwxsj9c+7 hQ9LvpX/amRQrX7Y+9vy26mPlfQ4wEmi2ULnrhxT3vnZDj4t+NN5W1nxnFXhj4sTVCBl qibvlhHXa3TUMlrtL/QTTQcMbshX0DeJ5X7QAKLxbz1W9J5zKgGPHMFV7ggCSY30tcoH Wjc15gLh9ADEm82PRxXQM7MNSMlCeavYhPwHvsWHUuwZzhKOq43bnP2ZFaojZywOnZ2z fYpYUcsm+VrH5jPFC6KYwmZ0UlWB3ba5THxTbI02JSIGSGUUnGrqaB4trxKtQ0Gm6HT9 LaXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2ColZvFMxeBX2F8jNmrJL1c8E3SYpy08jyj4gqYNN2Q=; b=RwCDvAH9+rjys3BHUptbUXXeTQYeWSzJlnD8QdcL2XTNbO2LW9h41TRxAXb/ZTeL4z EaQMZ9h86VtdslulV+qBx8+X/pBvNjDU0P2OFZQkhuI+8BsiRyL0Adp1gGfLwr9lejxk 1c7WCQEsQmk/ZbQVwZsq9zohl50smmGUtY49bc8/0LBdK2xzZmYIPrxyeeyyjk88GH5V Lh7CWKdXHX0+yuHhq/15Jh5XGvpx77gn9yN1hnZ4RNbcQ90N8mXjjCUM9ritz5jqVBi7 MA51msCvYUYsGan03sWGU4iB5+yxXgHsY5CP69/aYwrbtqxRZqSuyRjm59cUHwvnJbSc m/ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F/qSEHHi"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si5275960eju.331.2020.12.08.06.13.06; Tue, 08 Dec 2020 06:13:06 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F/qSEHHi"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729749AbgLHOMV (ORCPT + 6 others); Tue, 8 Dec 2020 09:12:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729752AbgLHOMQ (ORCPT ); Tue, 8 Dec 2020 09:12:16 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07AB7C0619D9 for ; Tue, 8 Dec 2020 06:10:49 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id x23so12569370lji.7 for ; Tue, 08 Dec 2020 06:10:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2ColZvFMxeBX2F8jNmrJL1c8E3SYpy08jyj4gqYNN2Q=; b=F/qSEHHimCf8rH5UvNdUHXdgEwBU/rlqYccUOT2bxodbri/gk8Sqdibs2NMzsEAzcO 4fhuiTBh6X4oPFv+D/gcuFPlTIPxOnCo4aG7Ug774m46ZqCtdh/SpQLhZupl49F9snVP NmCHLqUJtiVHRKBdHRKM+2zhZjQq/e0bc+w9x2tYgEAQzp6jMn+B34IavMEOChJn8xIS fcJsg60GI2pDYzfwYtgm15jMZ5Bx1KqMBii7Wc6NPAY/c3x6+WED5RWHnluhJ277kGvd fI17OZy2hTIKsgJk915wEy8Cm5yboxfD7X3jvKgO+whSRnemVeNclz5Cyb13d6StDetT XF5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2ColZvFMxeBX2F8jNmrJL1c8E3SYpy08jyj4gqYNN2Q=; b=dHRwTpIXZGkedU+naBdhoYczpobr8l5+aby8T14Az/s4W+8bgOHm1lyLoBB3x5EpDU PukrKmxn6TlV/213USjuH0mRsTQ1lm8s2+Az/G4ai+oyB2kLSHSA7faaA/KBTz9jqIgb Xr5stfxDM3HCb35DB/xhjjLSWd5wAd0ZeWfEtEY9GwqiT3ZCBUdJMczt/bIMYwAbdzJ7 eFrRnQkQ3hQcnZAahe68m6w0XYxvrSV3f2Of6DJVtWmduHvCWBmWDK/F1j2O0rYDHTVV KZ8bA4Mpw/C3mPL7xqZpAS9u7Qs7ZYjUIvzlzQflkPdPcHIAxXFTheCrv07jJPE37FZ9 F5yA== X-Gm-Message-State: AOAM530Gf8wRCP07Tl94s8ze3hD/0DFxipQlWNEHhIBT5MpR6zQ0IExM ty9HiU465BqHEQrJ+UNuvk0XkA== X-Received: by 2002:a05:651c:113c:: with SMTP id e28mr2820609ljo.252.1607436647436; Tue, 08 Dec 2020 06:10:47 -0800 (PST) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id h23sm417017ljh.115.2020.12.08.06.10.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2020 06:10:46 -0800 (PST) From: Grzegorz Jaszczyk To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, linux-remoteproc@vger.kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v4 6/6] remoteproc: pru: Add support for various PRU cores on K3 J721E SoCs Date: Tue, 8 Dec 2020 15:10:02 +0100 Message-Id: <20201208141002.17777-7-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> References: <20201208141002.17777-1-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The K3 J721E family of SoCs have a revised version of the AM65x ICSSG IP and contains two instances of this newer ICSSG IP. Each ICSSG processor subsystem contains 2 primary PRU cores, 2 auxiliary PRU cores called RTUs, and 2 new auxiliary cores called Transmit PRUs (Tx_PRUs). Enhance the existing PRU remoteproc driver to support these new PRU and RTU cores by using specific compatibles. The cores have the same memory copying limitations as on AM65x, so reuses the custom memcpy function within the driver's ELF loader implementation. The initial names for the firmware images for each PRU core are retrieved from DT nodes, and can be adjusted through sysfs if required. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Mathieu Poirier --- v3->v4: - No changes. v2->v3: - Add Reviewed-by: tag --- drivers/remoteproc/pru_rproc.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.29.0 diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 421ebbc1c02d..2667919d76b3 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -850,6 +850,9 @@ static const struct of_device_id pru_rproc_match[] = { { .compatible = "ti,am654-pru", .data = &k3_pru_data }, { .compatible = "ti,am654-rtu", .data = &k3_rtu_data }, { .compatible = "ti,am654-tx-pru", .data = &k3_tx_pru_data }, + { .compatible = "ti,j721e-pru", .data = &k3_pru_data }, + { .compatible = "ti,j721e-rtu", .data = &k3_rtu_data }, + { .compatible = "ti,j721e-tx-pru", .data = &k3_tx_pru_data }, {}, }; MODULE_DEVICE_TABLE(of, pru_rproc_match);